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$__gmon_start___ITM_deregisterTMCloneTable_ITM_registerTMCloneTable__cxa_finalize__cxa_atexitioctl__errno_location__stack_chk_failpthread_mutex_lockpthread_mutex_unlockmunmapmemcpymemsetpthread_onceclock_gettimepthread_cond_timedwaitmemcmpmmap64syscallmallocmemfd_createftruncate64reallocstderrfwrite__fprintf_chkstrerrorpthread_cond_broadcast__vsnprintf_chkdladdrdl_iterate_phdrstrcmp__snprintf_chkdrmGetDevice2drmFreeDevicestrncpydrmGetVersiondrmFreeVersionsysconfdrmSyncobjCreatedrmSyncobjWaitdrmGetCapdrmSyncobjDestroystrstrvk_common_CreateDevicevk_common_GetPhysicalDeviceDisplayPropertiesKHRvk_common_GetPhysicalDeviceDisplayPlanePropertiesKHRvk_common_GetDisplayPlaneSupportedDisplaysKHRvk_common_GetDisplayModePropertiesKHRvk_common_CreateDisplayModeKHRvk_common_GetDisplayPlaneCapabilitiesKHRvk_common_GetPhysicalDeviceSurfaceSupportKHRvk_common_GetPhysicalDeviceSurfaceCapabilitiesKHRvk_common_GetPhysicalDeviceSurfaceFormatsKHRvk_common_GetPhysicalDeviceSurfacePresentModesKHRvk_common_GetPhysicalDeviceWaylandPresentationSupportKHRvk_common_GetPhysicalDeviceXlibPresentationSupportKHRvk_common_GetPhysicalDeviceXcbPresentationSupportKHRvk_common_GetPhysicalDeviceExternalImageFormatPropertiesNVvk_common_GetPhysicalDeviceFeatures2KHRvk_common_GetPhysicalDeviceProperties2KHRvk_common_GetPhysicalDeviceFormatProperties2vk_common_GetPhysicalDeviceFormatProperties2KHRvk_common_GetPhysicalDeviceImageFormatProperties2vk_common_GetPhysicalDeviceImageFormatProperties2KHRvk_common_GetPhysicalDeviceQueueFamilyProperties2vk_common_GetPhysicalDeviceQueueFamilyProperties2KHRvk_common_GetPhysicalDeviceMemoryProperties2vk_common_GetPhysicalDeviceMemoryProperties2KHRvk_common_GetPhysicalDeviceSparseImageFormatProperties2vk_common_GetPhysicalDeviceSparseImageFormatProperties2KHRvk_common_GetPhysicalDeviceExternalBufferPropertiesvk_common_GetPhysicalDeviceExternalBufferPropertiesKHRvk_common_GetPhysicalDeviceExternalSemaphorePropertiesKHRvk_common_GetPhysicalDeviceExternalFencePropertiesKHRvk_common_ReleaseDisplayEXTvk_common_AcquireXlibDisplayEXTvk_common_GetRandROutputDisplayEXTvk_common_GetPhysicalDeviceSurfaceCapabilities2EXTvk_common_GetPhysicalDevicePresentRectanglesKHRvk_common_GetPhysicalDeviceMultisamplePropertiesEXTvk_common_GetPhysicalDeviceSurfaceCapabilities2KHRvk_common_GetPhysicalDeviceSurfaceFormats2KHRvk_common_GetPhysicalDeviceDisplayProperties2KHRvk_common_GetPhysicalDeviceDisplayPlaneProperties2KHRvk_common_GetDisplayModeProperties2KHRvk_common_GetDisplayPlaneCapabilities2KHRvk_common_GetPhysicalDeviceCalibrateableTimeDomainsKHRvk_common_GetPhysicalDeviceCalibrateableTimeDomainsEXTvk_common_GetPhysicalDeviceCooperativeMatrixPropertiesNVvk_common_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHRvk_common_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHRvk_common_GetPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNVvk_common_GetPhysicalDeviceToolPropertiesEXTvk_common_GetPhysicalDeviceFragmentShadingRatesKHRvk_common_GetPhysicalDeviceVideoCapabilitiesKHRvk_common_GetPhysicalDeviceVideoFormatPropertiesKHRvk_common_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHRvk_common_AcquireDrmDisplayEXTvk_common_GetDrmDisplayEXTvk_common_GetPhysicalDeviceOpticalFlowImageFormatsNVvk_common_GetPhysicalDeviceCooperativeMatrixPropertiesKHRwsi_GetPhysicalDevicePropertieswsi_GetPhysicalDeviceQueueFamilyPropertieswsi_GetPhysicalDeviceMemoryPropertieswsi_GetPhysicalDeviceFeatureswsi_GetPhysicalDeviceFormatPropertieswsi_GetPhysicalDeviceImageFormatPropertieswsi_CreateDevicewsi_EnumerateDeviceLayerPropertieswsi_EnumerateDeviceExtensionPropertieswsi_GetPhysicalDeviceSparseImageFormatPropertieswsi_GetPhysicalDeviceExternalImageFormatPropertiesNVwsi_GetPhysicalDeviceFeatures2wsi_GetPhysicalDeviceFeatures2KHRwsi_GetPhysicalDeviceProperties2wsi_GetPhysicalDeviceProperties2KHRwsi_GetPhysicalDeviceFormatProperties2wsi_GetPhysicalDeviceFormatProperties2KHRwsi_GetPhysicalDeviceImageFormatProperties2wsi_GetPhysicalDeviceImageFormatProperties2KHRwsi_GetPhysicalDeviceQueueFamilyProperties2wsi_GetPhysicalDeviceQueueFamilyProperties2KHRwsi_GetPhysicalDeviceMemoryProperties2wsi_GetPhysicalDeviceMemoryProperties2KHRwsi_GetPhysicalDeviceSparseImageFormatProperties2wsi_GetPhysicalDeviceSparseImageFormatProperties2KHRwsi_GetPhysicalDeviceExternalBufferPropertieswsi_GetPhysicalDeviceExternalBufferPropertiesKHRwsi_GetPhysicalDeviceExternalSemaphorePropertieswsi_GetPhysicalDeviceExternalSemaphorePropertiesKHRwsi_GetPhysicalDeviceExternalFencePropertieswsi_GetPhysicalDeviceExternalFencePropertiesKHRwsi_GetPhysicalDeviceMultisamplePropertiesEXTwsi_GetPhysicalDeviceCalibrateableTimeDomainsKHRwsi_GetPhysicalDeviceCalibrateableTimeDomainsEXTwsi_GetPhysicalDeviceCooperativeMatrixPropertiesNVwsi_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHRwsi_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHRwsi_GetPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNVwsi_GetPhysicalDeviceToolPropertieswsi_GetPhysicalDeviceToolPropertiesEXTwsi_GetPhysicalDeviceFragmentShadingRatesKHRwsi_GetPhysicalDeviceVideoCapabilitiesKHRwsi_GetPhysicalDeviceVideoFormatPropertiesKHRwsi_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHRwsi_GetPhysicalDeviceOpticalFlowImageFormatsNVwsi_GetPhysicalDeviceCooperativeMatrixPropertiesKHRanv_GetPhysicalDeviceQueueFamilyPropertiesanv_GetPhysicalDeviceFeaturesanv_GetPhysicalDeviceFormatPropertiesanv_EnumerateDeviceLayerPropertiesanv_EnumerateDeviceExtensionPropertiesanv_GetPhysicalDeviceDisplayPropertiesKHRanv_GetPhysicalDeviceDisplayPlanePropertiesKHRanv_GetDisplayPlaneSupportedDisplaysKHRanv_GetDisplayModePropertiesKHRanv_CreateDisplayModeKHRanv_GetDisplayPlaneCapabilitiesKHRanv_GetPhysicalDeviceSurfaceSupportKHRanv_GetPhysicalDeviceSurfaceCapabilitiesKHRanv_GetPhysicalDeviceSurfaceFormatsKHRanv_GetPhysicalDeviceSurfacePresentModesKHRanv_GetPhysicalDeviceWaylandPresentationSupportKHRanv_GetPhysicalDeviceXlibPresentationSupportKHRanv_GetPhysicalDeviceXcbPresentationSupportKHRanv_GetPhysicalDeviceExternalImageFormatPropertiesNVanv_GetPhysicalDeviceFeatures2anv_GetPhysicalDeviceFeatures2KHRanv_GetPhysicalDeviceProperties2KHRanv_GetPhysicalDeviceFormatProperties2KHRanv_GetPhysicalDeviceImageFormatProperties2KHRanv_GetPhysicalDeviceQueueFamilyProperties2KHRanv_GetPhysicalDeviceMemoryProperties2KHRanv_GetPhysicalDeviceSparseImageFormatProperties2KHRanv_GetPhysicalDeviceExternalBufferPropertiesKHRanv_GetPhysicalDeviceExternalSemaphorePropertiesanv_GetPhysicalDeviceExternalSemaphorePropertiesKHRanv_GetPhysicalDeviceExternalFencePropertiesanv_GetPhysicalDeviceExternalFencePropertiesKHRanv_ReleaseDisplayEXTanv_AcquireXlibDisplayEXTanv_GetRandROutputDisplayEXTanv_GetPhysicalDeviceSurfaceCapabilities2EXTanv_GetPhysicalDevicePresentRectanglesKHRanv_GetPhysicalDeviceSurfaceCapabilities2KHRanv_GetPhysicalDeviceSurfaceFormats2KHRanv_GetPhysicalDeviceDisplayProperties2KHRanv_GetPhysicalDeviceDisplayPlaneProperties2KHRanv_GetDisplayModeProperties2KHRanv_GetDisplayPlaneCapabilities2KHRanv_GetPhysicalDeviceCalibrateableTimeDomainsKHRanv_GetPhysicalDeviceCooperativeMatrixPropertiesNVanv_GetPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNVanv_GetPhysicalDeviceToolPropertiesanv_GetPhysicalDeviceToolPropertiesEXTanv_GetPhysicalDeviceFragmentShadingRatesKHRanv_GetPhysicalDeviceVideoCapabilitiesKHRanv_GetPhysicalDeviceVideoFormatPropertiesKHRanv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHRanv_AcquireDrmDisplayEXTanv_GetDrmDisplayEXTanv_GetPhysicalDeviceOpticalFlowImageFormatsNVanv_GetPhysicalDeviceCooperativeMatrixPropertiesKHRstrlenpthread_mutex_initstrtollsecure_getenvcallocstrdupabortpthread_mutex_destroystrtolfflushpthread_cond_destroylseek64vk_icdGetInstanceProcAddrvk_common_CreateInstancevk_common_DestroyInstancevk_common_GetInstanceProcAddrvk_common_EnumerateInstanceVersionvk_common_EnumerateInstanceLayerPropertiesvk_common_EnumerateInstanceExtensionPropertiesvk_common_CreateDisplayPlaneSurfaceKHRvk_common_DestroySurfaceKHRvk_common_CreateWaylandSurfaceKHRvk_common_CreateXlibSurfaceKHRvk_common_CreateXcbSurfaceKHRvk_common_EnumeratePhysicalDeviceGroupsKHRvk_common_CreateHeadlessSurfaceEXTwsi_CreateInstancewsi_DestroyInstancewsi_EnumeratePhysicalDeviceswsi_GetInstanceProcAddrwsi_EnumerateInstanceVersionwsi_EnumerateInstanceLayerPropertieswsi_EnumerateInstanceExtensionPropertieswsi_CreateDebugReportCallbackEXTwsi_DestroyDebugReportCallbackEXTwsi_DebugReportMessageEXTwsi_EnumeratePhysicalDeviceGroupswsi_EnumeratePhysicalDeviceGroupsKHRwsi_CreateDebugUtilsMessengerEXTwsi_DestroyDebugUtilsMessengerEXTwsi_SubmitDebugUtilsMessageEXTanv_EnumeratePhysicalDevicesanv_CreateDisplayPlaneSurfaceKHRanv_DestroySurfaceKHRanv_CreateWaylandSurfaceKHRanv_CreateXlibSurfaceKHRanv_CreateXcbSurfaceKHRanv_CreateDebugReportCallbackEXTanv_DestroyDebugReportCallbackEXTanv_DebugReportMessageEXTanv_EnumeratePhysicalDeviceGroupsanv_EnumeratePhysicalDeviceGroupsKHRanv_CreateDebugUtilsMessengerEXTanv_DestroyDebugUtilsMessengerEXTanv_SubmitDebugUtilsMessageEXTanv_CreateHeadlessSurfaceEXTpthread_cond_initpthread_condattr_initpthread_condattr_setclockpthread_condattr_destroyvk_common_DestroyDevicevk_common_AllocateMemoryvk_common_FreeMemoryvk_common_FlushMappedMemoryRangesvk_common_InvalidateMappedMemoryRangesvk_common_GetDeviceMemoryCommitmentvk_common_CreateEventvk_common_DestroyEventvk_common_GetEventStatusvk_common_SetEventvk_common_ResetEventvk_common_CreateQueryPoolvk_common_DestroyQueryPoolvk_common_GetQueryPoolResultsvk_common_ResetQueryPoolvk_common_ResetQueryPoolEXTvk_common_CreateBuffervk_common_DestroyBuffervk_common_CreateBufferViewvk_common_DestroyBufferViewvk_common_CreateImagevk_common_DestroyImagevk_common_CreateImageViewvk_common_DestroyImageViewvk_common_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIvk_common_CreateSamplervk_common_DestroySamplervk_common_CreateDescriptorSetLayoutvk_common_CreateDescriptorPoolvk_common_DestroyDescriptorPoolvk_common_ResetDescriptorPoolvk_common_AllocateDescriptorSetsvk_common_FreeDescriptorSetsvk_common_UpdateDescriptorSetsvk_common_BeginCommandBuffervk_common_EndCommandBuffervk_common_CmdDrawvk_common_CmdDrawIndexedvk_common_CmdDrawMultiEXTvk_common_CmdDrawMultiIndexedEXTvk_common_CmdDrawIndirectvk_common_CmdDrawIndexedIndirectvk_common_CmdDispatchIndirectvk_common_CmdSubpassShadingHUAWEIvk_common_CmdDrawClusterHUAWEIvk_common_CmdDrawClusterIndirectHUAWEIvk_common_CmdUpdatePipelineIndirectBufferNVvk_common_CmdCopyMemoryIndirectNVvk_common_CmdCopyMemoryToImageIndirectNVvk_common_CmdUpdateBuffervk_common_CmdFillBuffervk_common_CmdClearColorImagevk_common_CmdClearDepthStencilImagevk_common_CmdClearAttachmentsvk_common_CmdBeginConditionalRenderingEXTvk_common_CmdEndConditionalRenderingEXTvk_common_CmdResetQueryPoolvk_common_CmdCopyQueryPoolResultsvk_common_CreateSharedSwapchainsKHRvk_common_CreateSwapchainKHRvk_common_DestroySwapchainKHRvk_common_GetSwapchainImagesKHRvk_common_AcquireNextImageKHRvk_common_QueuePresentKHRvk_common_DebugMarkerSetObjectTagEXTvk_common_CmdDebugMarkerBeginEXTvk_common_CmdDebugMarkerEndEXTvk_common_CmdDebugMarkerInsertEXTvk_common_CmdExecuteGeneratedCommandsNVvk_common_CmdPreprocessGeneratedCommandsNVvk_common_CmdBindPipelineShaderGroupNVvk_common_GetGeneratedCommandsMemoryRequirementsNVvk_common_CreateIndirectCommandsLayoutNVvk_common_DestroyIndirectCommandsLayoutNVvk_common_TrimCommandPoolKHRvk_common_GetMemoryFdKHRvk_common_GetMemoryFdPropertiesKHRvk_common_GetMemoryRemoteAddressNVvk_common_DisplayPowerControlEXTvk_common_RegisterDeviceEventEXTvk_common_RegisterDisplayEventEXTvk_common_GetSwapchainCounterEXTvk_common_GetDeviceGroupPeerMemoryFeaturesKHRvk_common_BindBufferMemory2vk_common_BindBufferMemory2KHRvk_common_BindImageMemory2vk_common_BindImageMemory2KHRvk_common_CmdSetDeviceMaskKHRvk_common_GetDeviceGroupPresentCapabilitiesKHRvk_common_GetDeviceGroupSurfacePresentModesKHRvk_common_AcquireNextImage2KHRvk_common_CmdDispatchBasevk_common_CmdDispatchBaseKHRvk_common_CreateDescriptorUpdateTemplateKHRvk_common_DestroyDescriptorUpdateTemplateKHRvk_common_UpdateDescriptorSetWithTemplatevk_common_UpdateDescriptorSetWithTemplateKHRvk_common_SetHdrMetadataEXTvk_common_GetSwapchainStatusKHRvk_common_GetRefreshCycleDurationGOOGLEvk_common_GetPastPresentationTimingGOOGLEvk_common_CmdSetViewportWScalingNVvk_common_GetBufferMemoryRequirements2KHRvk_common_GetImageMemoryRequirements2vk_common_GetImageMemoryRequirements2KHRvk_common_GetImageSparseMemoryRequirements2vk_common_GetImageSparseMemoryRequirements2KHRvk_common_GetDeviceBufferMemoryRequirementsvk_common_GetDeviceBufferMemoryRequirementsKHRvk_common_GetDeviceImageMemoryRequirementsvk_common_GetDeviceImageMemoryRequirementsKHRvk_common_GetDeviceImageSparseMemoryRequirementsvk_common_GetDeviceImageSparseMemoryRequirementsKHRvk_common_CreateSamplerYcbcrConversionKHRvk_common_DestroySamplerYcbcrConversionKHRvk_common_CreateValidationCacheEXTvk_common_DestroyValidationCacheEXTvk_common_GetValidationCacheDataEXTvk_common_MergeValidationCachesEXTvk_common_GetDescriptorSetLayoutSupportvk_common_GetDescriptorSetLayoutSupportKHRvk_common_GetShaderInfoAMDvk_common_SetLocalDimmingAMDvk_common_GetCalibratedTimestampsKHRvk_common_GetCalibratedTimestampsEXTvk_common_GetMemoryHostPointerPropertiesEXTvk_common_CreateRenderPass2KHRvk_common_CmdBeginRenderPass2KHRvk_common_CmdNextSubpass2KHRvk_common_CmdEndRenderPass2KHRvk_common_GetSemaphoreCounterValueKHRvk_common_WaitSemaphoresKHRvk_common_SignalSemaphoreKHRvk_common_CmdDrawIndirectCountvk_common_CmdDrawIndirectCountKHRvk_common_CmdDrawIndirectCountAMDvk_common_CmdDrawIndexedIndirectCountvk_common_CmdDrawIndexedIndirectCountKHRvk_common_CmdDrawIndexedIndirectCountAMDvk_common_CmdSetCheckpointNVvk_common_CmdBindTransformFeedbackBuffersEXTvk_common_CmdBeginTransformFeedbackEXTvk_common_CmdEndTransformFeedbackEXTvk_common_CmdBeginQueryIndexedEXTvk_common_CmdEndQueryIndexedEXTvk_common_CmdDrawIndirectByteCountEXTvk_common_CmdSetExclusiveScissorNVvk_common_CmdSetExclusiveScissorEnableNVvk_common_CmdBindShadingRateImageNVvk_common_CmdSetViewportShadingRatePaletteNVvk_common_CmdSetCoarseSampleOrderNVvk_common_CmdDrawMeshTasksNVvk_common_CmdDrawMeshTasksIndirectNVvk_common_CmdDrawMeshTasksIndirectCountNVvk_common_CmdDrawMeshTasksEXTvk_common_CmdDrawMeshTasksIndirectEXTvk_common_CmdDrawMeshTasksIndirectCountEXTvk_common_CompileDeferredNVvk_common_CreateAccelerationStructureNVvk_common_CmdBindInvocationMaskHUAWEIvk_common_DestroyAccelerationStructureNVvk_common_GetAccelerationStructureMemoryRequirementsNVvk_common_BindAccelerationStructureMemoryNVvk_common_CmdCopyAccelerationStructureNVvk_common_CmdCopyAccelerationStructureKHRvk_common_CopyAccelerationStructureKHRvk_common_CmdCopyAccelerationStructureToMemoryKHRvk_common_CopyAccelerationStructureToMemoryKHRvk_common_CmdCopyMemoryToAccelerationStructureKHRvk_common_CopyMemoryToAccelerationStructureKHRvk_common_CmdWriteAccelerationStructuresPropertiesKHRvk_common_CmdWriteAccelerationStructuresPropertiesNVvk_common_CmdBuildAccelerationStructureNVvk_common_WriteAccelerationStructuresPropertiesKHRvk_common_CmdTraceRaysKHRvk_common_CmdTraceRaysNVvk_common_GetRayTracingShaderGroupHandlesKHRvk_common_GetRayTracingShaderGroupHandlesNVvk_common_GetRayTracingCaptureReplayShaderGroupHandlesKHRvk_common_GetAccelerationStructureHandleNVvk_common_CreateRayTracingPipelinesNVvk_common_CreateRayTracingPipelinesKHRvk_common_CmdTraceRaysIndirectKHRvk_common_CmdTraceRaysIndirect2KHRvk_common_GetDeviceAccelerationStructureCompatibilityKHRvk_common_GetRayTracingShaderGroupStackSizeKHRvk_common_CmdSetRayTracingPipelineStackSizeKHRvk_common_GetImageViewHandleNVXvk_common_GetImageViewAddressNVXvk_common_AcquireProfilingLockKHRvk_common_ReleaseProfilingLockKHRvk_common_GetBufferOpaqueCaptureAddressvk_common_GetBufferOpaqueCaptureAddressKHRvk_common_GetBufferDeviceAddressvk_common_GetBufferDeviceAddressKHRvk_common_GetBufferDeviceAddressEXTvk_common_InitializePerformanceApiINTELvk_common_UninitializePerformanceApiINTELvk_common_CmdSetPerformanceMarkerINTELvk_common_CmdSetPerformanceStreamMarkerINTELvk_common_CmdSetPerformanceOverrideINTELvk_common_AcquirePerformanceConfigurationINTELvk_common_ReleasePerformanceConfigurationINTELvk_common_QueueSetPerformanceConfigurationINTELvk_common_GetPerformanceParameterINTELvk_common_GetDeviceMemoryOpaqueCaptureAddressvk_common_GetDeviceMemoryOpaqueCaptureAddressKHRvk_common_CmdSetLineStippleEXTvk_common_CmdBuildAccelerationStructuresKHRvk_common_CmdBuildAccelerationStructuresIndirectKHRvk_common_BuildAccelerationStructuresKHRvk_common_GetPipelineIndirectMemoryRequirementsNVvk_common_GetPipelineIndirectDeviceAddressNVvk_common_CmdSetCullModeEXTvk_common_CmdSetFrontFaceEXTvk_common_CmdSetPrimitiveTopologyEXTvk_common_CmdSetViewportWithCountEXTvk_common_CmdSetScissorWithCountEXTvk_common_CmdBindIndexBuffer2KHRvk_common_CmdBindVertexBuffers2vk_common_CmdBindVertexBuffers2EXTvk_common_CmdSetDepthTestEnableEXTvk_common_CmdSetDepthWriteEnableEXTvk_common_CmdSetDepthCompareOpEXTvk_common_CmdSetDepthBoundsTestEnableEXTvk_common_CmdSetStencilTestEnableEXTvk_common_CmdSetStencilOpEXTvk_common_CmdSetRasterizerDiscardEnableEXTvk_common_CmdSetDepthBiasEnableEXTvk_common_CmdSetPrimitiveRestartEnableEXTvk_common_CreatePrivateDataSlotEXTvk_common_DestroyPrivateDataSlotEXTvk_common_SetPrivateDataEXTvk_common_GetPrivateDataEXTvk_common_CmdCopyBuffer2vk_common_CmdCopyBuffer2KHRvk_common_CmdCopyImage2vk_common_CmdCopyImage2KHRvk_common_CmdBlitImage2vk_common_CmdBlitImage2KHRvk_common_CmdCopyBufferToImage2vk_common_CmdCopyBufferToImage2KHRvk_common_CmdCopyImageToBuffer2vk_common_CmdCopyImageToBuffer2KHRvk_common_CmdResolveImage2vk_common_CmdResolveImage2KHRvk_common_CmdSetFragmentShadingRateEnumNVvk_common_GetAccelerationStructureBuildSizesKHRvk_common_CmdSetEvent2vk_common_CmdSetEvent2KHRvk_common_CmdResetEvent2vk_common_CmdResetEvent2KHRvk_common_CmdWaitEvents2vk_common_CmdWaitEvents2KHRvk_common_CmdPipelineBarrier2vk_common_CmdPipelineBarrier2KHRvk_common_QueueSubmit2KHRvk_common_CmdWriteTimestamp2vk_common_CmdWriteTimestamp2KHRvk_common_CmdWriteBufferMarker2AMDvk_common_GetQueueCheckpointData2NVvk_common_CopyMemoryToImageEXTvk_common_CopyImageToMemoryEXTvk_common_CopyImageToImageEXTvk_common_TransitionImageLayoutEXTvk_common_CreateVideoSessionKHRvk_common_DestroyVideoSessionKHRvk_common_CreateVideoSessionParametersKHRvk_common_UpdateVideoSessionParametersKHRvk_common_GetEncodedVideoSessionParametersKHRvk_common_DestroyVideoSessionParametersKHRvk_common_GetVideoSessionMemoryRequirementsKHRvk_common_BindVideoSessionMemoryKHRvk_common_CmdDecodeVideoKHRvk_common_CmdBeginVideoCodingKHRvk_common_CmdControlVideoCodingKHRvk_common_CmdEndVideoCodingKHRvk_common_CmdEncodeVideoKHRvk_common_CmdDecompressMemoryNVvk_common_CmdDecompressMemoryIndirectCountNVvk_common_CreateCuModuleNVXvk_common_CreateCuFunctionNVXvk_common_DestroyCuModuleNVXvk_common_DestroyCuFunctionNVXvk_common_CmdCuLaunchKernelNVXvk_common_GetDescriptorSetLayoutSizeEXTvk_common_GetDescriptorSetLayoutBindingOffsetEXTvk_common_GetDescriptorEXTvk_common_CmdBindDescriptorBuffersEXTvk_common_SetDeviceMemoryPriorityEXTvk_common_WaitForPresentKHRvk_common_CmdBeginRenderingvk_common_CmdBeginRenderingKHRvk_common_CmdEndRenderingvk_common_CmdEndRenderingKHRvk_common_GetDescriptorSetLayoutHostMappingInfoVALVEvk_common_GetDescriptorSetHostMappingVALVEvk_common_CreateMicromapEXTvk_common_CmdBuildMicromapsEXTvk_common_BuildMicromapsEXTvk_common_DestroyMicromapEXTvk_common_CmdCopyMicromapEXTvk_common_CopyMicromapEXTvk_common_CmdCopyMicromapToMemoryEXTvk_common_CopyMicromapToMemoryEXTvk_common_CmdCopyMemoryToMicromapEXTvk_common_CopyMemoryToMicromapEXTvk_common_CmdWriteMicromapsPropertiesEXTvk_common_WriteMicromapsPropertiesEXTvk_common_GetDeviceMicromapCompatibilityEXTvk_common_GetMicromapBuildSizesEXTvk_common_GetImageSubresourceLayout2KHRvk_common_GetImageSubresourceLayout2EXTvk_common_GetPipelinePropertiesEXTvk_common_GetFramebufferTilePropertiesQCOMvk_common_GetDynamicRenderingTilePropertiesQCOMvk_common_CreateOpticalFlowSessionNVvk_common_DestroyOpticalFlowSessionNVvk_common_BindOpticalFlowSessionImageNVvk_common_CmdOpticalFlowExecuteNVvk_common_GetDeviceFaultInfoEXTvk_common_ReleaseSwapchainImagesEXTvk_common_GetDeviceImageSubresourceLayoutKHRvk_common_MapMemory2KHRvk_common_UnmapMemory2KHRvk_common_CmdBindDescriptorSets2KHRvk_common_CmdPushConstants2KHRvk_common_CmdPushDescriptorSet2KHRvk_common_CmdPushDescriptorSetWithTemplate2KHRvk_common_CmdSetDescriptorBufferOffsets2EXTvk_common_CmdBindDescriptorBufferEmbeddedSamplers2EXTvk_common_SetLatencySleepModeNVvk_common_LatencySleepNVvk_common_SetLatencyMarkerNVvk_common_GetLatencyTimingsNVvk_common_QueueNotifyOutOfBandNVgfx8_GetDeviceProcAddrgfx8_DestroyDevicegfx8_GetDeviceQueuegfx8_QueueSubmitgfx8_QueueWaitIdlegfx8_DeviceWaitIdlegfx8_AllocateMemorygfx8_FreeMemorygfx8_MapMemorygfx8_UnmapMemorygfx8_FlushMappedMemoryRangesgfx8_InvalidateMappedMemoryRangesgfx8_GetDeviceMemoryCommitmentgfx8_GetBufferMemoryRequirementsgfx8_BindBufferMemorygfx8_GetImageMemoryRequirementsgfx8_BindImageMemorygfx8_GetImageSparseMemoryRequirementsgfx8_QueueBindSparsegfx8_CreateFencegfx8_DestroyFencegfx8_ResetFencesgfx8_GetFenceStatusgfx8_WaitForFencesgfx8_CreateSemaphoregfx8_DestroySemaphoregfx8_CreateEventgfx8_DestroyEventgfx8_GetEventStatusgfx8_SetEventgfx8_ResetEventgfx8_ResetQueryPoolEXTgfx8_CreateBuffergfx8_DestroyBuffergfx8_CreateBufferViewgfx8_DestroyBufferViewgfx8_CreateImagegfx8_DestroyImagegfx8_GetImageSubresourceLayoutgfx8_CreateImageViewgfx8_DestroyImageViewgfx8_CreateShaderModulegfx8_DestroyShaderModulegfx8_CreatePipelineCachegfx8_DestroyPipelineCachegfx8_GetPipelineCacheDatagfx8_MergePipelineCachesgfx8_CreateGraphicsPipelinesgfx8_CreateComputePipelinesgfx8_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIgfx8_DestroyPipelinegfx8_CreatePipelineLayoutgfx8_DestroyPipelineLayoutgfx8_DestroySamplergfx8_CreateDescriptorSetLayoutgfx8_DestroyDescriptorSetLayoutgfx8_CreateDescriptorPoolgfx8_DestroyDescriptorPoolgfx8_ResetDescriptorPoolgfx8_AllocateDescriptorSetsgfx8_FreeDescriptorSetsgfx8_UpdateDescriptorSetsgfx8_CreateFramebuffergfx8_DestroyFramebuffergfx8_CreateRenderPassgfx8_DestroyRenderPassgfx8_GetRenderAreaGranularitygfx8_GetRenderingAreaGranularityKHRgfx8_CreateCommandPoolgfx8_DestroyCommandPoolgfx8_ResetCommandPoolgfx8_AllocateCommandBuffersgfx8_FreeCommandBuffersgfx8_ResetCommandBuffergfx8_CmdBindPipelinegfx8_CmdSetAttachmentFeedbackLoopEnableEXTgfx8_CmdSetViewportgfx8_CmdSetScissorgfx8_CmdSetLineWidthgfx8_CmdSetDepthBiasgfx8_CmdSetBlendConstantsgfx8_CmdSetDepthBoundsgfx8_CmdSetStencilCompareMaskgfx8_CmdSetStencilWriteMaskgfx8_CmdSetStencilReferencegfx8_CmdBindDescriptorSetsgfx8_CmdBindVertexBuffersgfx8_CmdDispatchgfx8_CmdSubpassShadingHUAWEIgfx8_CmdDrawClusterHUAWEIgfx8_CmdDrawClusterIndirectHUAWEIgfx8_CmdUpdatePipelineIndirectBufferNVgfx8_CmdCopyBuffergfx8_CmdCopyImagegfx8_CmdBlitImagegfx8_CmdCopyBufferToImagegfx8_CmdCopyImageToBuffergfx8_CmdCopyMemoryIndirectNVgfx8_CmdCopyMemoryToImageIndirectNVgfx8_CmdUpdateBuffergfx8_CmdFillBuffergfx8_CmdClearColorImagegfx8_CmdClearDepthStencilImagegfx8_CmdClearAttachmentsgfx8_CmdResolveImagegfx8_CmdSetEventgfx8_CmdResetEventgfx8_CmdWaitEventsgfx8_CmdPipelineBarriergfx8_CmdWriteTimestampgfx8_CmdPushConstantsgfx8_CmdBeginRenderPassgfx8_CmdNextSubpassgfx8_CmdEndRenderPassgfx8_CreateSharedSwapchainsKHRgfx8_CreateSwapchainKHRgfx8_DestroySwapchainKHRgfx8_GetSwapchainImagesKHRgfx8_AcquireNextImageKHRgfx8_QueuePresentKHRgfx8_DebugMarkerSetObjectNameEXTgfx8_DebugMarkerSetObjectTagEXTgfx8_CmdDebugMarkerBeginEXTgfx8_CmdDebugMarkerEndEXTgfx8_CmdDebugMarkerInsertEXTgfx8_CmdExecuteGeneratedCommandsNVgfx8_CmdPreprocessGeneratedCommandsNVgfx8_CmdBindPipelineShaderGroupNVgfx8_GetGeneratedCommandsMemoryRequirementsNVgfx8_CreateIndirectCommandsLayoutNVgfx8_DestroyIndirectCommandsLayoutNVgfx8_CmdPushDescriptorSetKHRgfx8_TrimCommandPoolgfx8_TrimCommandPoolKHRgfx8_GetMemoryFdKHRgfx8_GetMemoryFdPropertiesKHRgfx8_GetMemoryRemoteAddressNVgfx8_GetSemaphoreFdKHRgfx8_ImportSemaphoreFdKHRgfx8_GetFenceFdKHRgfx8_ImportFenceFdKHRgfx8_DisplayPowerControlEXTgfx8_RegisterDeviceEventEXTgfx8_RegisterDisplayEventEXTgfx8_GetSwapchainCounterEXTgfx8_GetDeviceGroupPeerMemoryFeaturesgfx8_GetDeviceGroupPeerMemoryFeaturesKHRgfx8_BindBufferMemory2gfx8_BindBufferMemory2KHRgfx8_BindImageMemory2gfx8_BindImageMemory2KHRgfx8_CmdSetDeviceMaskgfx8_CmdSetDeviceMaskKHRgfx8_GetDeviceGroupPresentCapabilitiesKHRgfx8_GetDeviceGroupSurfacePresentModesKHRgfx8_AcquireNextImage2KHRgfx8_CmdDispatchBaseKHRgfx8_CreateDescriptorUpdateTemplategfx8_CreateDescriptorUpdateTemplateKHRgfx8_DestroyDescriptorUpdateTemplategfx8_DestroyDescriptorUpdateTemplateKHRgfx8_UpdateDescriptorSetWithTemplategfx8_UpdateDescriptorSetWithTemplateKHRgfx8_CmdPushDescriptorSetWithTemplateKHRgfx8_SetHdrMetadataEXTgfx8_GetSwapchainStatusKHRgfx8_GetRefreshCycleDurationGOOGLEgfx8_GetPastPresentationTimingGOOGLEgfx8_CmdSetViewportWScalingNVgfx8_CmdSetDiscardRectangleEXTgfx8_CmdSetDiscardRectangleEnableEXTgfx8_CmdSetDiscardRectangleModeEXTgfx8_CmdSetSampleLocationsEXTgfx8_GetBufferMemoryRequirements2gfx8_GetBufferMemoryRequirements2KHRgfx8_GetImageMemoryRequirements2gfx8_GetImageMemoryRequirements2KHRgfx8_GetImageSparseMemoryRequirements2gfx8_GetImageSparseMemoryRequirements2KHRgfx8_GetDeviceBufferMemoryRequirementsgfx8_GetDeviceBufferMemoryRequirementsKHRgfx8_GetDeviceImageMemoryRequirementsgfx8_GetDeviceImageMemoryRequirementsKHRgfx8_GetDeviceImageSparseMemoryRequirementsgfx8_GetDeviceImageSparseMemoryRequirementsKHRgfx8_CreateSamplerYcbcrConversiongfx8_CreateSamplerYcbcrConversionKHRgfx8_DestroySamplerYcbcrConversiongfx8_DestroySamplerYcbcrConversionKHRgfx8_GetDeviceQueue2gfx8_CreateValidationCacheEXTgfx8_DestroyValidationCacheEXTgfx8_GetValidationCacheDataEXTgfx8_MergeValidationCachesEXTgfx8_GetDescriptorSetLayoutSupportgfx8_GetDescriptorSetLayoutSupportKHRgfx8_GetShaderInfoAMDgfx8_SetLocalDimmingAMDgfx8_GetCalibratedTimestampsKHRgfx8_GetCalibratedTimestampsEXTgfx8_SetDebugUtilsObjectNameEXTgfx8_SetDebugUtilsObjectTagEXTgfx8_QueueBeginDebugUtilsLabelEXTgfx8_QueueEndDebugUtilsLabelEXTgfx8_QueueInsertDebugUtilsLabelEXTgfx8_CmdBeginDebugUtilsLabelEXTgfx8_CmdEndDebugUtilsLabelEXTgfx8_CmdInsertDebugUtilsLabelEXTgfx8_GetMemoryHostPointerPropertiesEXTgfx8_CmdWriteBufferMarkerAMDgfx8_CreateRenderPass2gfx8_CreateRenderPass2KHRgfx8_CmdBeginRenderPass2gfx8_CmdBeginRenderPass2KHRgfx8_CmdNextSubpass2gfx8_CmdNextSubpass2KHRgfx8_CmdEndRenderPass2gfx8_CmdEndRenderPass2KHRgfx8_GetSemaphoreCounterValuegfx8_GetSemaphoreCounterValueKHRgfx8_WaitSemaphoresgfx8_WaitSemaphoresKHRgfx8_SignalSemaphoregfx8_SignalSemaphoreKHRgfx8_CmdDrawIndirectCountKHRgfx8_CmdDrawIndirectCountAMDgfx8_CmdDrawIndexedIndirectCountKHRgfx8_CmdDrawIndexedIndirectCountAMDgfx8_CmdSetCheckpointNVgfx8_GetQueueCheckpointDataNVgfx8_CmdBindTransformFeedbackBuffersEXTgfx8_CmdSetExclusiveScissorNVgfx8_CmdSetExclusiveScissorEnableNVgfx8_CmdBindShadingRateImageNVgfx8_CmdSetViewportShadingRatePaletteNVgfx8_CmdSetCoarseSampleOrderNVgfx8_CmdDrawMeshTasksNVgfx8_CmdDrawMeshTasksIndirectNVgfx8_CmdDrawMeshTasksIndirectCountNVgfx8_CmdDrawMeshTasksEXTgfx8_CmdDrawMeshTasksIndirectEXTgfx8_CmdDrawMeshTasksIndirectCountEXTgfx8_CompileDeferredNVgfx8_CreateAccelerationStructureNVgfx8_CmdBindInvocationMaskHUAWEIgfx8_DestroyAccelerationStructureKHRgfx8_DestroyAccelerationStructureNVgfx8_GetAccelerationStructureMemoryRequirementsNVgfx8_BindAccelerationStructureMemoryNVgfx8_CmdCopyAccelerationStructureNVgfx8_CmdCopyAccelerationStructureKHRgfx8_CopyAccelerationStructureKHRgfx8_CmdCopyAccelerationStructureToMemoryKHRgfx8_CopyAccelerationStructureToMemoryKHRgfx8_CmdCopyMemoryToAccelerationStructureKHRgfx8_CopyMemoryToAccelerationStructureKHRgfx8_CmdWriteAccelerationStructuresPropertiesKHRgfx8_CmdWriteAccelerationStructuresPropertiesNVgfx8_CmdBuildAccelerationStructureNVgfx8_WriteAccelerationStructuresPropertiesKHRgfx8_CmdTraceRaysKHRgfx8_CmdTraceRaysNVgfx8_GetRayTracingShaderGroupHandlesKHRgfx8_GetRayTracingShaderGroupHandlesNVgfx8_GetRayTracingCaptureReplayShaderGroupHandlesKHRgfx8_GetAccelerationStructureHandleNVgfx8_CreateRayTracingPipelinesNVgfx8_CreateRayTracingPipelinesKHRgfx8_CmdTraceRaysIndirectKHRgfx8_CmdTraceRaysIndirect2KHRgfx8_GetDeviceAccelerationStructureCompatibilityKHRgfx8_GetRayTracingShaderGroupStackSizeKHRgfx8_CmdSetRayTracingPipelineStackSizeKHRgfx8_GetImageViewHandleNVXgfx8_GetImageViewAddressNVXgfx8_AcquireProfilingLockKHRgfx8_ReleaseProfilingLockKHRgfx8_GetImageDrmFormatModifierPropertiesEXTgfx8_GetBufferOpaqueCaptureAddressgfx8_GetBufferOpaqueCaptureAddressKHRgfx8_GetBufferDeviceAddressgfx8_GetBufferDeviceAddressKHRgfx8_GetBufferDeviceAddressEXTgfx8_InitializePerformanceApiINTELgfx8_UninitializePerformanceApiINTELgfx8_CmdSetPerformanceMarkerINTELgfx8_AcquirePerformanceConfigurationINTELgfx8_ReleasePerformanceConfigurationINTELgfx8_QueueSetPerformanceConfigurationINTELgfx8_GetPerformanceParameterINTELgfx8_GetDeviceMemoryOpaqueCaptureAddressgfx8_GetDeviceMemoryOpaqueCaptureAddressKHRgfx8_GetPipelineExecutablePropertiesKHRgfx8_GetPipelineExecutableStatisticsKHRgfx8_GetPipelineExecutableInternalRepresentationsKHRgfx8_CmdSetLineStippleKHRgfx8_CmdSetLineStippleEXTgfx8_CreateAccelerationStructureKHRgfx8_CmdBuildAccelerationStructuresKHRgfx8_CmdBuildAccelerationStructuresIndirectKHRgfx8_BuildAccelerationStructuresKHRgfx8_GetAccelerationStructureDeviceAddressKHRgfx8_CreateDeferredOperationKHRgfx8_DestroyDeferredOperationKHRgfx8_GetDeferredOperationMaxConcurrencyKHRgfx8_GetDeferredOperationResultKHRgfx8_DeferredOperationJoinKHRgfx8_GetPipelineIndirectMemoryRequirementsNVgfx8_GetPipelineIndirectDeviceAddressNVgfx8_CmdSetCullModegfx8_CmdSetCullModeEXTgfx8_CmdSetFrontFacegfx8_CmdSetFrontFaceEXTgfx8_CmdSetPrimitiveTopologygfx8_CmdSetPrimitiveTopologyEXTgfx8_CmdSetViewportWithCountgfx8_CmdSetViewportWithCountEXTgfx8_CmdSetScissorWithCountgfx8_CmdSetScissorWithCountEXTgfx8_CmdBindIndexBuffer2KHRgfx8_CmdBindVertexBuffers2gfx8_CmdBindVertexBuffers2EXTgfx8_CmdSetDepthTestEnablegfx8_CmdSetDepthTestEnableEXTgfx8_CmdSetDepthWriteEnablegfx8_CmdSetDepthWriteEnableEXTgfx8_CmdSetDepthCompareOpgfx8_CmdSetDepthCompareOpEXTgfx8_CmdSetDepthBoundsTestEnablegfx8_CmdSetDepthBoundsTestEnableEXTgfx8_CmdSetStencilTestEnablegfx8_CmdSetStencilTestEnableEXTgfx8_CmdSetStencilOpgfx8_CmdSetStencilOpEXTgfx8_CmdSetPatchControlPointsEXTgfx8_CmdSetRasterizerDiscardEnablegfx8_CmdSetRasterizerDiscardEnableEXTgfx8_CmdSetDepthBiasEnablegfx8_CmdSetDepthBiasEnableEXTgfx8_CmdSetLogicOpEXTgfx8_CmdSetPrimitiveRestartEnablegfx8_CmdSetPrimitiveRestartEnableEXTgfx8_CmdSetTessellationDomainOriginEXTgfx8_CmdSetDepthClampEnableEXTgfx8_CmdSetPolygonModeEXTgfx8_CmdSetRasterizationSamplesEXTgfx8_CmdSetSampleMaskEXTgfx8_CmdSetAlphaToCoverageEnableEXTgfx8_CmdSetAlphaToOneEnableEXTgfx8_CmdSetLogicOpEnableEXTgfx8_CmdSetColorBlendEnableEXTgfx8_CmdSetColorBlendEquationEXTgfx8_CmdSetColorWriteMaskEXTgfx8_CmdSetRasterizationStreamEXTgfx8_CmdSetConservativeRasterizationModeEXTgfx8_CmdSetExtraPrimitiveOverestimationSizeEXTgfx8_CmdSetDepthClipEnableEXTgfx8_CmdSetSampleLocationsEnableEXTgfx8_CmdSetColorBlendAdvancedEXTgfx8_CmdSetProvokingVertexModeEXTgfx8_CmdSetLineRasterizationModeEXTgfx8_CmdSetLineStippleEnableEXTgfx8_CmdSetDepthClipNegativeOneToOneEXTgfx8_CmdSetViewportWScalingEnableNVgfx8_CmdSetViewportSwizzleNVgfx8_CmdSetCoverageToColorEnableNVgfx8_CmdSetCoverageToColorLocationNVgfx8_CmdSetCoverageModulationModeNVgfx8_CmdSetCoverageModulationTableEnableNVgfx8_CmdSetCoverageModulationTableNVgfx8_CmdSetShadingRateImageEnableNVgfx8_CmdSetCoverageReductionModeNVgfx8_CmdSetRepresentativeFragmentTestEnableNVgfx8_CreatePrivateDataSlotgfx8_CreatePrivateDataSlotEXTgfx8_DestroyPrivateDataSlotgfx8_DestroyPrivateDataSlotEXTgfx8_SetPrivateDatagfx8_SetPrivateDataEXTgfx8_GetPrivateDatagfx8_GetPrivateDataEXTgfx8_CmdCopyBuffer2gfx8_CmdCopyBuffer2KHRgfx8_CmdCopyImage2gfx8_CmdCopyImage2KHRgfx8_CmdBlitImage2gfx8_CmdBlitImage2KHRgfx8_CmdCopyBufferToImage2gfx8_CmdCopyBufferToImage2KHRgfx8_CmdCopyImageToBuffer2gfx8_CmdCopyImageToBuffer2KHRgfx8_CmdResolveImage2gfx8_CmdResolveImage2KHRgfx8_CmdSetFragmentShadingRateKHRgfx8_CmdSetFragmentShadingRateEnumNVgfx8_GetAccelerationStructureBuildSizesKHRgfx8_CmdSetVertexInputEXTgfx8_CmdSetColorWriteEnableEXTgfx8_CmdSetEvent2KHRgfx8_CmdResetEvent2KHRgfx8_CmdWaitEvents2KHRgfx8_CmdPipelineBarrier2KHRgfx8_QueueSubmit2gfx8_QueueSubmit2KHRgfx8_CmdWriteTimestamp2KHRgfx8_CmdWriteBufferMarker2AMDgfx8_GetQueueCheckpointData2NVgfx8_CopyMemoryToImageEXTgfx8_CopyImageToMemoryEXTgfx8_CopyImageToImageEXTgfx8_TransitionImageLayoutEXTgfx8_CreateVideoSessionKHRgfx8_DestroyVideoSessionKHRgfx8_CreateVideoSessionParametersKHRgfx8_UpdateVideoSessionParametersKHRgfx8_GetEncodedVideoSessionParametersKHRgfx8_DestroyVideoSessionParametersKHRgfx8_GetVideoSessionMemoryRequirementsKHRgfx8_BindVideoSessionMemoryKHRgfx8_CmdDecodeVideoKHRgfx8_CmdBeginVideoCodingKHRgfx8_CmdControlVideoCodingKHRgfx8_CmdEndVideoCodingKHRgfx8_CmdEncodeVideoKHRgfx8_CmdDecompressMemoryNVgfx8_CmdDecompressMemoryIndirectCountNVgfx8_CreateCuModuleNVXgfx8_CreateCuFunctionNVXgfx8_DestroyCuModuleNVXgfx8_DestroyCuFunctionNVXgfx8_CmdCuLaunchKernelNVXgfx8_GetDescriptorSetLayoutSizeEXTgfx8_GetDescriptorSetLayoutBindingOffsetEXTgfx8_GetDescriptorEXTgfx8_CmdBindDescriptorBuffersEXTgfx8_CmdSetDescriptorBufferOffsetsEXTgfx8_CmdBindDescriptorBufferEmbeddedSamplersEXTgfx8_GetBufferOpaqueCaptureDescriptorDataEXTgfx8_GetImageOpaqueCaptureDescriptorDataEXTgfx8_GetImageViewOpaqueCaptureDescriptorDataEXTgfx8_GetSamplerOpaqueCaptureDescriptorDataEXTgfx8_GetAccelerationStructureOpaqueCaptureDescriptorDataEXTgfx8_SetDeviceMemoryPriorityEXTgfx8_WaitForPresentKHRgfx8_CmdBeginRenderingKHRgfx8_CmdEndRenderingKHRgfx8_GetDescriptorSetLayoutHostMappingInfoVALVEgfx8_GetDescriptorSetHostMappingVALVEgfx8_CreateMicromapEXTgfx8_CmdBuildMicromapsEXTgfx8_BuildMicromapsEXTgfx8_DestroyMicromapEXTgfx8_CmdCopyMicromapEXTgfx8_CopyMicromapEXTgfx8_CmdCopyMicromapToMemoryEXTgfx8_CopyMicromapToMemoryEXTgfx8_CmdCopyMemoryToMicromapEXTgfx8_CopyMemoryToMicromapEXTgfx8_CmdWriteMicromapsPropertiesEXTgfx8_WriteMicromapsPropertiesEXTgfx8_GetDeviceMicromapCompatibilityEXTgfx8_GetMicromapBuildSizesEXTgfx8_GetShaderModuleIdentifierEXTgfx8_GetShaderModuleCreateInfoIdentifierEXTgfx8_GetImageSubresourceLayout2KHRgfx8_GetImageSubresourceLayout2EXTgfx8_GetPipelinePropertiesEXTgfx8_GetFramebufferTilePropertiesQCOMgfx8_GetDynamicRenderingTilePropertiesQCOMgfx8_CreateOpticalFlowSessionNVgfx8_DestroyOpticalFlowSessionNVgfx8_BindOpticalFlowSessionImageNVgfx8_CmdOpticalFlowExecuteNVgfx8_GetDeviceFaultInfoEXTgfx8_CmdSetDepthBias2EXTgfx8_ReleaseSwapchainImagesEXTgfx8_GetDeviceImageSubresourceLayoutKHRgfx8_MapMemory2KHRgfx8_UnmapMemory2KHRgfx8_CreateShadersEXTgfx8_DestroyShaderEXTgfx8_GetShaderBinaryDataEXTgfx8_CmdBindShadersEXTgfx8_CmdBindDescriptorSets2KHRgfx8_CmdPushConstants2KHRgfx8_CmdPushDescriptorSet2KHRgfx8_CmdPushDescriptorSetWithTemplate2KHRgfx8_CmdSetDescriptorBufferOffsets2EXTgfx8_CmdBindDescriptorBufferEmbeddedSamplers2EXTgfx8_SetLatencySleepModeNVgfx8_LatencySleepNVgfx8_SetLatencyMarkerNVgfx8_GetLatencyTimingsNVgfx8_QueueNotifyOutOfBandNVgfx8_CmdSetRenderingAttachmentLocationsKHRgfx8_CmdSetRenderingInputAttachmentIndicesKHRgfx75_GetDeviceProcAddrgfx75_DestroyDevicegfx75_GetDeviceQueuegfx75_QueueSubmitgfx75_QueueWaitIdlegfx75_DeviceWaitIdlegfx75_AllocateMemorygfx75_FreeMemorygfx75_MapMemorygfx75_UnmapMemorygfx75_FlushMappedMemoryRangesgfx75_InvalidateMappedMemoryRangesgfx75_GetDeviceMemoryCommitmentgfx75_GetBufferMemoryRequirementsgfx75_BindBufferMemorygfx75_GetImageMemoryRequirementsgfx75_BindImageMemorygfx75_GetImageSparseMemoryRequirementsgfx75_QueueBindSparsegfx75_CreateFencegfx75_DestroyFencegfx75_ResetFencesgfx75_GetFenceStatusgfx75_WaitForFencesgfx75_CreateSemaphoregfx75_DestroySemaphoregfx75_CreateEventgfx75_DestroyEventgfx75_GetEventStatusgfx75_SetEventgfx75_ResetEventgfx75_ResetQueryPoolEXTgfx75_CreateBuffergfx75_DestroyBuffergfx75_CreateBufferViewgfx75_DestroyBufferViewgfx75_CreateImagegfx75_DestroyImagegfx75_GetImageSubresourceLayoutgfx75_CreateImageViewgfx75_DestroyImageViewgfx75_CreateShaderModulegfx75_DestroyShaderModulegfx75_CreatePipelineCachegfx75_DestroyPipelineCachegfx75_GetPipelineCacheDatagfx75_MergePipelineCachesgfx75_CreateGraphicsPipelinesgfx75_CreateComputePipelinesgfx75_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIgfx75_DestroyPipelinegfx75_CreatePipelineLayoutgfx75_DestroyPipelineLayoutgfx75_DestroySamplergfx75_CreateDescriptorSetLayoutgfx75_DestroyDescriptorSetLayoutgfx75_CreateDescriptorPoolgfx75_DestroyDescriptorPoolgfx75_ResetDescriptorPoolgfx75_AllocateDescriptorSetsgfx75_FreeDescriptorSetsgfx75_UpdateDescriptorSetsgfx75_CreateFramebuffergfx75_DestroyFramebuffergfx75_CreateRenderPassgfx75_DestroyRenderPassgfx75_GetRenderAreaGranularitygfx75_GetRenderingAreaGranularityKHRgfx75_CreateCommandPoolgfx75_DestroyCommandPoolgfx75_ResetCommandPoolgfx75_AllocateCommandBuffersgfx75_FreeCommandBuffersgfx75_ResetCommandBuffergfx75_CmdBindPipelinegfx75_CmdSetAttachmentFeedbackLoopEnableEXTgfx75_CmdSetViewportgfx75_CmdSetScissorgfx75_CmdSetLineWidthgfx75_CmdSetDepthBiasgfx75_CmdSetBlendConstantsgfx75_CmdSetDepthBoundsgfx75_CmdSetStencilCompareMaskgfx75_CmdSetStencilWriteMaskgfx75_CmdSetStencilReferencegfx75_CmdBindDescriptorSetsgfx75_CmdBindVertexBuffersgfx75_CmdDispatchgfx75_CmdSubpassShadingHUAWEIgfx75_CmdDrawClusterHUAWEIgfx75_CmdDrawClusterIndirectHUAWEIgfx75_CmdUpdatePipelineIndirectBufferNVgfx75_CmdCopyBuffergfx75_CmdCopyImagegfx75_CmdBlitImagegfx75_CmdCopyBufferToImagegfx75_CmdCopyImageToBuffergfx75_CmdCopyMemoryIndirectNVgfx75_CmdCopyMemoryToImageIndirectNVgfx75_CmdUpdateBuffergfx75_CmdFillBuffergfx75_CmdClearColorImagegfx75_CmdClearDepthStencilImagegfx75_CmdClearAttachmentsgfx75_CmdResolveImagegfx75_CmdSetEventgfx75_CmdResetEventgfx75_CmdWaitEventsgfx75_CmdPipelineBarriergfx75_CmdWriteTimestampgfx75_CmdPushConstantsgfx75_CmdBeginRenderPassgfx75_CmdNextSubpassgfx75_CmdEndRenderPassgfx75_CreateSharedSwapchainsKHRgfx75_CreateSwapchainKHRgfx75_DestroySwapchainKHRgfx75_GetSwapchainImagesKHRgfx75_AcquireNextImageKHRgfx75_QueuePresentKHRgfx75_DebugMarkerSetObjectNameEXTgfx75_DebugMarkerSetObjectTagEXTgfx75_CmdDebugMarkerBeginEXTgfx75_CmdDebugMarkerEndEXTgfx75_CmdDebugMarkerInsertEXTgfx75_CmdExecuteGeneratedCommandsNVgfx75_CmdPreprocessGeneratedCommandsNVgfx75_CmdBindPipelineShaderGroupNVgfx75_GetGeneratedCommandsMemoryRequirementsNVgfx75_CreateIndirectCommandsLayoutNVgfx75_DestroyIndirectCommandsLayoutNVgfx75_CmdPushDescriptorSetKHRgfx75_TrimCommandPoolgfx75_TrimCommandPoolKHRgfx75_GetMemoryFdKHRgfx75_GetMemoryFdPropertiesKHRgfx75_GetMemoryRemoteAddressNVgfx75_GetSemaphoreFdKHRgfx75_ImportSemaphoreFdKHRgfx75_GetFenceFdKHRgfx75_ImportFenceFdKHRgfx75_DisplayPowerControlEXTgfx75_RegisterDeviceEventEXTgfx75_RegisterDisplayEventEXTgfx75_GetSwapchainCounterEXTgfx75_GetDeviceGroupPeerMemoryFeaturesgfx75_GetDeviceGroupPeerMemoryFeaturesKHRgfx75_BindBufferMemory2gfx75_BindBufferMemory2KHRgfx75_BindImageMemory2gfx75_BindImageMemory2KHRgfx75_CmdSetDeviceMaskgfx75_CmdSetDeviceMaskKHRgfx75_GetDeviceGroupPresentCapabilitiesKHRgfx75_GetDeviceGroupSurfacePresentModesKHRgfx75_AcquireNextImage2KHRgfx75_CmdDispatchBaseKHRgfx75_CreateDescriptorUpdateTemplategfx75_CreateDescriptorUpdateTemplateKHRgfx75_DestroyDescriptorUpdateTemplategfx75_DestroyDescriptorUpdateTemplateKHRgfx75_UpdateDescriptorSetWithTemplategfx75_UpdateDescriptorSetWithTemplateKHRgfx75_CmdPushDescriptorSetWithTemplateKHRgfx75_SetHdrMetadataEXTgfx75_GetSwapchainStatusKHRgfx75_GetRefreshCycleDurationGOOGLEgfx75_GetPastPresentationTimingGOOGLEgfx75_CmdSetViewportWScalingNVgfx75_CmdSetDiscardRectangleEXTgfx75_CmdSetDiscardRectangleEnableEXTgfx75_CmdSetDiscardRectangleModeEXTgfx75_CmdSetSampleLocationsEXTgfx75_GetBufferMemoryRequirements2gfx75_GetBufferMemoryRequirements2KHRgfx75_GetImageMemoryRequirements2gfx75_GetImageMemoryRequirements2KHRgfx75_GetImageSparseMemoryRequirements2gfx75_GetImageSparseMemoryRequirements2KHRgfx75_GetDeviceBufferMemoryRequirementsgfx75_GetDeviceBufferMemoryRequirementsKHRgfx75_GetDeviceImageMemoryRequirementsgfx75_GetDeviceImageMemoryRequirementsKHRgfx75_GetDeviceImageSparseMemoryRequirementsgfx75_GetDeviceImageSparseMemoryRequirementsKHRgfx75_CreateSamplerYcbcrConversiongfx75_CreateSamplerYcbcrConversionKHRgfx75_DestroySamplerYcbcrConversiongfx75_DestroySamplerYcbcrConversionKHRgfx75_GetDeviceQueue2gfx75_CreateValidationCacheEXTgfx75_DestroyValidationCacheEXTgfx75_GetValidationCacheDataEXTgfx75_MergeValidationCachesEXTgfx75_GetDescriptorSetLayoutSupportgfx75_GetDescriptorSetLayoutSupportKHRgfx75_GetShaderInfoAMDgfx75_SetLocalDimmingAMDgfx75_GetCalibratedTimestampsKHRgfx75_GetCalibratedTimestampsEXTgfx75_SetDebugUtilsObjectNameEXTgfx75_SetDebugUtilsObjectTagEXTgfx75_QueueBeginDebugUtilsLabelEXTgfx75_QueueEndDebugUtilsLabelEXTgfx75_QueueInsertDebugUtilsLabelEXTgfx75_CmdBeginDebugUtilsLabelEXTgfx75_CmdEndDebugUtilsLabelEXTgfx75_CmdInsertDebugUtilsLabelEXTgfx75_GetMemoryHostPointerPropertiesEXTgfx75_CmdWriteBufferMarkerAMDgfx75_CreateRenderPass2gfx75_CreateRenderPass2KHRgfx75_CmdBeginRenderPass2gfx75_CmdBeginRenderPass2KHRgfx75_CmdNextSubpass2gfx75_CmdNextSubpass2KHRgfx75_CmdEndRenderPass2gfx75_CmdEndRenderPass2KHRgfx75_GetSemaphoreCounterValuegfx75_GetSemaphoreCounterValueKHRgfx75_WaitSemaphoresgfx75_WaitSemaphoresKHRgfx75_SignalSemaphoregfx75_SignalSemaphoreKHRgfx75_CmdDrawIndirectCountKHRgfx75_CmdDrawIndirectCountAMDgfx75_CmdDrawIndexedIndirectCountKHRgfx75_CmdDrawIndexedIndirectCountAMDgfx75_CmdSetCheckpointNVgfx75_GetQueueCheckpointDataNVgfx75_CmdBindTransformFeedbackBuffersEXTgfx75_CmdSetExclusiveScissorNVgfx75_CmdSetExclusiveScissorEnableNVgfx75_CmdBindShadingRateImageNVgfx75_CmdSetViewportShadingRatePaletteNVgfx75_CmdSetCoarseSampleOrderNVgfx75_CmdDrawMeshTasksNVgfx75_CmdDrawMeshTasksIndirectNVgfx75_CmdDrawMeshTasksIndirectCountNVgfx75_CmdDrawMeshTasksEXTgfx75_CmdDrawMeshTasksIndirectEXTgfx75_CmdDrawMeshTasksIndirectCountEXTgfx75_CompileDeferredNVgfx75_CreateAccelerationStructureNVgfx75_CmdBindInvocationMaskHUAWEIgfx75_DestroyAccelerationStructureKHRgfx75_DestroyAccelerationStructureNVgfx75_GetAccelerationStructureMemoryRequirementsNVgfx75_BindAccelerationStructureMemoryNVgfx75_CmdCopyAccelerationStructureNVgfx75_CmdCopyAccelerationStructureKHRgfx75_CopyAccelerationStructureKHRgfx75_CmdCopyAccelerationStructureToMemoryKHRgfx75_CopyAccelerationStructureToMemoryKHRgfx75_CmdCopyMemoryToAccelerationStructureKHRgfx75_CopyMemoryToAccelerationStructureKHRgfx75_CmdWriteAccelerationStructuresPropertiesKHRgfx75_CmdWriteAccelerationStructuresPropertiesNVgfx75_CmdBuildAccelerationStructureNVgfx75_WriteAccelerationStructuresPropertiesKHRgfx75_CmdTraceRaysKHRgfx75_CmdTraceRaysNVgfx75_GetRayTracingShaderGroupHandlesKHRgfx75_GetRayTracingShaderGroupHandlesNVgfx75_GetRayTracingCaptureReplayShaderGroupHandlesKHRgfx75_GetAccelerationStructureHandleNVgfx75_CreateRayTracingPipelinesNVgfx75_CreateRayTracingPipelinesKHRgfx75_CmdTraceRaysIndirectKHRgfx75_CmdTraceRaysIndirect2KHRgfx75_GetDeviceAccelerationStructureCompatibilityKHRgfx75_GetRayTracingShaderGroupStackSizeKHRgfx75_CmdSetRayTracingPipelineStackSizeKHRgfx75_GetImageViewHandleNVXgfx75_GetImageViewAddressNVXgfx75_AcquireProfilingLockKHRgfx75_ReleaseProfilingLockKHRgfx75_GetImageDrmFormatModifierPropertiesEXTgfx75_GetBufferOpaqueCaptureAddressgfx75_GetBufferOpaqueCaptureAddressKHRgfx75_GetBufferDeviceAddressgfx75_GetBufferDeviceAddressKHRgfx75_GetBufferDeviceAddressEXTgfx75_InitializePerformanceApiINTELgfx75_UninitializePerformanceApiINTELgfx75_CmdSetPerformanceMarkerINTELgfx75_AcquirePerformanceConfigurationINTELgfx75_ReleasePerformanceConfigurationINTELgfx75_QueueSetPerformanceConfigurationINTELgfx75_GetPerformanceParameterINTELgfx75_GetDeviceMemoryOpaqueCaptureAddressgfx75_GetDeviceMemoryOpaqueCaptureAddressKHRgfx75_GetPipelineExecutablePropertiesKHRgfx75_GetPipelineExecutableStatisticsKHRgfx75_GetPipelineExecutableInternalRepresentationsKHRgfx75_CmdSetLineStippleKHRgfx75_CmdSetLineStippleEXTgfx75_CreateAccelerationStructureKHRgfx75_CmdBuildAccelerationStructuresKHRgfx75_CmdBuildAccelerationStructuresIndirectKHRgfx75_BuildAccelerationStructuresKHRgfx75_GetAccelerationStructureDeviceAddressKHRgfx75_CreateDeferredOperationKHRgfx75_DestroyDeferredOperationKHRgfx75_GetDeferredOperationMaxConcurrencyKHRgfx75_GetDeferredOperationResultKHRgfx75_DeferredOperationJoinKHRgfx75_GetPipelineIndirectMemoryRequirementsNVgfx75_GetPipelineIndirectDeviceAddressNVgfx75_CmdSetCullModegfx75_CmdSetCullModeEXTgfx75_CmdSetFrontFacegfx75_CmdSetFrontFaceEXTgfx75_CmdSetPrimitiveTopologygfx75_CmdSetPrimitiveTopologyEXTgfx75_CmdSetViewportWithCountgfx75_CmdSetViewportWithCountEXTgfx75_CmdSetScissorWithCountgfx75_CmdSetScissorWithCountEXTgfx75_CmdBindIndexBuffer2KHRgfx75_CmdBindVertexBuffers2gfx75_CmdBindVertexBuffers2EXTgfx75_CmdSetDepthTestEnablegfx75_CmdSetDepthTestEnableEXTgfx75_CmdSetDepthWriteEnablegfx75_CmdSetDepthWriteEnableEXTgfx75_CmdSetDepthCompareOpgfx75_CmdSetDepthCompareOpEXTgfx75_CmdSetDepthBoundsTestEnablegfx75_CmdSetDepthBoundsTestEnableEXTgfx75_CmdSetStencilTestEnablegfx75_CmdSetStencilTestEnableEXTgfx75_CmdSetStencilOpgfx75_CmdSetStencilOpEXTgfx75_CmdSetPatchControlPointsEXTgfx75_CmdSetRasterizerDiscardEnablegfx75_CmdSetRasterizerDiscardEnableEXTgfx75_CmdSetDepthBiasEnablegfx75_CmdSetDepthBiasEnableEXTgfx75_CmdSetLogicOpEXTgfx75_CmdSetPrimitiveRestartEnablegfx75_CmdSetPrimitiveRestartEnableEXTgfx75_CmdSetTessellationDomainOriginEXTgfx75_CmdSetDepthClampEnableEXTgfx75_CmdSetPolygonModeEXTgfx75_CmdSetRasterizationSamplesEXTgfx75_CmdSetSampleMaskEXTgfx75_CmdSetAlphaToCoverageEnableEXTgfx75_CmdSetAlphaToOneEnableEXTgfx75_CmdSetLogicOpEnableEXTgfx75_CmdSetColorBlendEnableEXTgfx75_CmdSetColorBlendEquationEXTgfx75_CmdSetColorWriteMaskEXTgfx75_CmdSetRasterizationStreamEXTgfx75_CmdSetConservativeRasterizationModeEXTgfx75_CmdSetExtraPrimitiveOverestimationSizeEXTgfx75_CmdSetDepthClipEnableEXTgfx75_CmdSetSampleLocationsEnableEXTgfx75_CmdSetColorBlendAdvancedEXTgfx75_CmdSetProvokingVertexModeEXTgfx75_CmdSetLineRasterizationModeEXTgfx75_CmdSetLineStippleEnableEXTgfx75_CmdSetDepthClipNegativeOneToOneEXTgfx75_CmdSetViewportWScalingEnableNVgfx75_CmdSetViewportSwizzleNVgfx75_CmdSetCoverageToColorEnableNVgfx75_CmdSetCoverageToColorLocationNVgfx75_CmdSetCoverageModulationModeNVgfx75_CmdSetCoverageModulationTableEnableNVgfx75_CmdSetCoverageModulationTableNVgfx75_CmdSetShadingRateImageEnableNVgfx75_CmdSetCoverageReductionModeNVgfx75_CmdSetRepresentativeFragmentTestEnableNVgfx75_CreatePrivateDataSlotgfx75_CreatePrivateDataSlotEXTgfx75_DestroyPrivateDataSlotgfx75_DestroyPrivateDataSlotEXTgfx75_SetPrivateDatagfx75_SetPrivateDataEXTgfx75_GetPrivateDatagfx75_GetPrivateDataEXTgfx75_CmdCopyBuffer2gfx75_CmdCopyBuffer2KHRgfx75_CmdCopyImage2gfx75_CmdCopyImage2KHRgfx75_CmdBlitImage2gfx75_CmdBlitImage2KHRgfx75_CmdCopyBufferToImage2gfx75_CmdCopyBufferToImage2KHRgfx75_CmdCopyImageToBuffer2gfx75_CmdCopyImageToBuffer2KHRgfx75_CmdResolveImage2gfx75_CmdResolveImage2KHRgfx75_CmdSetFragmentShadingRateKHRgfx75_CmdSetFragmentShadingRateEnumNVgfx75_GetAccelerationStructureBuildSizesKHRgfx75_CmdSetVertexInputEXTgfx75_CmdSetColorWriteEnableEXTgfx75_CmdSetEvent2KHRgfx75_CmdResetEvent2KHRgfx75_CmdWaitEvents2KHRgfx75_CmdPipelineBarrier2KHRgfx75_QueueSubmit2gfx75_QueueSubmit2KHRgfx75_CmdWriteTimestamp2KHRgfx75_CmdWriteBufferMarker2AMDgfx75_GetQueueCheckpointData2NVgfx75_CopyMemoryToImageEXTgfx75_CopyImageToMemoryEXTgfx75_CopyImageToImageEXTgfx75_TransitionImageLayoutEXTgfx75_CreateVideoSessionKHRgfx75_DestroyVideoSessionKHRgfx75_CreateVideoSessionParametersKHRgfx75_UpdateVideoSessionParametersKHRgfx75_GetEncodedVideoSessionParametersKHRgfx75_DestroyVideoSessionParametersKHRgfx75_GetVideoSessionMemoryRequirementsKHRgfx75_BindVideoSessionMemoryKHRgfx75_CmdDecodeVideoKHRgfx75_CmdBeginVideoCodingKHRgfx75_CmdControlVideoCodingKHRgfx75_CmdEndVideoCodingKHRgfx75_CmdEncodeVideoKHRgfx75_CmdDecompressMemoryNVgfx75_CmdDecompressMemoryIndirectCountNVgfx75_CreateCuModuleNVXgfx75_CreateCuFunctionNVXgfx75_DestroyCuModuleNVXgfx75_DestroyCuFunctionNVXgfx75_CmdCuLaunchKernelNVXgfx75_GetDescriptorSetLayoutSizeEXTgfx75_GetDescriptorSetLayoutBindingOffsetEXTgfx75_GetDescriptorEXTgfx75_CmdBindDescriptorBuffersEXTgfx75_CmdSetDescriptorBufferOffsetsEXTgfx75_CmdBindDescriptorBufferEmbeddedSamplersEXTgfx75_GetBufferOpaqueCaptureDescriptorDataEXTgfx75_GetImageOpaqueCaptureDescriptorDataEXTgfx75_GetImageViewOpaqueCaptureDescriptorDataEXTgfx75_GetSamplerOpaqueCaptureDescriptorDataEXTgfx75_GetAccelerationStructureOpaqueCaptureDescriptorDataEXTgfx75_SetDeviceMemoryPriorityEXTgfx75_WaitForPresentKHRgfx75_CmdBeginRenderingKHRgfx75_CmdEndRenderingKHRgfx75_GetDescriptorSetLayoutHostMappingInfoVALVEgfx75_GetDescriptorSetHostMappingVALVEgfx75_CreateMicromapEXTgfx75_CmdBuildMicromapsEXTgfx75_BuildMicromapsEXTgfx75_DestroyMicromapEXTgfx75_CmdCopyMicromapEXTgfx75_CopyMicromapEXTgfx75_CmdCopyMicromapToMemoryEXTgfx75_CopyMicromapToMemoryEXTgfx75_CmdCopyMemoryToMicromapEXTgfx75_CopyMemoryToMicromapEXTgfx75_CmdWriteMicromapsPropertiesEXTgfx75_WriteMicromapsPropertiesEXTgfx75_GetDeviceMicromapCompatibilityEXTgfx75_GetMicromapBuildSizesEXTgfx75_GetShaderModuleIdentifierEXTgfx75_GetShaderModuleCreateInfoIdentifierEXTgfx75_GetImageSubresourceLayout2KHRgfx75_GetImageSubresourceLayout2EXTgfx75_GetPipelinePropertiesEXTgfx75_GetFramebufferTilePropertiesQCOMgfx75_GetDynamicRenderingTilePropertiesQCOMgfx75_CreateOpticalFlowSessionNVgfx75_DestroyOpticalFlowSessionNVgfx75_BindOpticalFlowSessionImageNVgfx75_CmdOpticalFlowExecuteNVgfx75_GetDeviceFaultInfoEXTgfx75_CmdSetDepthBias2EXTgfx75_ReleaseSwapchainImagesEXTgfx75_GetDeviceImageSubresourceLayoutKHRgfx75_MapMemory2KHRgfx75_UnmapMemory2KHRgfx75_CreateShadersEXTgfx75_DestroyShaderEXTgfx75_GetShaderBinaryDataEXTgfx75_CmdBindShadersEXTgfx75_CmdBindDescriptorSets2KHRgfx75_CmdPushConstants2KHRgfx75_CmdPushDescriptorSet2KHRgfx75_CmdPushDescriptorSetWithTemplate2KHRgfx75_CmdSetDescriptorBufferOffsets2EXTgfx75_CmdBindDescriptorBufferEmbeddedSamplers2EXTgfx75_SetLatencySleepModeNVgfx75_LatencySleepNVgfx75_SetLatencyMarkerNVgfx75_GetLatencyTimingsNVgfx75_QueueNotifyOutOfBandNVgfx75_CmdSetRenderingAttachmentLocationsKHRgfx75_CmdSetRenderingInputAttachmentIndicesKHRgfx7_GetDeviceProcAddrgfx7_DestroyDevicegfx7_GetDeviceQueuegfx7_QueueSubmitgfx7_QueueWaitIdlegfx7_DeviceWaitIdlegfx7_AllocateMemorygfx7_FreeMemorygfx7_MapMemorygfx7_UnmapMemorygfx7_FlushMappedMemoryRangesgfx7_InvalidateMappedMemoryRangesgfx7_GetDeviceMemoryCommitmentgfx7_GetBufferMemoryRequirementsgfx7_BindBufferMemorygfx7_GetImageMemoryRequirementsgfx7_BindImageMemorygfx7_GetImageSparseMemoryRequirementsgfx7_QueueBindSparsegfx7_CreateFencegfx7_DestroyFencegfx7_ResetFencesgfx7_GetFenceStatusgfx7_WaitForFencesgfx7_CreateSemaphoregfx7_DestroySemaphoregfx7_CreateEventgfx7_DestroyEventgfx7_GetEventStatusgfx7_SetEventgfx7_ResetEventgfx7_ResetQueryPoolEXTgfx7_CreateBuffergfx7_DestroyBuffergfx7_CreateBufferViewgfx7_DestroyBufferViewgfx7_CreateImagegfx7_DestroyImagegfx7_GetImageSubresourceLayoutgfx7_CreateImageViewgfx7_DestroyImageViewgfx7_CreateShaderModulegfx7_DestroyShaderModulegfx7_CreatePipelineCachegfx7_DestroyPipelineCachegfx7_GetPipelineCacheDatagfx7_MergePipelineCachesgfx7_CreateGraphicsPipelinesgfx7_CreateComputePipelinesgfx7_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIgfx7_DestroyPipelinegfx7_CreatePipelineLayoutgfx7_DestroyPipelineLayoutgfx7_DestroySamplergfx7_CreateDescriptorSetLayoutgfx7_DestroyDescriptorSetLayoutgfx7_CreateDescriptorPoolgfx7_DestroyDescriptorPoolgfx7_ResetDescriptorPoolgfx7_AllocateDescriptorSetsgfx7_FreeDescriptorSetsgfx7_UpdateDescriptorSetsgfx7_CreateFramebuffergfx7_DestroyFramebuffergfx7_CreateRenderPassgfx7_DestroyRenderPassgfx7_GetRenderAreaGranularitygfx7_GetRenderingAreaGranularityKHRgfx7_CreateCommandPoolgfx7_DestroyCommandPoolgfx7_ResetCommandPoolgfx7_AllocateCommandBuffersgfx7_FreeCommandBuffersgfx7_ResetCommandBuffergfx7_CmdBindPipelinegfx7_CmdSetAttachmentFeedbackLoopEnableEXTgfx7_CmdSetViewportgfx7_CmdSetScissorgfx7_CmdSetLineWidthgfx7_CmdSetDepthBiasgfx7_CmdSetBlendConstantsgfx7_CmdSetDepthBoundsgfx7_CmdSetStencilCompareMaskgfx7_CmdSetStencilWriteMaskgfx7_CmdSetStencilReferencegfx7_CmdBindDescriptorSetsgfx7_CmdBindVertexBuffersgfx7_CmdDispatchgfx7_CmdSubpassShadingHUAWEIgfx7_CmdDrawClusterHUAWEIgfx7_CmdDrawClusterIndirectHUAWEIgfx7_CmdUpdatePipelineIndirectBufferNVgfx7_CmdCopyBuffergfx7_CmdCopyImagegfx7_CmdBlitImagegfx7_CmdCopyBufferToImagegfx7_CmdCopyImageToBuffergfx7_CmdCopyMemoryIndirectNVgfx7_CmdCopyMemoryToImageIndirectNVgfx7_CmdUpdateBuffergfx7_CmdFillBuffergfx7_CmdClearColorImagegfx7_CmdClearDepthStencilImagegfx7_CmdClearAttachmentsgfx7_CmdResolveImagegfx7_CmdSetEventgfx7_CmdResetEventgfx7_CmdWaitEventsgfx7_CmdPipelineBarriergfx7_CmdBeginConditionalRenderingEXTgfx7_CmdEndConditionalRenderingEXTgfx7_CmdWriteTimestampgfx7_CmdPushConstantsgfx7_CmdBeginRenderPassgfx7_CmdNextSubpassgfx7_CmdEndRenderPassgfx7_CreateSharedSwapchainsKHRgfx7_CreateSwapchainKHRgfx7_DestroySwapchainKHRgfx7_GetSwapchainImagesKHRgfx7_AcquireNextImageKHRgfx7_QueuePresentKHRgfx7_DebugMarkerSetObjectNameEXTgfx7_DebugMarkerSetObjectTagEXTgfx7_CmdDebugMarkerBeginEXTgfx7_CmdDebugMarkerEndEXTgfx7_CmdDebugMarkerInsertEXTgfx7_CmdExecuteGeneratedCommandsNVgfx7_CmdPreprocessGeneratedCommandsNVgfx7_CmdBindPipelineShaderGroupNVgfx7_GetGeneratedCommandsMemoryRequirementsNVgfx7_CreateIndirectCommandsLayoutNVgfx7_DestroyIndirectCommandsLayoutNVgfx7_CmdPushDescriptorSetKHRgfx7_TrimCommandPoolgfx7_TrimCommandPoolKHRgfx7_GetMemoryFdKHRgfx7_GetMemoryFdPropertiesKHRgfx7_GetMemoryRemoteAddressNVgfx7_GetSemaphoreFdKHRgfx7_ImportSemaphoreFdKHRgfx7_GetFenceFdKHRgfx7_ImportFenceFdKHRgfx7_DisplayPowerControlEXTgfx7_RegisterDeviceEventEXTgfx7_RegisterDisplayEventEXTgfx7_GetSwapchainCounterEXTgfx7_GetDeviceGroupPeerMemoryFeaturesgfx7_GetDeviceGroupPeerMemoryFeaturesKHRgfx7_BindBufferMemory2gfx7_BindBufferMemory2KHRgfx7_BindImageMemory2gfx7_BindImageMemory2KHRgfx7_CmdSetDeviceMaskgfx7_CmdSetDeviceMaskKHRgfx7_GetDeviceGroupPresentCapabilitiesKHRgfx7_GetDeviceGroupSurfacePresentModesKHRgfx7_AcquireNextImage2KHRgfx7_CmdDispatchBaseKHRgfx7_CreateDescriptorUpdateTemplategfx7_CreateDescriptorUpdateTemplateKHRgfx7_DestroyDescriptorUpdateTemplategfx7_DestroyDescriptorUpdateTemplateKHRgfx7_UpdateDescriptorSetWithTemplategfx7_UpdateDescriptorSetWithTemplateKHRgfx7_CmdPushDescriptorSetWithTemplateKHRgfx7_SetHdrMetadataEXTgfx7_GetSwapchainStatusKHRgfx7_GetRefreshCycleDurationGOOGLEgfx7_GetPastPresentationTimingGOOGLEgfx7_CmdSetViewportWScalingNVgfx7_CmdSetDiscardRectangleEXTgfx7_CmdSetDiscardRectangleEnableEXTgfx7_CmdSetDiscardRectangleModeEXTgfx7_CmdSetSampleLocationsEXTgfx7_GetBufferMemoryRequirements2gfx7_GetBufferMemoryRequirements2KHRgfx7_GetImageMemoryRequirements2gfx7_GetImageMemoryRequirements2KHRgfx7_GetImageSparseMemoryRequirements2gfx7_GetImageSparseMemoryRequirements2KHRgfx7_GetDeviceBufferMemoryRequirementsgfx7_GetDeviceBufferMemoryRequirementsKHRgfx7_GetDeviceImageMemoryRequirementsgfx7_GetDeviceImageMemoryRequirementsKHRgfx7_GetDeviceImageSparseMemoryRequirementsgfx7_GetDeviceImageSparseMemoryRequirementsKHRgfx7_CreateSamplerYcbcrConversiongfx7_CreateSamplerYcbcrConversionKHRgfx7_DestroySamplerYcbcrConversiongfx7_DestroySamplerYcbcrConversionKHRgfx7_GetDeviceQueue2gfx7_CreateValidationCacheEXTgfx7_DestroyValidationCacheEXTgfx7_GetValidationCacheDataEXTgfx7_MergeValidationCachesEXTgfx7_GetDescriptorSetLayoutSupportgfx7_GetDescriptorSetLayoutSupportKHRgfx7_GetShaderInfoAMDgfx7_SetLocalDimmingAMDgfx7_GetCalibratedTimestampsKHRgfx7_GetCalibratedTimestampsEXTgfx7_SetDebugUtilsObjectNameEXTgfx7_SetDebugUtilsObjectTagEXTgfx7_QueueBeginDebugUtilsLabelEXTgfx7_QueueEndDebugUtilsLabelEXTgfx7_QueueInsertDebugUtilsLabelEXTgfx7_CmdBeginDebugUtilsLabelEXTgfx7_CmdEndDebugUtilsLabelEXTgfx7_CmdInsertDebugUtilsLabelEXTgfx7_GetMemoryHostPointerPropertiesEXTgfx7_CmdWriteBufferMarkerAMDgfx7_CreateRenderPass2gfx7_CreateRenderPass2KHRgfx7_CmdBeginRenderPass2gfx7_CmdBeginRenderPass2KHRgfx7_CmdNextSubpass2gfx7_CmdNextSubpass2KHRgfx7_CmdEndRenderPass2gfx7_CmdEndRenderPass2KHRgfx7_GetSemaphoreCounterValuegfx7_GetSemaphoreCounterValueKHRgfx7_WaitSemaphoresgfx7_WaitSemaphoresKHRgfx7_SignalSemaphoregfx7_SignalSemaphoreKHRgfx7_CmdDrawIndirectCountKHRgfx7_CmdDrawIndirectCountAMDgfx7_CmdDrawIndexedIndirectCountKHRgfx7_CmdDrawIndexedIndirectCountAMDgfx7_CmdSetCheckpointNVgfx7_GetQueueCheckpointDataNVgfx7_CmdBindTransformFeedbackBuffersEXTgfx7_CmdSetExclusiveScissorNVgfx7_CmdSetExclusiveScissorEnableNVgfx7_CmdBindShadingRateImageNVgfx7_CmdSetViewportShadingRatePaletteNVgfx7_CmdSetCoarseSampleOrderNVgfx7_CmdDrawMeshTasksNVgfx7_CmdDrawMeshTasksIndirectNVgfx7_CmdDrawMeshTasksIndirectCountNVgfx7_CmdDrawMeshTasksEXTgfx7_CmdDrawMeshTasksIndirectEXTgfx7_CmdDrawMeshTasksIndirectCountEXTgfx7_CompileDeferredNVgfx7_CreateAccelerationStructureNVgfx7_CmdBindInvocationMaskHUAWEIgfx7_DestroyAccelerationStructureKHRgfx7_DestroyAccelerationStructureNVgfx7_GetAccelerationStructureMemoryRequirementsNVgfx7_BindAccelerationStructureMemoryNVgfx7_CmdCopyAccelerationStructureNVgfx7_CmdCopyAccelerationStructureKHRgfx7_CopyAccelerationStructureKHRgfx7_CmdCopyAccelerationStructureToMemoryKHRgfx7_CopyAccelerationStructureToMemoryKHRgfx7_CmdCopyMemoryToAccelerationStructureKHRgfx7_CopyMemoryToAccelerationStructureKHRgfx7_CmdWriteAccelerationStructuresPropertiesKHRgfx7_CmdWriteAccelerationStructuresPropertiesNVgfx7_CmdBuildAccelerationStructureNVgfx7_WriteAccelerationStructuresPropertiesKHRgfx7_CmdTraceRaysKHRgfx7_CmdTraceRaysNVgfx7_GetRayTracingShaderGroupHandlesKHRgfx7_GetRayTracingShaderGroupHandlesNVgfx7_GetRayTracingCaptureReplayShaderGroupHandlesKHRgfx7_GetAccelerationStructureHandleNVgfx7_CreateRayTracingPipelinesNVgfx7_CreateRayTracingPipelinesKHRgfx7_CmdTraceRaysIndirectKHRgfx7_CmdTraceRaysIndirect2KHRgfx7_GetDeviceAccelerationStructureCompatibilityKHRgfx7_GetRayTracingShaderGroupStackSizeKHRgfx7_CmdSetRayTracingPipelineStackSizeKHRgfx7_GetImageViewHandleNVXgfx7_GetImageViewAddressNVXgfx7_AcquireProfilingLockKHRgfx7_ReleaseProfilingLockKHRgfx7_GetImageDrmFormatModifierPropertiesEXTgfx7_GetBufferOpaqueCaptureAddressgfx7_GetBufferOpaqueCaptureAddressKHRgfx7_GetBufferDeviceAddressgfx7_GetBufferDeviceAddressKHRgfx7_GetBufferDeviceAddressEXTgfx7_InitializePerformanceApiINTELgfx7_UninitializePerformanceApiINTELgfx7_CmdSetPerformanceMarkerINTELgfx7_AcquirePerformanceConfigurationINTELgfx7_ReleasePerformanceConfigurationINTELgfx7_QueueSetPerformanceConfigurationINTELgfx7_GetPerformanceParameterINTELgfx7_GetDeviceMemoryOpaqueCaptureAddressgfx7_GetDeviceMemoryOpaqueCaptureAddressKHRgfx7_GetPipelineExecutablePropertiesKHRgfx7_GetPipelineExecutableStatisticsKHRgfx7_GetPipelineExecutableInternalRepresentationsKHRgfx7_CmdSetLineStippleKHRgfx7_CmdSetLineStippleEXTgfx7_CreateAccelerationStructureKHRgfx7_CmdBuildAccelerationStructuresKHRgfx7_CmdBuildAccelerationStructuresIndirectKHRgfx7_BuildAccelerationStructuresKHRgfx7_GetAccelerationStructureDeviceAddressKHRgfx7_CreateDeferredOperationKHRgfx7_DestroyDeferredOperationKHRgfx7_GetDeferredOperationMaxConcurrencyKHRgfx7_GetDeferredOperationResultKHRgfx7_DeferredOperationJoinKHRgfx7_GetPipelineIndirectMemoryRequirementsNVgfx7_GetPipelineIndirectDeviceAddressNVgfx7_CmdSetCullModegfx7_CmdSetCullModeEXTgfx7_CmdSetFrontFacegfx7_CmdSetFrontFaceEXTgfx7_CmdSetPrimitiveTopologygfx7_CmdSetPrimitiveTopologyEXTgfx7_CmdSetViewportWithCountgfx7_CmdSetViewportWithCountEXTgfx7_CmdSetScissorWithCountgfx7_CmdSetScissorWithCountEXTgfx7_CmdBindIndexBuffer2KHRgfx7_CmdBindVertexBuffers2gfx7_CmdBindVertexBuffers2EXTgfx7_CmdSetDepthTestEnablegfx7_CmdSetDepthTestEnableEXTgfx7_CmdSetDepthWriteEnablegfx7_CmdSetDepthWriteEnableEXTgfx7_CmdSetDepthCompareOpgfx7_CmdSetDepthCompareOpEXTgfx7_CmdSetDepthBoundsTestEnablegfx7_CmdSetDepthBoundsTestEnableEXTgfx7_CmdSetStencilTestEnablegfx7_CmdSetStencilTestEnableEXTgfx7_CmdSetStencilOpgfx7_CmdSetStencilOpEXTgfx7_CmdSetPatchControlPointsEXTgfx7_CmdSetRasterizerDiscardEnablegfx7_CmdSetRasterizerDiscardEnableEXTgfx7_CmdSetDepthBiasEnablegfx7_CmdSetDepthBiasEnableEXTgfx7_CmdSetLogicOpEXTgfx7_CmdSetPrimitiveRestartEnablegfx7_CmdSetPrimitiveRestartEnableEXTgfx7_CmdSetTessellationDomainOriginEXTgfx7_CmdSetDepthClampEnableEXTgfx7_CmdSetPolygonModeEXTgfx7_CmdSetRasterizationSamplesEXTgfx7_CmdSetSampleMaskEXTgfx7_CmdSetAlphaToCoverageEnableEXTgfx7_CmdSetAlphaToOneEnableEXTgfx7_CmdSetLogicOpEnableEXTgfx7_CmdSetColorBlendEnableEXTgfx7_CmdSetColorBlendEquationEXTgfx7_CmdSetColorWriteMaskEXTgfx7_CmdSetRasterizationStreamEXTgfx7_CmdSetConservativeRasterizationModeEXTgfx7_CmdSetExtraPrimitiveOverestimationSizeEXTgfx7_CmdSetDepthClipEnableEXTgfx7_CmdSetSampleLocationsEnableEXTgfx7_CmdSetColorBlendAdvancedEXTgfx7_CmdSetProvokingVertexModeEXTgfx7_CmdSetLineRasterizationModeEXTgfx7_CmdSetLineStippleEnableEXTgfx7_CmdSetDepthClipNegativeOneToOneEXTgfx7_CmdSetViewportWScalingEnableNVgfx7_CmdSetViewportSwizzleNVgfx7_CmdSetCoverageToColorEnableNVgfx7_CmdSetCoverageToColorLocationNVgfx7_CmdSetCoverageModulationModeNVgfx7_CmdSetCoverageModulationTableEnableNVgfx7_CmdSetCoverageModulationTableNVgfx7_CmdSetShadingRateImageEnableNVgfx7_CmdSetCoverageReductionModeNVgfx7_CmdSetRepresentativeFragmentTestEnableNVgfx7_CreatePrivateDataSlotgfx7_CreatePrivateDataSlotEXTgfx7_DestroyPrivateDataSlotgfx7_DestroyPrivateDataSlotEXTgfx7_SetPrivateDatagfx7_SetPrivateDataEXTgfx7_GetPrivateDatagfx7_GetPrivateDataEXTgfx7_CmdCopyBuffer2gfx7_CmdCopyBuffer2KHRgfx7_CmdCopyImage2gfx7_CmdCopyImage2KHRgfx7_CmdBlitImage2gfx7_CmdBlitImage2KHRgfx7_CmdCopyBufferToImage2gfx7_CmdCopyBufferToImage2KHRgfx7_CmdCopyImageToBuffer2gfx7_CmdCopyImageToBuffer2KHRgfx7_CmdResolveImage2gfx7_CmdResolveImage2KHRgfx7_CmdSetFragmentShadingRateKHRgfx7_CmdSetFragmentShadingRateEnumNVgfx7_GetAccelerationStructureBuildSizesKHRgfx7_CmdSetVertexInputEXTgfx7_CmdSetColorWriteEnableEXTgfx7_CmdSetEvent2KHRgfx7_CmdResetEvent2KHRgfx7_CmdWaitEvents2KHRgfx7_CmdPipelineBarrier2KHRgfx7_QueueSubmit2gfx7_QueueSubmit2KHRgfx7_CmdWriteTimestamp2KHRgfx7_CmdWriteBufferMarker2AMDgfx7_GetQueueCheckpointData2NVgfx7_CopyMemoryToImageEXTgfx7_CopyImageToMemoryEXTgfx7_CopyImageToImageEXTgfx7_TransitionImageLayoutEXTgfx7_CreateVideoSessionKHRgfx7_DestroyVideoSessionKHRgfx7_CreateVideoSessionParametersKHRgfx7_UpdateVideoSessionParametersKHRgfx7_GetEncodedVideoSessionParametersKHRgfx7_DestroyVideoSessionParametersKHRgfx7_GetVideoSessionMemoryRequirementsKHRgfx7_BindVideoSessionMemoryKHRgfx7_CmdDecodeVideoKHRgfx7_CmdBeginVideoCodingKHRgfx7_CmdControlVideoCodingKHRgfx7_CmdEndVideoCodingKHRgfx7_CmdEncodeVideoKHRgfx7_CmdDecompressMemoryNVgfx7_CmdDecompressMemoryIndirectCountNVgfx7_CreateCuModuleNVXgfx7_CreateCuFunctionNVXgfx7_DestroyCuModuleNVXgfx7_DestroyCuFunctionNVXgfx7_CmdCuLaunchKernelNVXgfx7_GetDescriptorSetLayoutSizeEXTgfx7_GetDescriptorSetLayoutBindingOffsetEXTgfx7_GetDescriptorEXTgfx7_CmdBindDescriptorBuffersEXTgfx7_CmdSetDescriptorBufferOffsetsEXTgfx7_CmdBindDescriptorBufferEmbeddedSamplersEXTgfx7_GetBufferOpaqueCaptureDescriptorDataEXTgfx7_GetImageOpaqueCaptureDescriptorDataEXTgfx7_GetImageViewOpaqueCaptureDescriptorDataEXTgfx7_GetSamplerOpaqueCaptureDescriptorDataEXTgfx7_GetAccelerationStructureOpaqueCaptureDescriptorDataEXTgfx7_SetDeviceMemoryPriorityEXTgfx7_WaitForPresentKHRgfx7_CmdBeginRenderingKHRgfx7_CmdEndRenderingKHRgfx7_GetDescriptorSetLayoutHostMappingInfoVALVEgfx7_GetDescriptorSetHostMappingVALVEgfx7_CreateMicromapEXTgfx7_CmdBuildMicromapsEXTgfx7_BuildMicromapsEXTgfx7_DestroyMicromapEXTgfx7_CmdCopyMicromapEXTgfx7_CopyMicromapEXTgfx7_CmdCopyMicromapToMemoryEXTgfx7_CopyMicromapToMemoryEXTgfx7_CmdCopyMemoryToMicromapEXTgfx7_CopyMemoryToMicromapEXTgfx7_CmdWriteMicromapsPropertiesEXTgfx7_WriteMicromapsPropertiesEXTgfx7_GetDeviceMicromapCompatibilityEXTgfx7_GetMicromapBuildSizesEXTgfx7_GetShaderModuleIdentifierEXTgfx7_GetShaderModuleCreateInfoIdentifierEXTgfx7_GetImageSubresourceLayout2KHRgfx7_GetImageSubresourceLayout2EXTgfx7_GetPipelinePropertiesEXTgfx7_GetFramebufferTilePropertiesQCOMgfx7_GetDynamicRenderingTilePropertiesQCOMgfx7_CreateOpticalFlowSessionNVgfx7_DestroyOpticalFlowSessionNVgfx7_BindOpticalFlowSessionImageNVgfx7_CmdOpticalFlowExecuteNVgfx7_GetDeviceFaultInfoEXTgfx7_CmdSetDepthBias2EXTgfx7_ReleaseSwapchainImagesEXTgfx7_GetDeviceImageSubresourceLayoutKHRgfx7_MapMemory2KHRgfx7_UnmapMemory2KHRgfx7_CreateShadersEXTgfx7_DestroyShaderEXTgfx7_GetShaderBinaryDataEXTgfx7_CmdBindShadersEXTgfx7_CmdBindDescriptorSets2KHRgfx7_CmdPushConstants2KHRgfx7_CmdPushDescriptorSet2KHRgfx7_CmdPushDescriptorSetWithTemplate2KHRgfx7_CmdSetDescriptorBufferOffsets2EXTgfx7_CmdBindDescriptorBufferEmbeddedSamplers2EXTgfx7_SetLatencySleepModeNVgfx7_LatencySleepNVgfx7_SetLatencyMarkerNVgfx7_GetLatencyTimingsNVgfx7_QueueNotifyOutOfBandNVgfx7_CmdSetRenderingAttachmentLocationsKHRgfx7_CmdSetRenderingInputAttachmentIndicesKHRwsi_GetDeviceProcAddrwsi_DestroyDevicewsi_GetDeviceQueuewsi_QueueSubmitwsi_QueueWaitIdlewsi_DeviceWaitIdlewsi_AllocateMemorywsi_FreeMemorywsi_MapMemorywsi_UnmapMemorywsi_FlushMappedMemoryRangeswsi_InvalidateMappedMemoryRangeswsi_GetDeviceMemoryCommitmentwsi_GetBufferMemoryRequirementswsi_BindBufferMemorywsi_GetImageMemoryRequirementswsi_BindImageMemorywsi_GetImageSparseMemoryRequirementswsi_QueueBindSparsewsi_CreateFencewsi_DestroyFencewsi_ResetFenceswsi_GetFenceStatuswsi_WaitForFenceswsi_CreateSemaphorewsi_DestroySemaphorewsi_CreateEventwsi_DestroyEventwsi_GetEventStatuswsi_SetEventwsi_ResetEventwsi_CreateQueryPoolwsi_DestroyQueryPoolwsi_GetQueryPoolResultswsi_ResetQueryPoolwsi_ResetQueryPoolEXTwsi_CreateBufferwsi_DestroyBufferwsi_CreateBufferViewwsi_DestroyBufferViewwsi_CreateImagewsi_DestroyImagewsi_GetImageSubresourceLayoutwsi_CreateImageViewwsi_DestroyImageViewwsi_CreateShaderModulewsi_DestroyShaderModulewsi_CreatePipelineCachewsi_DestroyPipelineCachewsi_GetPipelineCacheDatawsi_MergePipelineCacheswsi_CreateGraphicsPipelineswsi_CreateComputePipelineswsi_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIwsi_DestroyPipelinewsi_CreatePipelineLayoutwsi_DestroyPipelineLayoutwsi_CreateSamplerwsi_DestroySamplerwsi_CreateDescriptorSetLayoutwsi_DestroyDescriptorSetLayoutwsi_CreateDescriptorPoolwsi_DestroyDescriptorPoolwsi_ResetDescriptorPoolwsi_AllocateDescriptorSetswsi_FreeDescriptorSetswsi_UpdateDescriptorSetswsi_CreateFramebufferwsi_DestroyFramebufferwsi_CreateRenderPasswsi_DestroyRenderPasswsi_GetRenderAreaGranularitywsi_GetRenderingAreaGranularityKHRwsi_CreateCommandPoolwsi_DestroyCommandPoolwsi_ResetCommandPoolwsi_AllocateCommandBufferswsi_FreeCommandBufferswsi_BeginCommandBufferwsi_EndCommandBufferwsi_ResetCommandBufferwsi_CmdBindPipelinewsi_CmdSetAttachmentFeedbackLoopEnableEXTwsi_CmdSetViewportwsi_CmdSetScissorwsi_CmdSetLineWidthwsi_CmdSetDepthBiaswsi_CmdSetBlendConstantswsi_CmdSetDepthBoundswsi_CmdSetStencilCompareMaskwsi_CmdSetStencilWriteMaskwsi_CmdSetStencilReferencewsi_CmdBindDescriptorSetswsi_CmdBindIndexBufferwsi_CmdBindVertexBufferswsi_CmdDrawwsi_CmdDrawIndexedwsi_CmdDrawMultiEXTwsi_CmdDrawMultiIndexedEXTwsi_CmdDrawIndirectwsi_CmdDrawIndexedIndirectwsi_CmdDispatchwsi_CmdDispatchIndirectwsi_CmdSubpassShadingHUAWEIwsi_CmdDrawClusterHUAWEIwsi_CmdDrawClusterIndirectHUAWEIwsi_CmdUpdatePipelineIndirectBufferNVwsi_CmdCopyBufferwsi_CmdCopyImagewsi_CmdBlitImagewsi_CmdCopyBufferToImagewsi_CmdCopyImageToBufferwsi_CmdCopyMemoryIndirectNVwsi_CmdCopyMemoryToImageIndirectNVwsi_CmdUpdateBufferwsi_CmdFillBufferwsi_CmdClearColorImagewsi_CmdClearDepthStencilImagewsi_CmdClearAttachmentswsi_CmdResolveImagewsi_CmdSetEventwsi_CmdResetEventwsi_CmdWaitEventswsi_CmdPipelineBarrierwsi_CmdBeginQuerywsi_CmdEndQuerywsi_CmdBeginConditionalRenderingEXTwsi_CmdEndConditionalRenderingEXTwsi_CmdResetQueryPoolwsi_CmdWriteTimestampwsi_CmdCopyQueryPoolResultswsi_CmdPushConstantswsi_CmdBeginRenderPasswsi_CmdNextSubpasswsi_CmdEndRenderPasswsi_CmdExecuteCommandswsi_CreateSharedSwapchainsKHRwsi_DebugMarkerSetObjectNameEXTwsi_DebugMarkerSetObjectTagEXTwsi_CmdDebugMarkerBeginEXTwsi_CmdDebugMarkerEndEXTwsi_CmdDebugMarkerInsertEXTwsi_CmdExecuteGeneratedCommandsNVwsi_CmdPreprocessGeneratedCommandsNVwsi_CmdBindPipelineShaderGroupNVwsi_GetGeneratedCommandsMemoryRequirementsNVwsi_CreateIndirectCommandsLayoutNVwsi_DestroyIndirectCommandsLayoutNVwsi_CmdPushDescriptorSetKHRwsi_TrimCommandPoolwsi_TrimCommandPoolKHRwsi_GetMemoryFdKHRwsi_GetMemoryFdPropertiesKHRwsi_GetMemoryRemoteAddressNVwsi_GetSemaphoreFdKHRwsi_ImportSemaphoreFdKHRwsi_GetFenceFdKHRwsi_ImportFenceFdKHRwsi_GetDeviceGroupPeerMemoryFeatureswsi_GetDeviceGroupPeerMemoryFeaturesKHRwsi_BindBufferMemory2wsi_BindBufferMemory2KHRwsi_BindImageMemory2wsi_BindImageMemory2KHRwsi_CmdSetDeviceMaskwsi_CmdSetDeviceMaskKHRwsi_CmdDispatchBasewsi_CmdDispatchBaseKHRwsi_CreateDescriptorUpdateTemplatewsi_CreateDescriptorUpdateTemplateKHRwsi_DestroyDescriptorUpdateTemplatewsi_DestroyDescriptorUpdateTemplateKHRwsi_UpdateDescriptorSetWithTemplatewsi_UpdateDescriptorSetWithTemplateKHRwsi_CmdPushDescriptorSetWithTemplateKHRwsi_SetHdrMetadataEXTwsi_GetSwapchainStatusKHRwsi_GetRefreshCycleDurationGOOGLEwsi_GetPastPresentationTimingGOOGLEwsi_CmdSetViewportWScalingNVwsi_CmdSetDiscardRectangleEXTwsi_CmdSetDiscardRectangleEnableEXTwsi_CmdSetDiscardRectangleModeEXTwsi_CmdSetSampleLocationsEXTwsi_GetBufferMemoryRequirements2wsi_GetBufferMemoryRequirements2KHRwsi_GetImageMemoryRequirements2wsi_GetImageMemoryRequirements2KHRwsi_GetImageSparseMemoryRequirements2wsi_GetImageSparseMemoryRequirements2KHRwsi_GetDeviceBufferMemoryRequirementswsi_GetDeviceBufferMemoryRequirementsKHRwsi_GetDeviceImageMemoryRequirementswsi_GetDeviceImageMemoryRequirementsKHRwsi_GetDeviceImageSparseMemoryRequirementswsi_GetDeviceImageSparseMemoryRequirementsKHRwsi_CreateSamplerYcbcrConversionwsi_CreateSamplerYcbcrConversionKHRwsi_DestroySamplerYcbcrConversionwsi_DestroySamplerYcbcrConversionKHRwsi_GetDeviceQueue2wsi_CreateValidationCacheEXTwsi_DestroyValidationCacheEXTwsi_GetValidationCacheDataEXTwsi_MergeValidationCachesEXTwsi_GetDescriptorSetLayoutSupportwsi_GetDescriptorSetLayoutSupportKHRwsi_GetShaderInfoAMDwsi_SetLocalDimmingAMDwsi_GetCalibratedTimestampsKHRwsi_GetCalibratedTimestampsEXTwsi_SetDebugUtilsObjectNameEXTwsi_SetDebugUtilsObjectTagEXTwsi_QueueBeginDebugUtilsLabelEXTwsi_QueueEndDebugUtilsLabelEXTwsi_QueueInsertDebugUtilsLabelEXTwsi_CmdBeginDebugUtilsLabelEXTwsi_CmdEndDebugUtilsLabelEXTwsi_CmdInsertDebugUtilsLabelEXTwsi_GetMemoryHostPointerPropertiesEXTwsi_CmdWriteBufferMarkerAMDwsi_CreateRenderPass2wsi_CreateRenderPass2KHRwsi_CmdBeginRenderPass2wsi_CmdBeginRenderPass2KHRwsi_CmdNextSubpass2wsi_CmdNextSubpass2KHRwsi_CmdEndRenderPass2wsi_CmdEndRenderPass2KHRwsi_GetSemaphoreCounterValuewsi_GetSemaphoreCounterValueKHRwsi_WaitSemaphoreswsi_WaitSemaphoresKHRwsi_SignalSemaphorewsi_SignalSemaphoreKHRwsi_CmdDrawIndirectCountwsi_CmdDrawIndirectCountKHRwsi_CmdDrawIndirectCountAMDwsi_CmdDrawIndexedIndirectCountwsi_CmdDrawIndexedIndirectCountKHRwsi_CmdDrawIndexedIndirectCountAMDwsi_CmdSetCheckpointNVwsi_GetQueueCheckpointDataNVwsi_CmdBindTransformFeedbackBuffersEXTwsi_CmdBeginTransformFeedbackEXTwsi_CmdEndTransformFeedbackEXTwsi_CmdBeginQueryIndexedEXTwsi_CmdEndQueryIndexedEXTwsi_CmdDrawIndirectByteCountEXTwsi_CmdSetExclusiveScissorNVwsi_CmdSetExclusiveScissorEnableNVwsi_CmdBindShadingRateImageNVwsi_CmdSetViewportShadingRatePaletteNVwsi_CmdSetCoarseSampleOrderNVwsi_CmdDrawMeshTasksNVwsi_CmdDrawMeshTasksIndirectNVwsi_CmdDrawMeshTasksIndirectCountNVwsi_CmdDrawMeshTasksEXTwsi_CmdDrawMeshTasksIndirectEXTwsi_CmdDrawMeshTasksIndirectCountEXTwsi_CompileDeferredNVwsi_CreateAccelerationStructureNVwsi_CmdBindInvocationMaskHUAWEIwsi_DestroyAccelerationStructureKHRwsi_DestroyAccelerationStructureNVwsi_GetAccelerationStructureMemoryRequirementsNVwsi_BindAccelerationStructureMemoryNVwsi_CmdCopyAccelerationStructureNVwsi_CmdCopyAccelerationStructureKHRwsi_CopyAccelerationStructureKHRwsi_CmdCopyAccelerationStructureToMemoryKHRwsi_CopyAccelerationStructureToMemoryKHRwsi_CmdCopyMemoryToAccelerationStructureKHRwsi_CopyMemoryToAccelerationStructureKHRwsi_CmdWriteAccelerationStructuresPropertiesKHRwsi_CmdWriteAccelerationStructuresPropertiesNVwsi_CmdBuildAccelerationStructureNVwsi_WriteAccelerationStructuresPropertiesKHRwsi_CmdTraceRaysKHRwsi_CmdTraceRaysNVwsi_GetRayTracingShaderGroupHandlesKHRwsi_GetRayTracingShaderGroupHandlesNVwsi_GetRayTracingCaptureReplayShaderGroupHandlesKHRwsi_GetAccelerationStructureHandleNVwsi_CreateRayTracingPipelinesNVwsi_CreateRayTracingPipelinesKHRwsi_CmdTraceRaysIndirectKHRwsi_CmdTraceRaysIndirect2KHRwsi_GetDeviceAccelerationStructureCompatibilityKHRwsi_GetRayTracingShaderGroupStackSizeKHRwsi_CmdSetRayTracingPipelineStackSizeKHRwsi_GetImageViewHandleNVXwsi_GetImageViewAddressNVXwsi_AcquireProfilingLockKHRwsi_ReleaseProfilingLockKHRwsi_GetImageDrmFormatModifierPropertiesEXTwsi_GetBufferOpaqueCaptureAddresswsi_GetBufferOpaqueCaptureAddressKHRwsi_GetBufferDeviceAddresswsi_GetBufferDeviceAddressKHRwsi_GetBufferDeviceAddressEXTwsi_InitializePerformanceApiINTELwsi_UninitializePerformanceApiINTELwsi_CmdSetPerformanceMarkerINTELwsi_CmdSetPerformanceStreamMarkerINTELwsi_CmdSetPerformanceOverrideINTELwsi_AcquirePerformanceConfigurationINTELwsi_ReleasePerformanceConfigurationINTELwsi_QueueSetPerformanceConfigurationINTELwsi_GetPerformanceParameterINTELwsi_GetDeviceMemoryOpaqueCaptureAddresswsi_GetDeviceMemoryOpaqueCaptureAddressKHRwsi_GetPipelineExecutablePropertiesKHRwsi_GetPipelineExecutableStatisticsKHRwsi_GetPipelineExecutableInternalRepresentationsKHRwsi_CmdSetLineStippleKHRwsi_CmdSetLineStippleEXTwsi_CreateAccelerationStructureKHRwsi_CmdBuildAccelerationStructuresKHRwsi_CmdBuildAccelerationStructuresIndirectKHRwsi_BuildAccelerationStructuresKHRwsi_GetAccelerationStructureDeviceAddressKHRwsi_CreateDeferredOperationKHRwsi_DestroyDeferredOperationKHRwsi_GetDeferredOperationMaxConcurrencyKHRwsi_GetDeferredOperationResultKHRwsi_DeferredOperationJoinKHRwsi_GetPipelineIndirectMemoryRequirementsNVwsi_GetPipelineIndirectDeviceAddressNVwsi_CmdSetCullModewsi_CmdSetCullModeEXTwsi_CmdSetFrontFacewsi_CmdSetFrontFaceEXTwsi_CmdSetPrimitiveTopologywsi_CmdSetPrimitiveTopologyEXTwsi_CmdSetViewportWithCountwsi_CmdSetViewportWithCountEXTwsi_CmdSetScissorWithCountwsi_CmdSetScissorWithCountEXTwsi_CmdBindIndexBuffer2KHRwsi_CmdBindVertexBuffers2wsi_CmdBindVertexBuffers2EXTwsi_CmdSetDepthTestEnablewsi_CmdSetDepthTestEnableEXTwsi_CmdSetDepthWriteEnablewsi_CmdSetDepthWriteEnableEXTwsi_CmdSetDepthCompareOpwsi_CmdSetDepthCompareOpEXTwsi_CmdSetDepthBoundsTestEnablewsi_CmdSetDepthBoundsTestEnableEXTwsi_CmdSetStencilTestEnablewsi_CmdSetStencilTestEnableEXTwsi_CmdSetStencilOpwsi_CmdSetStencilOpEXTwsi_CmdSetPatchControlPointsEXTwsi_CmdSetRasterizerDiscardEnablewsi_CmdSetRasterizerDiscardEnableEXTwsi_CmdSetDepthBiasEnablewsi_CmdSetDepthBiasEnableEXTwsi_CmdSetLogicOpEXTwsi_CmdSetPrimitiveRestartEnablewsi_CmdSetPrimitiveRestartEnableEXTwsi_CmdSetTessellationDomainOriginEXTwsi_CmdSetDepthClampEnableEXTwsi_CmdSetPolygonModeEXTwsi_CmdSetRasterizationSamplesEXTwsi_CmdSetSampleMaskEXTwsi_CmdSetAlphaToCoverageEnableEXTwsi_CmdSetAlphaToOneEnableEXTwsi_CmdSetLogicOpEnableEXTwsi_CmdSetColorBlendEnableEXTwsi_CmdSetColorBlendEquationEXTwsi_CmdSetColorWriteMaskEXTwsi_CmdSetRasterizationStreamEXTwsi_CmdSetConservativeRasterizationModeEXTwsi_CmdSetExtraPrimitiveOverestimationSizeEXTwsi_CmdSetDepthClipEnableEXTwsi_CmdSetSampleLocationsEnableEXTwsi_CmdSetColorBlendAdvancedEXTwsi_CmdSetProvokingVertexModeEXTwsi_CmdSetLineRasterizationModeEXTwsi_CmdSetLineStippleEnableEXTwsi_CmdSetDepthClipNegativeOneToOneEXTwsi_CmdSetViewportWScalingEnableNVwsi_CmdSetViewportSwizzleNVwsi_CmdSetCoverageToColorEnableNVwsi_CmdSetCoverageToColorLocationNVwsi_CmdSetCoverageModulationModeNVwsi_CmdSetCoverageModulationTableEnableNVwsi_CmdSetCoverageModulationTableNVwsi_CmdSetShadingRateImageEnableNVwsi_CmdSetCoverageReductionModeNVwsi_CmdSetRepresentativeFragmentTestEnableNVwsi_CreatePrivateDataSlotwsi_CreatePrivateDataSlotEXTwsi_DestroyPrivateDataSlotwsi_DestroyPrivateDataSlotEXTwsi_SetPrivateDatawsi_SetPrivateDataEXTwsi_GetPrivateDatawsi_GetPrivateDataEXTwsi_CmdCopyBuffer2wsi_CmdCopyBuffer2KHRwsi_CmdCopyImage2wsi_CmdCopyImage2KHRwsi_CmdBlitImage2wsi_CmdBlitImage2KHRwsi_CmdCopyBufferToImage2wsi_CmdCopyBufferToImage2KHRwsi_CmdCopyImageToBuffer2wsi_CmdCopyImageToBuffer2KHRwsi_CmdResolveImage2wsi_CmdResolveImage2KHRwsi_CmdSetFragmentShadingRateKHRwsi_CmdSetFragmentShadingRateEnumNVwsi_GetAccelerationStructureBuildSizesKHRwsi_CmdSetVertexInputEXTwsi_CmdSetColorWriteEnableEXTwsi_CmdSetEvent2wsi_CmdSetEvent2KHRwsi_CmdResetEvent2wsi_CmdResetEvent2KHRwsi_CmdWaitEvents2wsi_CmdWaitEvents2KHRwsi_CmdPipelineBarrier2wsi_CmdPipelineBarrier2KHRwsi_QueueSubmit2wsi_QueueSubmit2KHRwsi_CmdWriteTimestamp2wsi_CmdWriteTimestamp2KHRwsi_CmdWriteBufferMarker2AMDwsi_GetQueueCheckpointData2NVwsi_CopyMemoryToImageEXTwsi_CopyImageToMemoryEXTwsi_CopyImageToImageEXTwsi_TransitionImageLayoutEXTwsi_CreateVideoSessionKHRwsi_DestroyVideoSessionKHRwsi_CreateVideoSessionParametersKHRwsi_UpdateVideoSessionParametersKHRwsi_GetEncodedVideoSessionParametersKHRwsi_DestroyVideoSessionParametersKHRwsi_GetVideoSessionMemoryRequirementsKHRwsi_BindVideoSessionMemoryKHRwsi_CmdDecodeVideoKHRwsi_CmdBeginVideoCodingKHRwsi_CmdControlVideoCodingKHRwsi_CmdEndVideoCodingKHRwsi_CmdEncodeVideoKHRwsi_CmdDecompressMemoryNVwsi_CmdDecompressMemoryIndirectCountNVwsi_CreateCuModuleNVXwsi_CreateCuFunctionNVXwsi_DestroyCuModuleNVXwsi_DestroyCuFunctionNVXwsi_CmdCuLaunchKernelNVXwsi_GetDescriptorSetLayoutSizeEXTwsi_GetDescriptorSetLayoutBindingOffsetEXTwsi_GetDescriptorEXTwsi_CmdBindDescriptorBuffersEXTwsi_CmdSetDescriptorBufferOffsetsEXTwsi_CmdBindDescriptorBufferEmbeddedSamplersEXTwsi_GetBufferOpaqueCaptureDescriptorDataEXTwsi_GetImageOpaqueCaptureDescriptorDataEXTwsi_GetImageViewOpaqueCaptureDescriptorDataEXTwsi_GetSamplerOpaqueCaptureDescriptorDataEXTwsi_GetAccelerationStructureOpaqueCaptureDescriptorDataEXTwsi_SetDeviceMemoryPriorityEXTwsi_CmdBeginRenderingwsi_CmdBeginRenderingKHRwsi_CmdEndRenderingwsi_CmdEndRenderingKHRwsi_GetDescriptorSetLayoutHostMappingInfoVALVEwsi_GetDescriptorSetHostMappingVALVEwsi_CreateMicromapEXTwsi_CmdBuildMicromapsEXTwsi_BuildMicromapsEXTwsi_DestroyMicromapEXTwsi_CmdCopyMicromapEXTwsi_CopyMicromapEXTwsi_CmdCopyMicromapToMemoryEXTwsi_CopyMicromapToMemoryEXTwsi_CmdCopyMemoryToMicromapEXTwsi_CopyMemoryToMicromapEXTwsi_CmdWriteMicromapsPropertiesEXTwsi_WriteMicromapsPropertiesEXTwsi_GetDeviceMicromapCompatibilityEXTwsi_GetMicromapBuildSizesEXTwsi_GetShaderModuleIdentifierEXTwsi_GetShaderModuleCreateInfoIdentifierEXTwsi_GetImageSubresourceLayout2KHRwsi_GetImageSubresourceLayout2EXTwsi_GetPipelinePropertiesEXTwsi_GetFramebufferTilePropertiesQCOMwsi_GetDynamicRenderingTilePropertiesQCOMwsi_CreateOpticalFlowSessionNVwsi_DestroyOpticalFlowSessionNVwsi_BindOpticalFlowSessionImageNVwsi_CmdOpticalFlowExecuteNVwsi_GetDeviceFaultInfoEXTwsi_CmdSetDepthBias2EXTwsi_GetDeviceImageSubresourceLayoutKHRwsi_MapMemory2KHRwsi_UnmapMemory2KHRwsi_CreateShadersEXTwsi_DestroyShaderEXTwsi_GetShaderBinaryDataEXTwsi_CmdBindShadersEXTwsi_CmdBindDescriptorSets2KHRwsi_CmdPushConstants2KHRwsi_CmdPushDescriptorSet2KHRwsi_CmdPushDescriptorSetWithTemplate2KHRwsi_CmdSetDescriptorBufferOffsets2EXTwsi_CmdBindDescriptorBufferEmbeddedSamplers2EXTwsi_SetLatencySleepModeNVwsi_LatencySleepNVwsi_SetLatencyMarkerNVwsi_GetLatencyTimingsNVwsi_QueueNotifyOutOfBandNVwsi_CmdSetRenderingAttachmentLocationsKHRwsi_CmdSetRenderingInputAttachmentIndicesKHRanv_GetDeviceProcAddranv_GetDeviceQueueanv_QueueSubmitanv_QueueWaitIdleanv_DeviceWaitIdleanv_GetBufferMemoryRequirementsanv_BindBufferMemoryanv_GetImageMemoryRequirementsanv_BindImageMemoryanv_CreateFenceanv_DestroyFenceanv_ResetFencesanv_GetFenceStatusanv_WaitForFencesanv_CreateSemaphoreanv_DestroySemaphoreanv_CreateQueryPoolanv_DestroyQueryPoolanv_GetQueryPoolResultsanv_ResetQueryPoolanv_ResetQueryPoolEXTanv_CreateShaderModuleanv_DestroyShaderModuleanv_CreatePipelineCacheanv_DestroyPipelineCacheanv_GetPipelineCacheDataanv_MergePipelineCachesanv_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIanv_CreateSampleranv_CreateFramebufferanv_DestroyFramebufferanv_CreateRenderPassanv_DestroyRenderPassanv_GetRenderAreaGranularityanv_GetRenderingAreaGranularityKHRanv_CreateCommandPoolanv_DestroyCommandPoolanv_ResetCommandPoolanv_AllocateCommandBuffersanv_FreeCommandBuffersanv_BeginCommandBufferanv_EndCommandBufferanv_ResetCommandBufferanv_CmdSetAttachmentFeedbackLoopEnableEXTanv_CmdSetViewportanv_CmdSetScissoranv_CmdSetLineWidthanv_CmdSetDepthBiasanv_CmdSetBlendConstantsanv_CmdSetDepthBoundsanv_CmdSetStencilCompareMaskanv_CmdSetStencilWriteMaskanv_CmdSetStencilReferenceanv_CmdBindIndexBufferanv_CmdBindVertexBuffersanv_CmdDrawanv_CmdDrawIndexedanv_CmdDrawMultiEXTanv_CmdDrawMultiIndexedEXTanv_CmdDrawIndirectanv_CmdDrawIndexedIndirectanv_CmdDispatchanv_CmdDispatchIndirectanv_CmdSubpassShadingHUAWEIanv_CmdDrawClusterHUAWEIanv_CmdDrawClusterIndirectHUAWEIanv_CmdUpdatePipelineIndirectBufferNVanv_CmdCopyBufferanv_CmdCopyImageanv_CmdBlitImageanv_CmdCopyBufferToImageanv_CmdCopyImageToBufferanv_CmdCopyMemoryIndirectNVanv_CmdCopyMemoryToImageIndirectNVanv_CmdResolveImageanv_CmdSetEventanv_CmdResetEventanv_CmdWaitEventsanv_CmdPipelineBarrieranv_CmdBeginQueryanv_CmdEndQueryanv_CmdBeginConditionalRenderingEXTanv_CmdEndConditionalRenderingEXTanv_CmdResetQueryPoolanv_CmdWriteTimestampanv_CmdCopyQueryPoolResultsanv_CmdBeginRenderPassanv_CmdNextSubpassanv_CmdEndRenderPassanv_CmdExecuteCommandsanv_CreateSharedSwapchainsKHRanv_CreateSwapchainKHRanv_DestroySwapchainKHRanv_GetSwapchainImagesKHRanv_AcquireNextImageKHRanv_DebugMarkerSetObjectNameEXTanv_DebugMarkerSetObjectTagEXTanv_CmdDebugMarkerBeginEXTanv_CmdDebugMarkerEndEXTanv_CmdDebugMarkerInsertEXTanv_CmdExecuteGeneratedCommandsNVanv_CmdPreprocessGeneratedCommandsNVanv_CmdBindPipelineShaderGroupNVanv_GetGeneratedCommandsMemoryRequirementsNVanv_CreateIndirectCommandsLayoutNVanv_DestroyIndirectCommandsLayoutNVanv_TrimCommandPoolanv_TrimCommandPoolKHRanv_GetMemoryRemoteAddressNVanv_GetSemaphoreFdKHRanv_ImportSemaphoreFdKHRanv_GetFenceFdKHRanv_ImportFenceFdKHRanv_DisplayPowerControlEXTanv_RegisterDeviceEventEXTanv_RegisterDisplayEventEXTanv_GetSwapchainCounterEXTanv_GetDeviceGroupPeerMemoryFeaturesanv_GetDeviceGroupPeerMemoryFeaturesKHRanv_BindBufferMemory2KHRanv_BindImageMemory2KHRanv_CmdSetDeviceMaskanv_CmdSetDeviceMaskKHRanv_GetDeviceGroupPresentCapabilitiesKHRanv_GetDeviceGroupSurfacePresentModesKHRanv_CmdDispatchBaseanv_CmdDispatchBaseKHRanv_CreateDescriptorUpdateTemplateanv_CreateDescriptorUpdateTemplateKHRanv_DestroyDescriptorUpdateTemplateanv_DestroyDescriptorUpdateTemplateKHRanv_UpdateDescriptorSetWithTemplateKHRanv_SetHdrMetadataEXTanv_GetSwapchainStatusKHRanv_GetRefreshCycleDurationGOOGLEanv_GetPastPresentationTimingGOOGLEanv_CmdSetViewportWScalingNVanv_CmdSetDiscardRectangleEXTanv_CmdSetDiscardRectangleEnableEXTanv_CmdSetDiscardRectangleModeEXTanv_CmdSetSampleLocationsEXTanv_GetBufferMemoryRequirements2KHRanv_GetImageMemoryRequirements2KHRanv_GetImageSparseMemoryRequirements2KHRanv_GetDeviceBufferMemoryRequirementsKHRanv_GetDeviceImageMemoryRequirementsKHRanv_GetDeviceImageSparseMemoryRequirementsKHRanv_CreateSamplerYcbcrConversionanv_CreateSamplerYcbcrConversionKHRanv_DestroySamplerYcbcrConversionanv_DestroySamplerYcbcrConversionKHRanv_GetDeviceQueue2anv_CreateValidationCacheEXTanv_DestroyValidationCacheEXTanv_GetValidationCacheDataEXTanv_MergeValidationCachesEXTanv_GetDescriptorSetLayoutSupportKHRanv_GetShaderInfoAMDanv_SetLocalDimmingAMDanv_GetCalibratedTimestampsKHRanv_SetDebugUtilsObjectNameEXTanv_SetDebugUtilsObjectTagEXTanv_QueueBeginDebugUtilsLabelEXTanv_QueueEndDebugUtilsLabelEXTanv_QueueInsertDebugUtilsLabelEXTanv_CmdBeginDebugUtilsLabelEXTanv_CmdEndDebugUtilsLabelEXTanv_CmdInsertDebugUtilsLabelEXTanv_CmdWriteBufferMarkerAMDanv_CreateRenderPass2anv_CreateRenderPass2KHRanv_CmdBeginRenderPass2anv_CmdBeginRenderPass2KHRanv_CmdNextSubpass2anv_CmdNextSubpass2KHRanv_CmdEndRenderPass2anv_CmdEndRenderPass2KHRanv_GetSemaphoreCounterValueanv_GetSemaphoreCounterValueKHRanv_WaitSemaphoresanv_WaitSemaphoresKHRanv_SignalSemaphoreanv_SignalSemaphoreKHRanv_CmdDrawIndirectCountanv_CmdDrawIndirectCountKHRanv_CmdDrawIndirectCountAMDanv_CmdDrawIndexedIndirectCountanv_CmdDrawIndexedIndirectCountKHRanv_CmdDrawIndexedIndirectCountAMDanv_CmdSetCheckpointNVanv_GetQueueCheckpointDataNVanv_CmdBeginTransformFeedbackEXTanv_CmdEndTransformFeedbackEXTanv_CmdBeginQueryIndexedEXTanv_CmdEndQueryIndexedEXTanv_CmdDrawIndirectByteCountEXTanv_CmdSetExclusiveScissorNVanv_CmdSetExclusiveScissorEnableNVanv_CmdBindShadingRateImageNVanv_CmdSetViewportShadingRatePaletteNVanv_CmdSetCoarseSampleOrderNVanv_CmdDrawMeshTasksNVanv_CmdDrawMeshTasksIndirectNVanv_CmdDrawMeshTasksIndirectCountNVanv_CmdDrawMeshTasksEXTanv_CmdDrawMeshTasksIndirectEXTanv_CmdDrawMeshTasksIndirectCountEXTanv_CompileDeferredNVanv_CreateAccelerationStructureNVanv_CmdBindInvocationMaskHUAWEIanv_DestroyAccelerationStructureKHRanv_DestroyAccelerationStructureNVanv_GetAccelerationStructureMemoryRequirementsNVanv_BindAccelerationStructureMemoryNVanv_CmdCopyAccelerationStructureNVanv_CmdCopyAccelerationStructureKHRanv_CopyAccelerationStructureKHRanv_CmdCopyAccelerationStructureToMemoryKHRanv_CopyAccelerationStructureToMemoryKHRanv_CmdCopyMemoryToAccelerationStructureKHRanv_CopyMemoryToAccelerationStructureKHRanv_CmdWriteAccelerationStructuresPropertiesKHRanv_CmdWriteAccelerationStructuresPropertiesNVanv_CmdBuildAccelerationStructureNVanv_WriteAccelerationStructuresPropertiesKHRanv_CmdTraceRaysKHRanv_CmdTraceRaysNVanv_GetRayTracingShaderGroupHandlesKHRanv_GetRayTracingShaderGroupHandlesNVanv_GetRayTracingCaptureReplayShaderGroupHandlesKHRanv_GetAccelerationStructureHandleNVanv_CreateRayTracingPipelinesNVanv_CreateRayTracingPipelinesKHRanv_CmdTraceRaysIndirectKHRanv_CmdTraceRaysIndirect2KHRanv_GetDeviceAccelerationStructureCompatibilityKHRanv_GetRayTracingShaderGroupStackSizeKHRanv_CmdSetRayTracingPipelineStackSizeKHRanv_GetImageViewHandleNVXanv_GetImageViewAddressNVXanv_GetImageDrmFormatModifierPropertiesEXTanv_GetBufferOpaqueCaptureAddressKHRanv_GetBufferDeviceAddressKHRanv_GetBufferDeviceAddressEXTanv_CmdSetPerformanceStreamMarkerINTELanv_CmdSetPerformanceOverrideINTELanv_GetDeviceMemoryOpaqueCaptureAddressKHRanv_CmdSetLineStippleKHRanv_CmdSetLineStippleEXTanv_CreateAccelerationStructureKHRanv_CmdBuildAccelerationStructuresKHRanv_CmdBuildAccelerationStructuresIndirectKHRanv_BuildAccelerationStructuresKHRanv_GetAccelerationStructureDeviceAddressKHRanv_CreateDeferredOperationKHRanv_DestroyDeferredOperationKHRanv_GetDeferredOperationMaxConcurrencyKHRanv_GetDeferredOperationResultKHRanv_DeferredOperationJoinKHRanv_GetPipelineIndirectMemoryRequirementsNVanv_GetPipelineIndirectDeviceAddressNVanv_CmdSetCullModeanv_CmdSetCullModeEXTanv_CmdSetFrontFaceanv_CmdSetFrontFaceEXTanv_CmdSetPrimitiveTopologyanv_CmdSetPrimitiveTopologyEXTanv_CmdSetViewportWithCountanv_CmdSetViewportWithCountEXTanv_CmdSetScissorWithCountanv_CmdSetScissorWithCountEXTanv_CmdBindIndexBuffer2KHRanv_CmdBindVertexBuffers2EXTanv_CmdSetDepthTestEnableanv_CmdSetDepthTestEnableEXTanv_CmdSetDepthWriteEnableanv_CmdSetDepthWriteEnableEXTanv_CmdSetDepthCompareOpanv_CmdSetDepthCompareOpEXTanv_CmdSetDepthBoundsTestEnableanv_CmdSetDepthBoundsTestEnableEXTanv_CmdSetStencilTestEnableanv_CmdSetStencilTestEnableEXTanv_CmdSetStencilOpanv_CmdSetStencilOpEXTanv_CmdSetPatchControlPointsEXTanv_CmdSetRasterizerDiscardEnableanv_CmdSetRasterizerDiscardEnableEXTanv_CmdSetDepthBiasEnableanv_CmdSetDepthBiasEnableEXTanv_CmdSetLogicOpEXTanv_CmdSetPrimitiveRestartEnableanv_CmdSetPrimitiveRestartEnableEXTanv_CmdSetTessellationDomainOriginEXTanv_CmdSetDepthClampEnableEXTanv_CmdSetPolygonModeEXTanv_CmdSetRasterizationSamplesEXTanv_CmdSetSampleMaskEXTanv_CmdSetAlphaToCoverageEnableEXTanv_CmdSetAlphaToOneEnableEXTanv_CmdSetLogicOpEnableEXTanv_CmdSetColorBlendEnableEXTanv_CmdSetColorBlendEquationEXTanv_CmdSetColorWriteMaskEXTanv_CmdSetRasterizationStreamEXTanv_CmdSetConservativeRasterizationModeEXTanv_CmdSetExtraPrimitiveOverestimationSizeEXTanv_CmdSetDepthClipEnableEXTanv_CmdSetSampleLocationsEnableEXTanv_CmdSetColorBlendAdvancedEXTanv_CmdSetProvokingVertexModeEXTanv_CmdSetLineRasterizationModeEXTanv_CmdSetLineStippleEnableEXTanv_CmdSetDepthClipNegativeOneToOneEXTanv_CmdSetViewportWScalingEnableNVanv_CmdSetViewportSwizzleNVanv_CmdSetCoverageToColorEnableNVanv_CmdSetCoverageToColorLocationNVanv_CmdSetCoverageModulationModeNVanv_CmdSetCoverageModulationTableEnableNVanv_CmdSetCoverageModulationTableNVanv_CmdSetShadingRateImageEnableNVanv_CmdSetCoverageReductionModeNVanv_CmdSetRepresentativeFragmentTestEnableNVanv_CreatePrivateDataSlotanv_CreatePrivateDataSlotEXTanv_DestroyPrivateDataSlotanv_DestroyPrivateDataSlotEXTanv_SetPrivateDataanv_SetPrivateDataEXTanv_GetPrivateDataanv_GetPrivateDataEXTanv_CmdCopyBuffer2KHRanv_CmdCopyImage2KHRanv_CmdBlitImage2KHRanv_CmdCopyBufferToImage2KHRanv_CmdCopyImageToBuffer2KHRanv_CmdResolveImage2KHRanv_CmdSetFragmentShadingRateKHRanv_CmdSetFragmentShadingRateEnumNVanv_GetAccelerationStructureBuildSizesKHRanv_CmdSetVertexInputEXTanv_CmdSetColorWriteEnableEXTanv_CmdSetEvent2anv_CmdSetEvent2KHRanv_CmdResetEvent2anv_CmdResetEvent2KHRanv_CmdWaitEvents2anv_CmdWaitEvents2KHRanv_CmdPipelineBarrier2anv_CmdPipelineBarrier2KHRanv_QueueSubmit2anv_QueueSubmit2KHRanv_CmdWriteTimestamp2anv_CmdWriteTimestamp2KHRanv_CmdWriteBufferMarker2AMDanv_GetQueueCheckpointData2NVanv_CopyMemoryToImageEXTanv_CopyImageToMemoryEXTanv_CopyImageToImageEXTanv_TransitionImageLayoutEXTanv_CreateVideoSessionKHRanv_DestroyVideoSessionKHRanv_CreateVideoSessionParametersKHRanv_UpdateVideoSessionParametersKHRanv_GetEncodedVideoSessionParametersKHRanv_DestroyVideoSessionParametersKHRanv_GetVideoSessionMemoryRequirementsKHRanv_BindVideoSessionMemoryKHRanv_CmdDecodeVideoKHRanv_CmdBeginVideoCodingKHRanv_CmdControlVideoCodingKHRanv_CmdEndVideoCodingKHRanv_CmdEncodeVideoKHRanv_CmdDecompressMemoryNVanv_CmdDecompressMemoryIndirectCountNVanv_CreateCuModuleNVXanv_CreateCuFunctionNVXanv_DestroyCuModuleNVXanv_DestroyCuFunctionNVXanv_CmdCuLaunchKernelNVXanv_GetDescriptorSetLayoutSizeEXTanv_GetDescriptorSetLayoutBindingOffsetEXTanv_GetDescriptorEXTanv_CmdBindDescriptorBuffersEXTanv_CmdSetDescriptorBufferOffsetsEXTanv_CmdBindDescriptorBufferEmbeddedSamplersEXTanv_GetBufferOpaqueCaptureDescriptorDataEXTanv_GetImageOpaqueCaptureDescriptorDataEXTanv_GetImageViewOpaqueCaptureDescriptorDataEXTanv_GetSamplerOpaqueCaptureDescriptorDataEXTanv_GetAccelerationStructureOpaqueCaptureDescriptorDataEXTanv_SetDeviceMemoryPriorityEXTanv_WaitForPresentKHRanv_CmdBeginRenderinganv_CmdBeginRenderingKHRanv_CmdEndRenderinganv_CmdEndRenderingKHRanv_GetDescriptorSetLayoutHostMappingInfoVALVEanv_GetDescriptorSetHostMappingVALVEanv_CreateMicromapEXTanv_CmdBuildMicromapsEXTanv_BuildMicromapsEXTanv_DestroyMicromapEXTanv_CmdCopyMicromapEXTanv_CopyMicromapEXTanv_CmdCopyMicromapToMemoryEXTanv_CopyMicromapToMemoryEXTanv_CmdCopyMemoryToMicromapEXTanv_CopyMemoryToMicromapEXTanv_CmdWriteMicromapsPropertiesEXTanv_WriteMicromapsPropertiesEXTanv_GetDeviceMicromapCompatibilityEXTanv_GetMicromapBuildSizesEXTanv_GetShaderModuleIdentifierEXTanv_GetShaderModuleCreateInfoIdentifierEXTanv_GetImageSubresourceLayout2KHRanv_GetImageSubresourceLayout2EXTanv_GetPipelinePropertiesEXTanv_GetFramebufferTilePropertiesQCOManv_GetDynamicRenderingTilePropertiesQCOManv_CreateOpticalFlowSessionNVanv_DestroyOpticalFlowSessionNVanv_BindOpticalFlowSessionImageNVanv_CmdOpticalFlowExecuteNVanv_GetDeviceFaultInfoEXTanv_CmdSetDepthBias2EXTanv_ReleaseSwapchainImagesEXTanv_GetDeviceImageSubresourceLayoutKHRanv_MapMemory2KHRanv_UnmapMemory2KHRanv_CreateShadersEXTanv_DestroyShaderEXTanv_GetShaderBinaryDataEXTanv_CmdBindShadersEXTanv_CmdBindDescriptorSets2KHRanv_CmdPushConstants2KHRanv_CmdPushDescriptorSet2KHRanv_CmdPushDescriptorSetWithTemplate2KHRanv_CmdSetDescriptorBufferOffsets2EXTanv_CmdBindDescriptorBufferEmbeddedSamplers2EXTanv_SetLatencySleepModeNVanv_LatencySleepNVanv_SetLatencyMarkerNVanv_GetLatencyTimingsNVanv_QueueNotifyOutOfBandNVanv_CmdSetRenderingAttachmentLocationsKHRanv_CmdSetRenderingInputAttachmentIndicesKHRdoom64_GetDeviceProcAddrdoom64_DestroyDevicedoom64_GetDeviceQueuedoom64_QueueSubmitdoom64_QueueWaitIdledoom64_DeviceWaitIdledoom64_AllocateMemorydoom64_FreeMemorydoom64_MapMemorydoom64_UnmapMemorydoom64_FlushMappedMemoryRangesdoom64_InvalidateMappedMemoryRangesdoom64_GetDeviceMemoryCommitmentdoom64_GetBufferMemoryRequirementsdoom64_BindBufferMemorydoom64_GetImageMemoryRequirementsdoom64_BindImageMemorydoom64_GetImageSparseMemoryRequirementsdoom64_QueueBindSparsedoom64_CreateFencedoom64_DestroyFencedoom64_ResetFencesdoom64_GetFenceStatusdoom64_WaitForFencesdoom64_CreateSemaphoredoom64_DestroySemaphoredoom64_CreateEventdoom64_DestroyEventdoom64_GetEventStatusdoom64_SetEventdoom64_ResetEventdoom64_CreateQueryPooldoom64_DestroyQueryPooldoom64_GetQueryPoolResultsdoom64_ResetQueryPooldoom64_ResetQueryPoolEXTdoom64_CreateBufferdoom64_DestroyBufferdoom64_CreateBufferViewdoom64_DestroyBufferViewdoom64_GetImageSubresourceLayoutdoom64_CreateImageViewdoom64_DestroyImageViewdoom64_CreateShaderModuledoom64_DestroyShaderModuledoom64_CreatePipelineCachedoom64_DestroyPipelineCachedoom64_GetPipelineCacheDatadoom64_MergePipelineCachesdoom64_CreateGraphicsPipelinesdoom64_CreateComputePipelinesdoom64_GetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIdoom64_DestroyPipelinedoom64_CreatePipelineLayoutdoom64_DestroyPipelineLayoutdoom64_CreateSamplerdoom64_DestroySamplerdoom64_CreateDescriptorSetLayoutdoom64_DestroyDescriptorSetLayoutdoom64_CreateDescriptorPooldoom64_DestroyDescriptorPooldoom64_ResetDescriptorPooldoom64_AllocateDescriptorSetsdoom64_FreeDescriptorSetsdoom64_UpdateDescriptorSetsdoom64_CreateFramebufferdoom64_DestroyFramebufferdoom64_CreateRenderPassdoom64_DestroyRenderPassdoom64_GetRenderAreaGranularitydoom64_GetRenderingAreaGranularityKHRdoom64_CreateCommandPooldoom64_DestroyCommandPooldoom64_ResetCommandPooldoom64_AllocateCommandBuffersdoom64_FreeCommandBuffersdoom64_BeginCommandBufferdoom64_EndCommandBufferdoom64_ResetCommandBufferdoom64_CmdBindPipelinedoom64_CmdSetAttachmentFeedbackLoopEnableEXTdoom64_CmdSetViewportdoom64_CmdSetScissordoom64_CmdSetLineWidthdoom64_CmdSetDepthBiasdoom64_CmdSetBlendConstantsdoom64_CmdSetDepthBoundsdoom64_CmdSetStencilCompareMaskdoom64_CmdSetStencilWriteMaskdoom64_CmdSetStencilReferencedoom64_CmdBindDescriptorSetsdoom64_CmdBindIndexBufferdoom64_CmdBindVertexBuffersdoom64_CmdDrawdoom64_CmdDrawIndexeddoom64_CmdDrawMultiEXTdoom64_CmdDrawMultiIndexedEXTdoom64_CmdDrawIndirectdoom64_CmdDrawIndexedIndirectdoom64_CmdDispatchdoom64_CmdDispatchIndirectdoom64_CmdSubpassShadingHUAWEIdoom64_CmdDrawClusterHUAWEIdoom64_CmdDrawClusterIndirectHUAWEIdoom64_CmdUpdatePipelineIndirectBufferNVdoom64_CmdCopyBufferdoom64_CmdCopyImagedoom64_CmdBlitImagedoom64_CmdCopyBufferToImagedoom64_CmdCopyImageToBufferdoom64_CmdCopyMemoryIndirectNVdoom64_CmdCopyMemoryToImageIndirectNVdoom64_CmdUpdateBufferdoom64_CmdFillBufferdoom64_CmdClearColorImagedoom64_CmdClearDepthStencilImagedoom64_CmdClearAttachmentsdoom64_CmdResolveImagedoom64_CmdSetEventdoom64_CmdResetEventdoom64_CmdWaitEventsdoom64_CmdBeginQuerydoom64_CmdEndQuerydoom64_CmdBeginConditionalRenderingEXTdoom64_CmdEndConditionalRenderingEXTdoom64_CmdResetQueryPooldoom64_CmdWriteTimestampdoom64_CmdCopyQueryPoolResultsdoom64_CmdPushConstantsdoom64_CmdBeginRenderPassdoom64_CmdNextSubpassdoom64_CmdEndRenderPassdoom64_CmdExecuteCommandsdoom64_CreateSharedSwapchainsKHRdoom64_CreateSwapchainKHRdoom64_DestroySwapchainKHRdoom64_GetSwapchainImagesKHRdoom64_AcquireNextImageKHRdoom64_QueuePresentKHRdoom64_DebugMarkerSetObjectNameEXTdoom64_DebugMarkerSetObjectTagEXTdoom64_CmdDebugMarkerBeginEXTdoom64_CmdDebugMarkerEndEXTdoom64_CmdDebugMarkerInsertEXTdoom64_CmdExecuteGeneratedCommandsNVdoom64_CmdPreprocessGeneratedCommandsNVdoom64_CmdBindPipelineShaderGroupNVdoom64_GetGeneratedCommandsMemoryRequirementsNVdoom64_CreateIndirectCommandsLayoutNVdoom64_DestroyIndirectCommandsLayoutNVdoom64_CmdPushDescriptorSetKHRdoom64_TrimCommandPooldoom64_TrimCommandPoolKHRdoom64_GetMemoryFdKHRdoom64_GetMemoryFdPropertiesKHRdoom64_GetMemoryRemoteAddressNVdoom64_GetSemaphoreFdKHRdoom64_ImportSemaphoreFdKHRdoom64_GetFenceFdKHRdoom64_ImportFenceFdKHRdoom64_DisplayPowerControlEXTdoom64_RegisterDeviceEventEXTdoom64_RegisterDisplayEventEXTdoom64_GetSwapchainCounterEXTdoom64_GetDeviceGroupPeerMemoryFeaturesdoom64_GetDeviceGroupPeerMemoryFeaturesKHRdoom64_BindBufferMemory2doom64_BindBufferMemory2KHRdoom64_BindImageMemory2doom64_BindImageMemory2KHRdoom64_CmdSetDeviceMaskdoom64_CmdSetDeviceMaskKHRdoom64_GetDeviceGroupPresentCapabilitiesKHRdoom64_GetDeviceGroupSurfacePresentModesKHRdoom64_AcquireNextImage2KHRdoom64_CmdDispatchBasedoom64_CmdDispatchBaseKHRdoom64_CreateDescriptorUpdateTemplatedoom64_CreateDescriptorUpdateTemplateKHRdoom64_DestroyDescriptorUpdateTemplatedoom64_DestroyDescriptorUpdateTemplateKHRdoom64_UpdateDescriptorSetWithTemplatedoom64_UpdateDescriptorSetWithTemplateKHRdoom64_CmdPushDescriptorSetWithTemplateKHRdoom64_SetHdrMetadataEXTdoom64_GetSwapchainStatusKHRdoom64_GetRefreshCycleDurationGOOGLEdoom64_GetPastPresentationTimingGOOGLEdoom64_CmdSetViewportWScalingNVdoom64_CmdSetDiscardRectangleEXTdoom64_CmdSetDiscardRectangleEnableEXTdoom64_CmdSetDiscardRectangleModeEXTdoom64_CmdSetSampleLocationsEXTdoom64_GetBufferMemoryRequirements2doom64_GetBufferMemoryRequirements2KHRdoom64_GetImageMemoryRequirements2doom64_GetImageMemoryRequirements2KHRdoom64_GetImageSparseMemoryRequirements2doom64_GetImageSparseMemoryRequirements2KHRdoom64_GetDeviceBufferMemoryRequirementsdoom64_GetDeviceBufferMemoryRequirementsKHRdoom64_GetDeviceImageMemoryRequirementsdoom64_GetDeviceImageMemoryRequirementsKHRdoom64_GetDeviceImageSparseMemoryRequirementsdoom64_GetDeviceImageSparseMemoryRequirementsKHRdoom64_CreateSamplerYcbcrConversiondoom64_CreateSamplerYcbcrConversionKHRdoom64_DestroySamplerYcbcrConversiondoom64_DestroySamplerYcbcrConversionKHRdoom64_GetDeviceQueue2doom64_CreateValidationCacheEXTdoom64_DestroyValidationCacheEXTdoom64_GetValidationCacheDataEXTdoom64_MergeValidationCachesEXTdoom64_GetDescriptorSetLayoutSupportdoom64_GetDescriptorSetLayoutSupportKHRdoom64_GetShaderInfoAMDdoom64_SetLocalDimmingAMDdoom64_GetCalibratedTimestampsKHRdoom64_GetCalibratedTimestampsEXTdoom64_SetDebugUtilsObjectNameEXTdoom64_SetDebugUtilsObjectTagEXTdoom64_QueueBeginDebugUtilsLabelEXTdoom64_QueueEndDebugUtilsLabelEXTdoom64_QueueInsertDebugUtilsLabelEXTdoom64_CmdBeginDebugUtilsLabelEXTdoom64_CmdEndDebugUtilsLabelEXTdoom64_CmdInsertDebugUtilsLabelEXTdoom64_GetMemoryHostPointerPropertiesEXTdoom64_CmdWriteBufferMarkerAMDdoom64_CreateRenderPass2doom64_CreateRenderPass2KHRdoom64_CmdBeginRenderPass2doom64_CmdBeginRenderPass2KHRdoom64_CmdNextSubpass2doom64_CmdNextSubpass2KHRdoom64_CmdEndRenderPass2doom64_CmdEndRenderPass2KHRdoom64_GetSemaphoreCounterValuedoom64_GetSemaphoreCounterValueKHRdoom64_WaitSemaphoresdoom64_WaitSemaphoresKHRdoom64_SignalSemaphoredoom64_SignalSemaphoreKHRdoom64_CmdDrawIndirectCountdoom64_CmdDrawIndirectCountKHRdoom64_CmdDrawIndirectCountAMDdoom64_CmdDrawIndexedIndirectCountdoom64_CmdDrawIndexedIndirectCountKHRdoom64_CmdDrawIndexedIndirectCountAMDdoom64_CmdSetCheckpointNVdoom64_GetQueueCheckpointDataNVdoom64_CmdBindTransformFeedbackBuffersEXTdoom64_CmdBeginTransformFeedbackEXTdoom64_CmdEndTransformFeedbackEXTdoom64_CmdBeginQueryIndexedEXTdoom64_CmdEndQueryIndexedEXTdoom64_CmdDrawIndirectByteCountEXTdoom64_CmdSetExclusiveScissorNVdoom64_CmdSetExclusiveScissorEnableNVdoom64_CmdBindShadingRateImageNVdoom64_CmdSetViewportShadingRatePaletteNVdoom64_CmdSetCoarseSampleOrderNVdoom64_CmdDrawMeshTasksNVdoom64_CmdDrawMeshTasksIndirectNVdoom64_CmdDrawMeshTasksIndirectCountNVdoom64_CmdDrawMeshTasksEXTdoom64_CmdDrawMeshTasksIndirectEXTdoom64_CmdDrawMeshTasksIndirectCountEXTdoom64_CompileDeferredNVdoom64_CreateAccelerationStructureNVdoom64_CmdBindInvocationMaskHUAWEIdoom64_DestroyAccelerationStructureKHRdoom64_DestroyAccelerationStructureNVdoom64_GetAccelerationStructureMemoryRequirementsNVdoom64_BindAccelerationStructureMemoryNVdoom64_CmdCopyAccelerationStructureNVdoom64_CmdCopyAccelerationStructureKHRdoom64_CopyAccelerationStructureKHRdoom64_CmdCopyAccelerationStructureToMemoryKHRdoom64_CopyAccelerationStructureToMemoryKHRdoom64_CmdCopyMemoryToAccelerationStructureKHRdoom64_CopyMemoryToAccelerationStructureKHRdoom64_CmdWriteAccelerationStructuresPropertiesKHRdoom64_CmdWriteAccelerationStructuresPropertiesNVdoom64_CmdBuildAccelerationStructureNVdoom64_WriteAccelerationStructuresPropertiesKHRdoom64_CmdTraceRaysKHRdoom64_CmdTraceRaysNVdoom64_GetRayTracingShaderGroupHandlesKHRdoom64_GetRayTracingShaderGroupHandlesNVdoom64_GetRayTracingCaptureReplayShaderGroupHandlesKHRdoom64_GetAccelerationStructureHandleNVdoom64_CreateRayTracingPipelinesNVdoom64_CreateRayTracingPipelinesKHRdoom64_CmdTraceRaysIndirectKHRdoom64_CmdTraceRaysIndirect2KHRdoom64_GetDeviceAccelerationStructureCompatibilityKHRdoom64_GetRayTracingShaderGroupStackSizeKHRdoom64_CmdSetRayTracingPipelineStackSizeKHRdoom64_GetImageViewHandleNVXdoom64_GetImageViewAddressNVXdoom64_AcquireProfilingLockKHRdoom64_ReleaseProfilingLockKHRdoom64_GetImageDrmFormatModifierPropertiesEXTdoom64_GetBufferOpaqueCaptureAddressdoom64_GetBufferOpaqueCaptureAddressKHRdoom64_GetBufferDeviceAddressdoom64_GetBufferDeviceAddressKHRdoom64_GetBufferDeviceAddressEXTdoom64_InitializePerformanceApiINTELdoom64_UninitializePerformanceApiINTELdoom64_CmdSetPerformanceMarkerINTELdoom64_CmdSetPerformanceStreamMarkerINTELdoom64_CmdSetPerformanceOverrideINTELdoom64_AcquirePerformanceConfigurationINTELdoom64_ReleasePerformanceConfigurationINTELdoom64_QueueSetPerformanceConfigurationINTELdoom64_GetPerformanceParameterINTELdoom64_GetDeviceMemoryOpaqueCaptureAddressdoom64_GetDeviceMemoryOpaqueCaptureAddressKHRdoom64_GetPipelineExecutablePropertiesKHRdoom64_GetPipelineExecutableStatisticsKHRdoom64_GetPipelineExecutableInternalRepresentationsKHRdoom64_CmdSetLineStippleKHRdoom64_CmdSetLineStippleEXTdoom64_CreateAccelerationStructureKHRdoom64_CmdBuildAccelerationStructuresKHRdoom64_CmdBuildAccelerationStructuresIndirectKHRdoom64_BuildAccelerationStructuresKHRdoom64_GetAccelerationStructureDeviceAddressKHRdoom64_CreateDeferredOperationKHRdoom64_DestroyDeferredOperationKHRdoom64_GetDeferredOperationMaxConcurrencyKHRdoom64_GetDeferredOperationResultKHRdoom64_DeferredOperationJoinKHRdoom64_GetPipelineIndirectMemoryRequirementsNVdoom64_GetPipelineIndirectDeviceAddressNVdoom64_CmdSetCullModedoom64_CmdSetCullModeEXTdoom64_CmdSetFrontFacedoom64_CmdSetFrontFaceEXTdoom64_CmdSetPrimitiveTopologydoom64_CmdSetPrimitiveTopologyEXTdoom64_CmdSetViewportWithCountdoom64_CmdSetViewportWithCountEXTdoom64_CmdSetScissorWithCountdoom64_CmdSetScissorWithCountEXTdoom64_CmdBindIndexBuffer2KHRdoom64_CmdBindVertexBuffers2doom64_CmdBindVertexBuffers2EXTdoom64_CmdSetDepthTestEnabledoom64_CmdSetDepthTestEnableEXTdoom64_CmdSetDepthWriteEnabledoom64_CmdSetDepthWriteEnableEXTdoom64_CmdSetDepthCompareOpdoom64_CmdSetDepthCompareOpEXTdoom64_CmdSetDepthBoundsTestEnabledoom64_CmdSetDepthBoundsTestEnableEXTdoom64_CmdSetStencilTestEnabledoom64_CmdSetStencilTestEnableEXTdoom64_CmdSetStencilOpdoom64_CmdSetStencilOpEXTdoom64_CmdSetPatchControlPointsEXTdoom64_CmdSetRasterizerDiscardEnabledoom64_CmdSetRasterizerDiscardEnableEXTdoom64_CmdSetDepthBiasEnabledoom64_CmdSetDepthBiasEnableEXTdoom64_CmdSetLogicOpEXTdoom64_CmdSetPrimitiveRestartEnabledoom64_CmdSetPrimitiveRestartEnableEXTdoom64_CmdSetTessellationDomainOriginEXTdoom64_CmdSetDepthClampEnableEXTdoom64_CmdSetPolygonModeEXTdoom64_CmdSetRasterizationSamplesEXTdoom64_CmdSetSampleMaskEXTdoom64_CmdSetAlphaToCoverageEnableEXTdoom64_CmdSetAlphaToOneEnableEXTdoom64_CmdSetLogicOpEnableEXTdoom64_CmdSetColorBlendEnableEXTdoom64_CmdSetColorBlendEquationEXTdoom64_CmdSetColorWriteMaskEXTdoom64_CmdSetRasterizationStreamEXTdoom64_CmdSetConservativeRasterizationModeEXTdoom64_CmdSetExtraPrimitiveOverestimationSizeEXTdoom64_CmdSetDepthClipEnableEXTdoom64_CmdSetSampleLocationsEnableEXTdoom64_CmdSetColorBlendAdvancedEXTdoom64_CmdSetProvokingVertexModeEXTdoom64_CmdSetLineRasterizationModeEXTdoom64_CmdSetLineStippleEnableEXTdoom64_CmdSetDepthClipNegativeOneToOneEXTdoom64_CmdSetViewportWScalingEnableNVdoom64_CmdSetViewportSwizzleNVdoom64_CmdSetCoverageToColorEnableNVdoom64_CmdSetCoverageToColorLocationNVdoom64_CmdSetCoverageModulationModeNVdoom64_CmdSetCoverageModulationTableEnableNVdoom64_CmdSetCoverageModulationTableNVdoom64_CmdSetShadingRateImageEnableNVdoom64_CmdSetCoverageReductionModeNVdoom64_CmdSetRepresentativeFragmentTestEnableNVdoom64_CreatePrivateDataSlotdoom64_CreatePrivateDataSlotEXTdoom64_DestroyPrivateDataSlotdoom64_DestroyPrivateDataSlotEXTdoom64_SetPrivateDatadoom64_SetPrivateDataEXTdoom64_GetPrivateDatadoom64_GetPrivateDataEXTdoom64_CmdCopyBuffer2doom64_CmdCopyBuffer2KHRdoom64_CmdCopyImage2doom64_CmdCopyImage2KHRdoom64_CmdBlitImage2doom64_CmdBlitImage2KHRdoom64_CmdCopyBufferToImage2doom64_CmdCopyBufferToImage2KHRdoom64_CmdCopyImageToBuffer2doom64_CmdCopyImageToBuffer2KHRdoom64_CmdResolveImage2doom64_CmdResolveImage2KHRdoom64_CmdSetFragmentShadingRateKHRdoom64_CmdSetFragmentShadingRateEnumNVdoom64_GetAccelerationStructureBuildSizesKHRdoom64_CmdSetVert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x HLA<1ɺ(y HLAlff.AVAUATL%UUHS0+HH UH{8Ls(HCHCLc H$U111HCxHSUHLHǃRǃ1ɺHL?L?HH XHDyDAAAuTHcC0HI>HIDƸH!H@(HHC8HLULH֏HtL`HX[]A\A]A^1ɺ0~ HL 1ɺ{ HLAW1ɺ | HLA<1ɺ(} HLAlff.AVAUATL% UUHS@)HH)UH{8Lk(HCHCLc HU111HCxHCUHL HǃJǃ 1ɺHL=L=HH hHDyDAAAuUHcC0HZ>HIDŸH!H@(HHC8HLULHHtL`HX[]A\A]A^Ð1ɺ0HL%1ɺHLAV1ɺ HLA;1ɺ(HLAlff.AVAUATL% UUHSP'HHFUH{8Ls(HCHCLc HĤU111HCxHUHLHǃRǃ1ɺHL<L<HH x@HDyDAAAuTHcC0Hi>HIDƸH!H@(HHC8HLULHHtL`HX[]A\A]A^1ɺ0HL*51ɺHLAW1ɺ HLA<1ɺ(HLAlff.AVAUATL%* UUHS`%HHcUH{8Lk(HCHCLc HU111HCxHUHL)HǃJǃ)1ɺHL:L:HH HDyDAAAuTHcC0Hy>HIDŸH!H@(HHC8HLULHHtL`HX[]A\A]A^1ɺ0 HL:E1ɺ HL%AW1ɺ HLA<1ɺ( HLAlff.AVAUATL%bUUHSp#HHTH{8Ls(HCHCLc HdU111HCxHUHL9HǃRǃ91ɺHL(8L'8HH HDyDAAAuTHcC0H>HIDƸH!H@(HHC8HLULHHtL`HX[]A\A]A^1ɺ0 HLJU1ɺ HL 5AW1ɺ HLA<1ɺ( HLAlff.AVAUATL%UUHS!HHTH{8Lk(HCHCLc HTU111HCxHUHLIHǃJǃI1ɺHL86.L76HH HDyDAAAuUHcC0H>HIDŸH!H@(HHC8HLULH'HtL`HX[]A\A]A^Ð1ɺ0HLZe1ɺHLEAV1ɺ HL A;1ɺ(HLAlff.AVAUATL%UUHSHHTH{8Ls(HCHCLc HU111HCxH3UHLYHǃRǃY1ɺHLH4>LG4HH @HDyDAAAuTHcC0H>HIDƸH!H@(HHC8HLULH6HtL`HX[]A\A]A^1ɺ0HLju1ɺHL*UAW1ɺ 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" $ 1  2  4  6  >  ?  @ H I Q R a b d q  r  t  v  ~    @ H I Q R a b d q  r  t  v  ~          @                ../src/intel/vulkan_hasvk/anv_batch_chain.c../src/intel/vulkan_hasvk/anv_bo_sync.cfailed to allocate virtual address for BO../src/intel/vulkan_hasvk/anv_allocator.csame host pointer imported two different waysThe same BO was imported with and without buffer device addressThe same BO was imported at two different addresses../src/intel/vulkan_hasvk/anv_utrace.cBatch offset=0x%x len=0x%x on queue 0 BO: addr=0x%016lx-0x%016lx size=0x%010lx handle=%05u name=%s ../src/intel/vulkan_hasvk/anv_cmd_buffer.cWARNING: INTEL_MEASURE cannot capture timings of commands in secondary command buffers with VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT set. PIPE_FORMAT_R64G64B64A64_FLOATPIPE_FORMAT_R32G32B32A32_FLOATPIPE_FORMAT_R32G32B32A32_UNORMPIPE_FORMAT_R32G32B32A32_USCALEDPIPE_FORMAT_R32G32B32A32_SNORMPIPE_FORMAT_R32G32B32A32_SSCALEDPIPE_FORMAT_R16G16B16A16_UNORMPIPE_FORMAT_R16G16B16A16_USCALEDPIPE_FORMAT_R16G16B16A16_SNORMPIPE_FORMAT_R16G16B16A16_SSCALEDPIPE_FORMAT_R32G32B32A32_FIXEDPIPE_FORMAT_R16G16B16A16_FLOATPIPE_FORMAT_R10G10B10A2_USCALEDPIPE_FORMAT_R10G10B10A2_SSCALEDPIPE_FORMAT_B10G10R10A2_USCALEDPIPE_FORMAT_B10G10R10A2_SSCALEDPIPE_FORMAT_Z32_FLOAT_S8X24_UINTPIPE_FORMAT_R10G10B10X2_USCALEDPIPE_FORMAT_R10SG10SB10SA2U_NORMPIPE_FORMAT_Y8_U8_V8_422_UNORMPIPE_FORMAT_Y8_U8_V8_444_UNORMPIPE_FORMAT_Y16_U16_V16_420_UNORMPIPE_FORMAT_Y16_U16_V16_422_UNORMPIPE_FORMAT_Y16_U16V16_422_UNORMPIPE_FORMAT_Y16_U16_V16_444_UNORMPIPE_FORMAT_R16G16B16X16_UNORMPIPE_FORMAT_R16G16B16X16_SNORMPIPE_FORMAT_R16G16B16X16_FLOATPIPE_FORMAT_R32G32B32X32_FLOATPIPE_FORMAT_ATC_RGBA_INTERPOLATEDPIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8PIPE_FORMAT_R8_G8_B8_420_UNORMPIPE_FORMAT_R8_B8_G8_420_UNORMPIPE_FORMAT_G8_B8_R8_420_UNORMmmap failed: %mbo-synchost-ptrblock poolstate tablepc: add +tex_inval before UpdateBufferANV_USERSPACE_RELOCSBatch on queue %d i915-perf config failed: %sexecbuf2 failed: %msync wait failedvk_sync_signal failedanv_gem_execbuffer failed: %manv_device_wait failed: %mbefore copy_to_shadow+rt_flush after copy_to_shadowafter clear DS+depth_flush before clear DS+depth_stall before clear hizafter clear hizbefore fast clear mcs+state_inval before blorp clear color edit+pss_stall after fast clear mcsbefore fast clear ccsafter fast clear ccsPIPE_FORMAT_NONEnonePIPE_FORMAT_R64_UINTr64_uintPIPE_FORMAT_R64G64_UINTr64g64_uintPIPE_FORMAT_R64G64B64_UINTr64g64b64_uintPIPE_FORMAT_R64G64B64A64_UINTr64g64b64a64_uintPIPE_FORMAT_R64_SINTr64_sintPIPE_FORMAT_R64G64_SINTr64g64_sintPIPE_FORMAT_R64G64B64_SINTr64g64b64_sintPIPE_FORMAT_R64G64B64A64_SINTr64g64b64a64_sintPIPE_FORMAT_R64_FLOATr64_floatPIPE_FORMAT_R64G64_FLOATr64g64_floatPIPE_FORMAT_R64G64B64_FLOATr64g64b64_floatr64g64b64a64_floatPIPE_FORMAT_R32_FLOATr32_floatPIPE_FORMAT_R32G32_FLOATr32g32_floatPIPE_FORMAT_R32G32B32_FLOATr32g32b32_floatr32g32b32a32_floatPIPE_FORMAT_R32_UNORMr32_unormPIPE_FORMAT_R32G32_UNORMr32g32_unormPIPE_FORMAT_R32G32B32_UNORMr32g32b32_unormr32g32b32a32_unormPIPE_FORMAT_R32_USCALEDr32_uscaledPIPE_FORMAT_R32G32_USCALEDr32g32_uscaledPIPE_FORMAT_R32G32B32_USCALEDr32g32b32_uscaledr32g32b32a32_uscaledPIPE_FORMAT_R32_SNORMr32_snormPIPE_FORMAT_R32G32_SNORMr32g32_snormPIPE_FORMAT_R32G32B32_SNORMr32g32b32_snormr32g32b32a32_snormPIPE_FORMAT_R32_SSCALEDr32_sscaledPIPE_FORMAT_R32G32_SSCALEDr32g32_sscaledPIPE_FORMAT_R32G32B32_SSCALEDr32g32b32_sscaledr32g32b32a32_sscaledPIPE_FORMAT_R16_UNORMPIPE_FORMAT_R16G16_UNORMr16g16_unormPIPE_FORMAT_R16G16B16_UNORMr16g16b16_unormr16g16b16a16_unormPIPE_FORMAT_R16_USCALEDr16_uscaledPIPE_FORMAT_R16G16_USCALEDr16g16_uscaledPIPE_FORMAT_R16G16B16_USCALEDr16g16b16_uscaledr16g16b16a16_uscaledPIPE_FORMAT_R16_SNORMPIPE_FORMAT_R16G16_SNORMr16g16_snormPIPE_FORMAT_R16G16B16_SNORMr16g16b16_snormr16g16b16a16_snormPIPE_FORMAT_R16_SSCALEDr16_sscaledPIPE_FORMAT_R16G16_SSCALEDr16g16_sscaledPIPE_FORMAT_R16G16B16_SSCALEDr16g16b16_sscaledr16g16b16a16_sscaledPIPE_FORMAT_R8_UNORMPIPE_FORMAT_R8G8_UNORMPIPE_FORMAT_R8G8B8_UNORMPIPE_FORMAT_B8G8R8_UNORMPIPE_FORMAT_R8G8B8A8_UNORMr8g8b8a8_unormPIPE_FORMAT_B8G8R8A8_UNORMb8g8r8a8_unormPIPE_FORMAT_R8_USCALEDPIPE_FORMAT_R8G8_USCALEDr8g8_uscaledPIPE_FORMAT_R8G8B8_USCALEDr8g8b8_uscaledPIPE_FORMAT_B8G8R8_USCALEDPIPE_FORMAT_R8G8B8A8_USCALEDr8g8b8a8_uscaledPIPE_FORMAT_B8G8R8A8_USCALEDb8g8r8a8_uscaledPIPE_FORMAT_A8B8G8R8_USCALEDa8b8g8r8_uscaledPIPE_FORMAT_R8_SNORMPIPE_FORMAT_R8G8_SNORMr8g8_snormPIPE_FORMAT_R8G8B8_SNORMPIPE_FORMAT_B8G8R8_SNORMPIPE_FORMAT_R8G8B8A8_SNORMr8g8b8a8_snormPIPE_FORMAT_B8G8R8A8_SNORMb8g8r8a8_snormPIPE_FORMAT_R8_SSCALEDPIPE_FORMAT_R8G8_SSCALEDr8g8_sscaledPIPE_FORMAT_R8G8B8_SSCALEDr8g8b8_sscaledPIPE_FORMAT_B8G8R8_SSCALEDPIPE_FORMAT_R8G8B8A8_SSCALEDr8g8b8a8_sscaledPIPE_FORMAT_B8G8R8A8_SSCALEDb8g8r8a8_sscaledPIPE_FORMAT_A8B8G8R8_SSCALEDa8b8g8r8_sscaledPIPE_FORMAT_A8R8G8B8_UNORMa8r8g8b8_unormPIPE_FORMAT_R32_FIXEDr32_fixedPIPE_FORMAT_R32G32_FIXEDr32g32_fixedPIPE_FORMAT_R32G32B32_FIXEDr32g32b32_fixedr32g32b32a32_fixedPIPE_FORMAT_R16_FLOATr16_floatPIPE_FORMAT_R16G16_FLOATr16g16_floatPIPE_FORMAT_R16G16B16_FLOATr16g16b16_floatr16g16b16a16_floatPIPE_FORMAT_R8_UINTPIPE_FORMAT_R8G8_UINTr8g8_uintPIPE_FORMAT_R8G8B8_UINTPIPE_FORMAT_B8G8R8_UINTPIPE_FORMAT_R8G8B8A8_UINTr8g8b8a8_uintPIPE_FORMAT_B8G8R8A8_UINTb8g8r8a8_uintPIPE_FORMAT_R8_SINTPIPE_FORMAT_R8G8_SINTr8g8_sintPIPE_FORMAT_R8G8B8_SINTPIPE_FORMAT_B8G8R8_SINTPIPE_FORMAT_R8G8B8A8_SINTr8g8b8a8_sintPIPE_FORMAT_B8G8R8A8_SINTb8g8r8a8_sintPIPE_FORMAT_R16_UINTr16_uintPIPE_FORMAT_R16G16_UINTr16g16_uintPIPE_FORMAT_R16G16B16_UINTr16g16b16_uintPIPE_FORMAT_R16G16B16A16_UINTr16g16b16a16_uintPIPE_FORMAT_R16_SINTPIPE_FORMAT_R16G16_SINTr16g16_sintPIPE_FORMAT_R16G16B16_SINTr16g16b16_sintPIPE_FORMAT_R16G16B16A16_SINTr16g16b16a16_sintPIPE_FORMAT_R32_UINTr32_uintPIPE_FORMAT_R32G32_UINTr32g32_uintPIPE_FORMAT_R32G32B32_UINTr32g32b32_uintPIPE_FORMAT_R32G32B32A32_UINTr32g32b32a32_uintPIPE_FORMAT_R32_SINTr32_sintPIPE_FORMAT_R32G32_SINTr32g32_sintPIPE_FORMAT_R32G32B32_SINTr32g32b32_sintPIPE_FORMAT_R32G32B32A32_SINTr32g32b32a32_sintPIPE_FORMAT_R10G10B10A2_UNORMr10g10b10a2_unormPIPE_FORMAT_R10G10B10A2_SNORMr10g10b10a2_snormr10g10b10a2_uscaledr10g10b10a2_sscaledPIPE_FORMAT_B10G10R10A2_UNORMb10g10r10a2_unormPIPE_FORMAT_B10G10R10A2_SNORMb10g10r10a2_snormb10g10r10a2_uscaledb10g10r10a2_sscaledPIPE_FORMAT_R11G11B10_FLOATr11g11b10_floatPIPE_FORMAT_R10G10B10A2_UINTr10g10b10a2_uintPIPE_FORMAT_R10G10B10A2_SINTr10g10b10a2_sintPIPE_FORMAT_B10G10R10A2_UINTb10g10r10a2_uintPIPE_FORMAT_B10G10R10A2_SINTb10g10r10a2_sintPIPE_FORMAT_B8G8R8X8_UNORMb8g8r8x8_unormPIPE_FORMAT_X8B8G8R8_UNORMx8b8g8r8_unormPIPE_FORMAT_X8R8G8B8_UNORMx8r8g8b8_unormPIPE_FORMAT_B5G5R5A1_UNORMb5g5r5a1_unormPIPE_FORMAT_R4G4B4A4_UNORMr4g4b4a4_unormPIPE_FORMAT_B4G4R4A4_UNORMb4g4r4a4_unormPIPE_FORMAT_R5G6B5_UNORMr5g6b5_unormPIPE_FORMAT_B5G6R5_UNORMb5g6r5_unormPIPE_FORMAT_L8_UNORMl8_unormPIPE_FORMAT_A8_UNORMPIPE_FORMAT_I8_UNORMi8_unormPIPE_FORMAT_L8A8_UNORMl8a8_unormPIPE_FORMAT_L16_UNORMl16_unormPIPE_FORMAT_UYVYuyvyPIPE_FORMAT_VYUYvyuyPIPE_FORMAT_YUYVyuyvPIPE_FORMAT_YVYUyvyuPIPE_FORMAT_Z16_UNORMz16_unormPIPE_FORMAT_Z16_UNORM_S8_UINTz16_unorm_s8_uintPIPE_FORMAT_Z32_UNORMz32_unormPIPE_FORMAT_Z32_FLOATz32_floatPIPE_FORMAT_Z24_UNORM_S8_UINTz24_unorm_s8_uintPIPE_FORMAT_S8_UINT_Z24_UNORMs8_uint_z24_unormPIPE_FORMAT_Z24X8_UNORMz24x8_unormPIPE_FORMAT_X8Z24_UNORMx8z24_unormPIPE_FORMAT_S8_UINTPIPE_FORMAT_L8_SRGBl8_srgbPIPE_FORMAT_R8_SRGBPIPE_FORMAT_L8A8_SRGBl8a8_srgbPIPE_FORMAT_R8G8_SRGBr8g8_srgbPIPE_FORMAT_R8G8B8_SRGBPIPE_FORMAT_B8G8R8_SRGBPIPE_FORMAT_A8B8G8R8_SRGBa8b8g8r8_srgbPIPE_FORMAT_X8B8G8R8_SRGBx8b8g8r8_srgbPIPE_FORMAT_B8G8R8A8_SRGBb8g8r8a8_srgbPIPE_FORMAT_B8G8R8X8_SRGBb8g8r8x8_srgbPIPE_FORMAT_A8R8G8B8_SRGBa8r8g8b8_srgbPIPE_FORMAT_X8R8G8B8_SRGBx8r8g8b8_srgbPIPE_FORMAT_R8G8B8A8_SRGBr8g8b8a8_srgbPIPE_FORMAT_DXT1_RGBdxt1_rgbPIPE_FORMAT_DXT1_RGBAdxt1_rgbaPIPE_FORMAT_DXT3_RGBAdxt3_rgbaPIPE_FORMAT_DXT5_RGBAdxt5_rgbaPIPE_FORMAT_DXT1_SRGBdxt1_srgbPIPE_FORMAT_DXT1_SRGBAdxt1_srgbaPIPE_FORMAT_DXT3_SRGBAdxt3_srgbaPIPE_FORMAT_DXT5_SRGBAdxt5_srgbaPIPE_FORMAT_RGTC1_UNORMrgtc1_unormPIPE_FORMAT_RGTC1_SNORMrgtc1_snormPIPE_FORMAT_RGTC2_UNORMrgtc2_unormPIPE_FORMAT_RGTC2_SNORMrgtc2_snormPIPE_FORMAT_R8G8_B8G8_UNORMr8g8_b8g8_unormPIPE_FORMAT_G8R8_G8B8_UNORMg8r8_g8b8_unormPIPE_FORMAT_R8SG8SB8UX8U_NORMr8sg8sb8ux8u_normPIPE_FORMAT_R5SG5SB6U_NORMr5sg5sb6u_normPIPE_FORMAT_A8B8G8R8_UNORMa8b8g8r8_unormPIPE_FORMAT_B5G5R5X1_UNORMb5g5r5x1_unormPIPE_FORMAT_R9G9B9E5_FLOATr9g9b9e5_floatz32_float_s8x24_uintPIPE_FORMAT_R1_UNORMr1_unormr10g10b10x2_uscaledPIPE_FORMAT_R10G10B10X2_SNORMr10g10b10x2_snormPIPE_FORMAT_L4A4_UNORMl4a4_unormPIPE_FORMAT_A2R10G10B10_UNORMa2r10g10b10_unormPIPE_FORMAT_A2B10G10R10_UNORMa2b10g10r10_unormr10sg10sb10sa2u_normPIPE_FORMAT_R8G8Bx_SNORMr8g8bx_snormPIPE_FORMAT_R8G8B8X8_UNORMr8g8b8x8_unormPIPE_FORMAT_B4G4R4X4_UNORMb4g4r4x4_unormPIPE_FORMAT_X24S8_UINTx24s8_uintPIPE_FORMAT_S8X24_UINTPIPE_FORMAT_X32_S8X24_UINTx32_s8x24_uintPIPE_FORMAT_R3G3B2_UNORMr3g3b2_unormPIPE_FORMAT_B2G3R3_UNORMb2g3r3_unormPIPE_FORMAT_L16A16_UNORMl16a16_unormPIPE_FORMAT_A16_UNORMPIPE_FORMAT_I16_UNORMi16_unormPIPE_FORMAT_LATC1_UNORMlatc1_unormPIPE_FORMAT_LATC1_SNORMlatc1_snormPIPE_FORMAT_LATC2_UNORMlatc2_unormPIPE_FORMAT_LATC2_SNORMlatc2_snormPIPE_FORMAT_A8_SNORMPIPE_FORMAT_L8_SNORMl8_snormPIPE_FORMAT_L8A8_SNORMl8a8_snormPIPE_FORMAT_I8_SNORMi8_snormPIPE_FORMAT_A16_SNORMPIPE_FORMAT_L16_SNORMl16_snormPIPE_FORMAT_L16A16_SNORMl16a16_snormPIPE_FORMAT_I16_SNORMi16_snormPIPE_FORMAT_A16_FLOATPIPE_FORMAT_L16_FLOATl16_floatPIPE_FORMAT_L16A16_FLOATl16a16_floatPIPE_FORMAT_I16_FLOATi16_floatPIPE_FORMAT_A32_FLOATPIPE_FORMAT_L32_FLOATl32_floatPIPE_FORMAT_L32A32_FLOATl32a32_floatPIPE_FORMAT_I32_FLOATi32_floatPIPE_FORMAT_YV12yv12PIPE_FORMAT_YV16yv16PIPE_FORMAT_IYUViyuvPIPE_FORMAT_NV12nv12PIPE_FORMAT_NV21nv21PIPE_FORMAT_Y8_400_UNORMy8_400_unormy8_u8_v8_422_unormPIPE_FORMAT_Y8_U8V8_422_UNORMy8_u8v8_422_unormy8_u8_v8_444_unormy16_u16_v16_420_unormy16_u16_v16_422_unormy16_u16v16_422_unormy16_u16_v16_444_unormPIPE_FORMAT_A4R4_UNORMa4r4_unormPIPE_FORMAT_R4A4_UNORMPIPE_FORMAT_R8A8_UNORMPIPE_FORMAT_A8R8_UNORMa8r8_unormPIPE_FORMAT_A8_UINTPIPE_FORMAT_I8_UINTi8_uintPIPE_FORMAT_L8_UINTl8_uintPIPE_FORMAT_L8A8_UINTl8a8_uintPIPE_FORMAT_A8_SINTPIPE_FORMAT_I8_SINTi8_sintPIPE_FORMAT_L8_SINTl8_sintPIPE_FORMAT_L8A8_SINTl8a8_sintPIPE_FORMAT_A16_UINTPIPE_FORMAT_I16_UINTi16_uintPIPE_FORMAT_L16_UINTl16_uintPIPE_FORMAT_L16A16_UINTl16a16_uintPIPE_FORMAT_A16_SINTPIPE_FORMAT_I16_SINTi16_sintPIPE_FORMAT_L16_SINTl16_sintPIPE_FORMAT_L16A16_SINTl16a16_sintPIPE_FORMAT_A32_UINTPIPE_FORMAT_I32_UINTi32_uintPIPE_FORMAT_L32_UINTl32_uintPIPE_FORMAT_L32A32_UINTl32a32_uintPIPE_FORMAT_A32_SINTPIPE_FORMAT_I32_SINTi32_sintPIPE_FORMAT_L32_SINTl32_sintPIPE_FORMAT_L32A32_SINTl32a32_sintPIPE_FORMAT_A8R8G8B8_UINTa8r8g8b8_uintPIPE_FORMAT_A8B8G8R8_UINTa8b8g8r8_uintPIPE_FORMAT_A2R10G10B10_UINTa2r10g10b10_uintPIPE_FORMAT_A2B10G10R10_UINTa2b10g10r10_uintPIPE_FORMAT_R5G6B5_UINTr5g6b5_uintPIPE_FORMAT_B5G6R5_UINTb5g6r5_uintPIPE_FORMAT_R5G5B5A1_UINTr5g5b5a1_uintPIPE_FORMAT_B5G5R5A1_UINTb5g5r5a1_uintPIPE_FORMAT_A1R5G5B5_UINTa1r5g5b5_uintPIPE_FORMAT_A1B5G5R5_UINTa1b5g5r5_uintPIPE_FORMAT_R4G4B4A4_UINTr4g4b4a4_uintPIPE_FORMAT_B4G4R4A4_UINTb4g4r4a4_uintPIPE_FORMAT_A4R4G4B4_UINTa4r4g4b4_uintPIPE_FORMAT_A4B4G4R4_UINTa4b4g4r4_uintPIPE_FORMAT_R3G3B2_UINTr3g3b2_uintPIPE_FORMAT_B2G3R3_UINTb2g3r3_uintPIPE_FORMAT_ETC1_RGB8etc1_rgb8PIPE_FORMAT_R8G8_R8B8_UNORMr8g8_r8b8_unormPIPE_FORMAT_R8B8_R8G8_UNORMr8b8_r8g8_unormPIPE_FORMAT_G8R8_B8R8_UNORMg8r8_b8r8_unormPIPE_FORMAT_B8R8_G8R8_UNORMb8r8_g8r8_unormPIPE_FORMAT_G8B8_G8R8_UNORMg8b8_g8r8_unormPIPE_FORMAT_B8G8_R8G8_UNORMb8g8_r8g8_unormPIPE_FORMAT_R8G8B8X8_SNORMr8g8b8x8_snormPIPE_FORMAT_R8G8B8X8_SRGBr8g8b8x8_srgbPIPE_FORMAT_R8G8B8X8_UINTr8g8b8x8_uintPIPE_FORMAT_R8G8B8X8_SINTr8g8b8x8_sintPIPE_FORMAT_B10G10R10X2_UNORMb10g10r10x2_unormr16g16b16x16_unormr16g16b16x16_snormr16g16b16x16_floatPIPE_FORMAT_R16G16B16X16_UINTr16g16b16x16_uintPIPE_FORMAT_R16G16B16X16_SINTr16g16b16x16_sintr32g32b32x32_floatPIPE_FORMAT_R32G32B32X32_UINTr32g32b32x32_uintPIPE_FORMAT_R32G32B32X32_SINTr32g32b32x32_sintPIPE_FORMAT_R8A8_SNORMPIPE_FORMAT_R16A16_UNORMr16a16_unormPIPE_FORMAT_R16A16_SNORMr16a16_snormPIPE_FORMAT_R16A16_FLOATr16a16_floatPIPE_FORMAT_R32A32_FLOATr32a32_floatPIPE_FORMAT_R8A8_UINTPIPE_FORMAT_R8A8_SINTPIPE_FORMAT_R16A16_UINTr16a16_uintPIPE_FORMAT_R16A16_SINTr16a16_sintPIPE_FORMAT_R32A32_UINTr32a32_uintPIPE_FORMAT_R32A32_SINTr32a32_sintPIPE_FORMAT_B5G6R5_SRGBb5g6r5_srgbPIPE_FORMAT_BPTC_RGBA_UNORMbptc_rgba_unormPIPE_FORMAT_BPTC_SRGBAbptc_srgbaPIPE_FORMAT_BPTC_RGB_FLOATbptc_rgb_floatPIPE_FORMAT_BPTC_RGB_UFLOATbptc_rgb_ufloatPIPE_FORMAT_G8R8_UNORMPIPE_FORMAT_G8R8_SNORMPIPE_FORMAT_G16R16_UNORMg16r16_unormPIPE_FORMAT_G16R16_SNORMg16r16_snormPIPE_FORMAT_A8B8G8R8_SNORMa8b8g8r8_snormPIPE_FORMAT_X8B8G8R8_SNORMx8b8g8r8_snormPIPE_FORMAT_ETC2_RGB8etc2_rgb8PIPE_FORMAT_ETC2_SRGB8etc2_srgb8PIPE_FORMAT_ETC2_RGB8A1etc2_rgb8a1PIPE_FORMAT_ETC2_SRGB8A1etc2_srgb8a1PIPE_FORMAT_ETC2_RGBA8etc2_rgba8PIPE_FORMAT_ETC2_SRGBA8etc2_srgba8PIPE_FORMAT_ETC2_R11_UNORMetc2_r11_unormPIPE_FORMAT_ETC2_R11_SNORMetc2_r11_snormPIPE_FORMAT_ETC2_RG11_UNORMetc2_rg11_unormPIPE_FORMAT_ETC2_RG11_SNORMetc2_rg11_snormPIPE_FORMAT_ASTC_4x4astc_4x4PIPE_FORMAT_ASTC_5x4astc_5x4PIPE_FORMAT_ASTC_5x5astc_5x5PIPE_FORMAT_ASTC_6x5astc_6x5PIPE_FORMAT_ASTC_6x6astc_6x6PIPE_FORMAT_ASTC_8x5astc_8x5PIPE_FORMAT_ASTC_8x6astc_8x6PIPE_FORMAT_ASTC_8x8astc_8x8PIPE_FORMAT_ASTC_10x5astc_10x5PIPE_FORMAT_ASTC_10x6astc_10x6PIPE_FORMAT_ASTC_10x8astc_10x8PIPE_FORMAT_ASTC_10x10astc_10x10PIPE_FORMAT_ASTC_12x10astc_12x10PIPE_FORMAT_ASTC_12x12astc_12x12PIPE_FORMAT_ASTC_4x4_SRGBastc_4x4_srgbPIPE_FORMAT_ASTC_5x4_SRGBastc_5x4_srgbPIPE_FORMAT_ASTC_5x5_SRGBastc_5x5_srgbPIPE_FORMAT_ASTC_6x5_SRGBastc_6x5_srgbPIPE_FORMAT_ASTC_6x6_SRGBastc_6x6_srgbPIPE_FORMAT_ASTC_8x5_SRGBastc_8x5_srgbPIPE_FORMAT_ASTC_8x6_SRGBastc_8x6_srgbPIPE_FORMAT_ASTC_8x8_SRGBastc_8x8_srgbPIPE_FORMAT_ASTC_10x5_SRGBastc_10x5_srgbPIPE_FORMAT_ASTC_10x6_SRGBastc_10x6_srgbPIPE_FORMAT_ASTC_10x8_SRGBastc_10x8_srgbPIPE_FORMAT_ASTC_10x10_SRGBastc_10x10_srgbPIPE_FORMAT_ASTC_12x10_SRGBastc_12x10_srgbPIPE_FORMAT_ASTC_12x12_SRGBastc_12x12_srgbPIPE_FORMAT_ASTC_3x3x3astc_3x3x3PIPE_FORMAT_ASTC_4x3x3astc_4x3x3PIPE_FORMAT_ASTC_4x4x3astc_4x4x3PIPE_FORMAT_ASTC_4x4x4astc_4x4x4PIPE_FORMAT_ASTC_5x4x4astc_5x4x4PIPE_FORMAT_ASTC_5x5x4astc_5x5x4PIPE_FORMAT_ASTC_5x5x5astc_5x5x5PIPE_FORMAT_ASTC_6x5x5astc_6x5x5PIPE_FORMAT_ASTC_6x6x5astc_6x6x5PIPE_FORMAT_ASTC_6x6x6astc_6x6x6PIPE_FORMAT_ASTC_3x3x3_SRGBastc_3x3x3_srgbPIPE_FORMAT_ASTC_4x3x3_SRGBastc_4x3x3_srgbPIPE_FORMAT_ASTC_4x4x3_SRGBastc_4x4x3_srgbPIPE_FORMAT_ASTC_4x4x4_SRGBastc_4x4x4_srgbPIPE_FORMAT_ASTC_5x4x4_SRGBastc_5x4x4_srgbPIPE_FORMAT_ASTC_5x5x4_SRGBastc_5x5x4_srgbPIPE_FORMAT_ASTC_5x5x5_SRGBastc_5x5x5_srgbPIPE_FORMAT_ASTC_6x5x5_SRGBastc_6x5x5_srgbPIPE_FORMAT_ASTC_6x6x5_SRGBastc_6x6x5_srgbPIPE_FORMAT_ASTC_6x6x6_SRGBastc_6x6x6_srgbPIPE_FORMAT_FXT1_RGBfxt1_rgbPIPE_FORMAT_FXT1_RGBAfxt1_rgbaPIPE_FORMAT_P010p010PIPE_FORMAT_P012p012PIPE_FORMAT_P016p016PIPE_FORMAT_P030p030PIPE_FORMAT_Y210y210PIPE_FORMAT_Y212y212PIPE_FORMAT_Y216y216PIPE_FORMAT_Y410y410PIPE_FORMAT_Y412y412PIPE_FORMAT_Y416y416PIPE_FORMAT_R10G10B10X2_UNORMr10g10b10x2_unormPIPE_FORMAT_A1R5G5B5_UNORMa1r5g5b5_unormPIPE_FORMAT_A1B5G5R5_UNORMa1b5g5r5_unormPIPE_FORMAT_X1B5G5R5_UNORMx1b5g5r5_unormPIPE_FORMAT_R5G5B5A1_UNORMr5g5b5a1_unormPIPE_FORMAT_A4R4G4B4_UNORMa4r4g4b4_unormPIPE_FORMAT_A4B4G4R4_UNORMa4b4g4r4_unormPIPE_FORMAT_G8R8_SINTPIPE_FORMAT_A8B8G8R8_SINTa8b8g8r8_sintPIPE_FORMAT_X8B8G8R8_SINTx8b8g8r8_sintPIPE_FORMAT_ATC_RGBatc_rgbPIPE_FORMAT_ATC_RGBA_EXPLICITatc_rgba_explicitatc_rgba_interpolatedz24_unorm_s8_uint_as_r8g8b8a8PIPE_FORMAT_AYUVayuvPIPE_FORMAT_XYUVxyuvPIPE_FORMAT_R8_G8B8_420_UNORMr8_g8b8_420_unormPIPE_FORMAT_R8_B8G8_420_UNORMr8_b8g8_420_unormPIPE_FORMAT_G8_B8R8_420_UNORMg8_b8r8_420_unormr8_g8_b8_420_unormr8_b8_g8_420_unormg8_b8_r8_420_unormPIPE_FORMAT_R8_G8_B8_UNORMr8_g8_b8_unormPIPE_FORMAT_Y8_UNORMy8_unormPIPE_FORMAT_B8G8R8X8_SNORMb8g8r8x8_snormPIPE_FORMAT_B8G8R8X8_UINTb8g8r8x8_uintPIPE_FORMAT_B8G8R8X8_SINTb8g8r8x8_sintPIPE_FORMAT_A8R8G8B8_SNORMa8r8g8b8_snormPIPE_FORMAT_A8R8G8B8_SINTa8r8g8b8_sintPIPE_FORMAT_X8R8G8B8_SNORMx8r8g8b8_snormPIPE_FORMAT_X8R8G8B8_SINTx8r8g8b8_sintPIPE_FORMAT_R5G5B5X1_UNORMr5g5b5x1_unormPIPE_FORMAT_X1R5G5B5_UNORMx1r5g5b5_unormPIPE_FORMAT_R4G4B4X4_UNORMr4g4b4x4_unormPIPE_FORMAT_B10G10R10X2_SNORMb10g10r10x2_snormPIPE_FORMAT_R5G6B5_SRGBr5g6b5_srgbPIPE_FORMAT_R10G10B10X2_SINTr10g10b10x2_sintPIPE_FORMAT_B10G10R10X2_SINTb10g10r10x2_sintPIPE_FORMAT_G16R16_SINTg16r16_sint??Tv../src/intel/vulkan_hasvk/anv_descriptor_set.c../src/intel/vulkan_hasvk/anv_device.cbuild-id too short. It needs to be a SHAMESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZdescriptorsFailed to find build-id24.1.2idTechanv_%04xMESA_DISK_CACHE_SINGLE_FILEMESA_DISK_CACHE_DATABASEUnable to open device %s: %mINTEL_STUB_GPU_JSONFailed to query drm device.MESAIntel(R) 965Q (BW)Intel(R) 946GZ (BW)Intel(R) 965GM (CL)Intel(R) 965GME/GLE (CL)Intel(R) Q45/Q43 (ELK)Intel(R) G45/G43 (ELK)Intel(R) G41 (ELK)Intel(R) HD Graphics (BXT 2)Intel(R) UHD Graphics (EHL)Intel(R) UHD Graphics (JSL)Intel(R) Graphics (RKL GT0.5)Intel(R) Graphics (TGL GT2)Intel(R) Graphics (SG1)Intel(R) Graphics (DG2)Intel(R) Graphics (MTL)INTEL_NO_HWi915Unknown kernel mode driverXXXMESA-INTELkernel missing gem waitkernel missing execbuf2kernel missing wc mmapkernel missing softpinANV_QUEUE_THREAD_DISABLEANV_ALWAYS_BINDLESSalways_flush_cacheINTEL_PRECISE_TRIGillegalmovismovasrcmpcmpnf32to16f16to32bfrevbfi1bfi2jmpibrdbrcelseendifdocasewhilecontcallamsavecallmrestretpushforkgotopopsendsendcmathavgfrcrndurnddrnderndzmacmachlzdfbhfblcbitaddcsubbsad2sada2dp4dp3dp2plnmadmnenopUnable to open device %s: out of memoryMobile Intel® GM45 Express Chipset (CTG)Intel(R) Integrated Graphics Device (ELK)Intel(R) HD Graphics (IVB GT1)Intel(R) HD Graphics P4000 (IVB GT2)Intel(R) HD Graphics P4600/P4700 (HSW GT2)Intel(R) HD Graphics 5000 (HSW GT3)Intel(R) HD Graphics 4200 (HSW GT2)Intel(R) Iris(R) Graphics 5100 (HSW GT3)Intel(R) Iris(R) Pro Graphics 5200 (HSW GT3)Intel(R) Iris(R) Pro Graphics P5200 (HSW GT3)Intel(R) HD Graphics XXX (BSW)Intel(R) HD Graphics 5600 (BDW GT2)Intel(R) HD Graphics 5500 (BDW GT2)Intel(R) HD Graphics P5700 (BDW GT2)Intel(R) HD Graphics 5300 (BDW GT2)Intel(R) Iris(R) Pro Graphics 6200 (BDW GT3)Intel(R) HD Graphics 6000 (BDW GT3)Intel(R) Iris(R) Pro Graphics P6300 (BDW GT3)Intel(R) Iris(R) Graphics 6100 (BDW GT3)Intel(R) HD Graphics (SKL GT2)Intel(R) HD Graphics P530 (SKL GT2)Intel(R) HD Graphics 515 (SKL GT2)Intel(R) HD Graphics 535 (SKL GT3)Intel(R) Iris(R) Graphics 540 (SKL GT3)Intel(R) Iris(R) Graphics 550 (SKL GT3)Intel(R) HD Graphics (SKL GT4)Intel(R) Iris(R) Graphics 555 (SKL GT3)Intel(R) Iris(R) Graphics P555 (SKL GT3)Intel(R) HD Graphics 505 (APL 3)Intel(R) HD Graphics 500 (APL 2)Intel(R) UHD Graphics 605 (GLK 3)Intel(R) UHD Graphics 600 (GLK 2)Intel(R) UHD Graphics 620 (KBL GT2)Intel(R) HD Graphics 620 (KBL GT2)Intel(R) HD Graphics 615 (KBL GT2)Intel(R) HD Graphics 620 (KBL GT2F)Intel(R) HD Graphics 635 (KBL GT3)Intel(R) Iris(R) Plus Graphics 640 (Kaby Lake GT3e) (KBL GT3)Intel(R) Iris(R) Plus Graphics 650 (Kaby Lake GT3e) (KBL GT3)Intel(R) HD Graphics (KBL GT4)Intel(R) UHD Graphics 615 (AML-KBL)Intel(R) UHD Graphics 617 (AML-KBL)Intel(R) UHD Graphics (AML-CFL)Intel(R) UHD Graphics 620 (CFL GT2)Intel(R) Iris(R) Plus Graphics 645 (CFL GT3)Intel(R) HD Graphics (CFL GT3)Intel(R) UHD Graphics 610 (WHL GT1)Intel(R) UHD Graphics (WHL GT1)Intel(R) UHD Graphics 620 (WHL GT2)Intel(R) UHD Graphics (WHL GT2)Intel(R) UHD Graphics (WHL GT3)Intel(R) HD Graphics (ICL GT2)Intel(R) HD Graphics (ICL GT0.5)Intel(R) UHD Graphics (ADL-S GT0.5)Intel(R) UHD Graphics 710 (ADL-S GT1)Intel(R) Arc(tm) A770M Graphics (DG2)Intel(R) Arc(tm) A730M Graphics (DG2)Intel(R) Arc(tm) A550M Graphics (DG2)Intel(R) Arc(tm) A370M Graphics (DG2)Intel(R) Arc(tm) A350M Graphics (DG2)Intel(R) Arc(tm) A570M Graphics (DG2)Intel(R) Arc(tm) A530M Graphics (DG2)Intel(R) Arc(tm) A770 Graphics (DG2)Intel(R) Arc(tm) A750 Graphics (DG2)Intel(R) Arc(tm) A580 Graphics (DG2)Intel(R) Arc(tm) A380 Graphics (DG2)Intel(R) Arc(tm) A310 Graphics (DG2)Intel(R) Arc(tm) Pro A30M Graphics (DG2)Intel(R) Arc(tm) Pro A40/A50 Graphics (DG2)Intel(R) Arc(tm) Pro A60M Graphics (DG2)Intel(R) Arc(tm) Pro A60 Graphics (DG2)Intel(R) Arc(tm) A380E Graphics (DG2)Intel(R) Arc(tm) A310E Graphics (DG2)Intel(R) Arc(tm) A370E Graphics (DG2)Intel(R) Arc(tm) A350E Graphics (DG2)Intel(R) Arc(tm) A750E Graphics (DG2)Intel(R) Arc(tm) A580E Graphics (DG2)Intel(R) Data Center GPU Flex 170 (ATS-M)Intel(R) Data Center GPU Flex 140 (ATS-M)Intel(R) Data Center GPU Flex 170V (ATS-M)Intel(R) Arc(tm) Graphics (MTL)Driver does not support the 0x%x PCI ID.Kernel 4.15 required to read the CS timestamp frequency.Kernel 4.1 required to properly query GPU properties.Could not get intel_device_info.Could not query local memory size.MESA_VK_IGNORE_CONFORMANCE_WARNINGHaswell Vulkan support is incompleteIvy Bridge Vulkan support is incompleteBay Trail Vulkan support is incompletefailed to get command parser versionkernel missing syncobj support%s:%d: The kernel reported a GTT size larger than 2 GiB but not support for 48-bit addressesANV_DISABLE_SECONDARY_CMD_BUFFER_CALLSSupport for this platform is experimental with Xe KMD, bug reports may be ignored.m酢ރӁ{PPPPPPPPywu 8 8}sPPPPPPPPP{qxmPPPPPPbWLA6+  :499:4v6+44444444444444|ӡ444:Q44444444444444446+ggd4gj ;hofd4daS_][bw20w20 蕡蕡蕡~ JR F+++PPPPPE"$$$#$%$$$$$$$$$d'$$$$$$$$$$$$$$$^ k@ >@@y?xءAxءxء@7lllN5l~ %luBFailed to read the TIMESTAMP register: %mAdapt the monitor sync to the application performance (when possible)Override the VkSurfaceCapabilitiesKHR::minImageCount (0 = no override)vk_x11_override_min_image_countForce the X11 WSI to create exactly the number of image specified by the application in VkSwapchainCreateInfoKHR::minImageCountWait for fences before submitting buffers to XwaylandAllow assuming full subgroups requirement even when it's not specified explicitly and set the given sizeIgnore sample mask out when having single sampled targetOverride intel_hasvk API versionEnable flushing GPU caches with each draw callForce vkGetPhysicalDeviceSurfaceFormatsKHR to return VK_FORMAT_B8G8R8A8_UNORM as the first formatvk_wsi_force_bgra8_unorm_firstForce VkSwapchainCreateInfoKHR::imageExtent to be VkSurfaceCapabilities2KHR::currentExtentvk_wsi_force_swapchain_to_current_extentForce the X11 WSI to never report VK_SUBOPTIMAL_KHRLimit trig input range to [-2p : 2p] to improve sin/cos calculation precision on IntelLower depth range for fixing misrendering issues due to z coordinate float point interpolation accuracyMESA_VK_TRACEMESA_VK_TRACE_FRAMEMESA_VK_TRACE_TRIGGER../src/util/xmlconfig.c%s: %d: out of memory. MESA_DEBUGsilentanv_assume_full_subgroupslimit_trig_input_rangelower_depth_range_rateno_16bithasvk_report_vk_1_3_versionget_reset_stats failed: %mimporteduserfailed to set BO tiling: %mOut of heap memoryMemory object not mappable.Memory object already mapped.trivial-batchrmvPerformanceadaptive_syncvk_x11_strict_image_countvk_xwayland_wait_readyDisable 16-bit instructionsDebuggingvk_x11_ignore_suboptimalImage QualityVK_KHR_android_surfaceVK_KHR_device_group_creationVK_KHR_displayVK_KHR_external_fence_capabilitiesVK_KHR_external_memory_capabilitiesVK_KHR_external_semaphore_capabilitiesVK_KHR_get_display_properties2VK_KHR_get_physical_device_properties2VK_KHR_get_surface_capabilities2VK_KHR_portability_enumerationVK_KHR_surfaceVK_KHR_surface_protected_capabilitiesVK_KHR_wayland_surfaceVK_KHR_win32_surfaceVK_KHR_xcb_surfaceVK_KHR_xlib_surfaceVK_EXT_acquire_drm_displayVK_EXT_acquire_xlib_displayVK_EXT_debug_report VK_EXT_debug_utilsVK_EXT_direct_mode_displayVK_EXT_directfb_surfaceVK_EXT_display_surface_counterVK_EXT_headless_surfaceVK_EXT_layer_settingsVK_EXT_metal_surfaceVK_EXT_surface_maintenance1VK_EXT_swapchain_colorspaceVK_EXT_validation_featuresVK_EXT_validation_flagsVK_FUCHSIA_imagepipe_surfaceVK_GGP_stream_descriptor_surfaceVK_GOOGLE_surfaceless_queryVK_LUNARG_direct_driver_loadingVK_MVK_ios_surfaceVK_MVK_macos_surfaceVK_NN_vi_surfaceVK_NV_external_memory_capabilitiesVK_QNX_screen_surfaceA@eACIntel open-sourcMESA-BLAKE3../src/vulkan/runtime/vk_device.cVkPhysicalDeviceFeatures2.featuresVkPhysicalDeviceDeviceGeneratedCommandsFeaturesNVsrc/vulkan/runtime/vk_physical_device_features.cVkPhysicalDeviceDeviceGeneratedCommandsComputeFeaturesNVdeviceGeneratedComputePipelinesdeviceGeneratedComputeCaptureReplayVkPhysicalDevicePrivateDataFeaturesVkPhysicalDeviceVariablePointersFeaturesVkPhysicalDeviceMultiviewFeaturesVkPhysicalDevicePresentIdFeaturesKHRVkPhysicalDevicePresentWaitFeaturesKHRVkPhysicalDevice16BitStorageFeaturesuniformAndStorageBuffer16BitAccessVkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesVkPhysicalDeviceSamplerYcbcrConversionFeaturesVkPhysicalDeviceProtectedMemoryFeaturesVkPhysicalDeviceBlendOperationAdvancedFeaturesEXTadvancedBlendCoherentOperationsVkPhysicalDeviceMultiDrawFeaturesEXTVkPhysicalDeviceInlineUniformBlockFeaturesdescriptorBindingInlineUniformBlockUpdateAfterBindVkPhysicalDeviceMaintenance4FeaturesVkPhysicalDeviceMaintenance5FeaturesKHRVkPhysicalDeviceMaintenance6FeaturesKHRVkPhysicalDeviceShaderDrawParametersFeaturesVkPhysicalDeviceShaderFloat16Int8FeaturesVkPhysicalDeviceHostQueryResetFeaturesVkPhysicalDeviceGlobalPriorityQueryFeaturesKHRVkPhysicalDeviceDeviceMemoryReportFeaturesEXTVkPhysicalDeviceDescriptorIndexingFeaturesshaderInputAttachmentArrayDynamicIndexingshaderUniformTexelBufferArrayDynamicIndexingshaderStorageTexelBufferArrayDynamicIndexingshaderUniformBufferArrayNonUniformIndexingshaderSampledImageArrayNonUniformIndexingshaderStorageBufferArrayNonUniformIndexingshaderStorageImageArrayNonUniformIndexingshaderInputAttachmentArrayNonUniformIndexingshaderUniformTexelBufferArrayNonUniformIndexingshaderStorageTexelBufferArrayNonUniformIndexingdescriptorBindingUniformBufferUpdateAfterBinddescriptorBindingSampledImageUpdateAfterBinddescriptorBindingStorageImageUpdateAfterBinddescriptorBindingStorageBufferUpdateAfterBinddescriptorBindingUniformTexelBufferUpdateAfterBinddescriptorBindingStorageTexelBufferUpdateAfterBinddescriptorBindingUpdateUnusedWhilePendingdescriptorBindingPartiallyBounddescriptorBindingVariableDescriptorCountVkPhysicalDeviceTimelineSemaphoreFeaturesVkPhysicalDevice8BitStorageFeaturesuniformAndStorageBuffer8BitAccessVkPhysicalDeviceConditionalRenderingFeaturesEXTVkPhysicalDeviceVulkanMemoryModelFeaturesvulkanMemoryModelAvailabilityVisibilityChainsVkPhysicalDeviceShaderAtomicInt64FeaturesVkPhysicalDeviceShaderAtomicFloatFeaturesEXTVkPhysicalDeviceShaderAtomicFloat2FeaturesEXTshaderBufferFloat16AtomicMinMaxshaderBufferFloat32AtomicMinMaxshaderBufferFloat64AtomicMinMaxshaderSharedFloat16AtomicMinMaxshaderSharedFloat32AtomicMinMaxshaderSharedFloat64AtomicMinMaxshaderImageFloat32AtomicMinMaxsparseImageFloat32AtomicMinMaxVkPhysicalDeviceVertexAttributeDivisorFeaturesKHRvertexAttributeInstanceRateDivisorvertexAttributeInstanceRateZeroDivisorVkPhysicalDeviceASTCDecodeFeaturesEXTVkPhysicalDeviceTransformFeedbackFeaturesEXTVkPhysicalDeviceRepresentativeFragmentTestFeaturesNVVkPhysicalDeviceExclusiveScissorFeaturesNVVkPhysicalDeviceCornerSampledImageFeaturesNVVkPhysicalDeviceComputeShaderDerivativesFeaturesNVVkPhysicalDeviceShaderImageFootprintFeaturesNVVkPhysicalDeviceDedicatedAllocationImageAliasingFeaturesNVdedicatedAllocationImageAliasingVkPhysicalDeviceCopyMemoryIndirectFeaturesNVVkPhysicalDeviceMemoryDecompressionFeaturesNVVkPhysicalDeviceShadingRateImageFeaturesNVVkPhysicalDeviceInvocationMaskFeaturesHUAWEIVkPhysicalDeviceMeshShaderFeaturesNVVkPhysicalDeviceMeshShaderFeaturesEXTprimitiveFragmentShadingRateMeshShaderVkPhysicalDeviceAccelerationStructureFeaturesKHRaccelerationStructureCaptureReplayaccelerationStructureIndirectBuildaccelerationStructureHostCommandsdescriptorBindingAccelerationStructureUpdateAfterBindVkPhysicalDeviceRayTracingPipelineFeaturesKHRrayTracingPipelineShaderGroupHandleCaptureReplayrayTracingPipelineShaderGroupHandleCaptureReplayMixedrayTracingPipelineTraceRaysIndirectVkPhysicalDeviceRayQueryFeaturesKHRVkPhysicalDeviceRayTracingMaintenance1FeaturesKHRrayTracingPipelineTraceRaysIndirect2VkPhysicalDeviceFragmentDensityMapFeaturesEXTfragmentDensityMapNonSubsampledImagesVkPhysicalDeviceFragmentDensityMap2FeaturesEXTVkPhysicalDeviceFragmentDensityMapOffsetFeaturesQCOMVkPhysicalDeviceScalarBlockLayoutFeaturesVkPhysicalDeviceUniformBufferStandardLayoutFeaturesVkPhysicalDeviceDepthClipEnableFeaturesEXTVkPhysicalDeviceMemoryPriorityFeaturesEXTVkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXTVkPhysicalDeviceBufferDeviceAddressFeaturesbufferDeviceAddressCaptureReplaybufferDeviceAddressMultiDeviceVkPhysicalDeviceBufferDeviceAddressFeaturesEXTVkPhysicalDeviceImagelessFramebufferFeaturesVkPhysicalDeviceTextureCompressionASTCHDRFeaturesVkPhysicalDeviceCooperativeMatrixFeaturesNVcooperativeMatrixRobustBufferAccessVkPhysicalDeviceYcbcrImageArraysFeaturesEXTVkPhysicalDevicePresentBarrierFeaturesNVVkPhysicalDevicePerformanceQueryFeaturesKHRperformanceCounterMultipleQueryPoolsVkPhysicalDeviceCoverageReductionModeFeaturesNVVkPhysicalDeviceShaderIntegerFunctions2FeaturesINTELVkPhysicalDeviceShaderClockFeaturesKHRVkPhysicalDeviceIndexTypeUint8FeaturesKHRVkPhysicalDeviceShaderSMBuiltinsFeaturesNVVkPhysicalDeviceFragmentShaderInterlockFeaturesEXTfragmentShaderShadingRateInterlockVkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesVkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXTprimitiveTopologyPatchListRestartVkPhysicalDevicePipelineExecutablePropertiesFeaturesKHRVkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesshaderDemoteToHelperInvocationVkPhysicalDeviceTexelBufferAlignmentFeaturesEXTVkPhysicalDeviceSubgroupSizeControlFeaturesVkPhysicalDeviceLineRasterizationFeaturesKHRVkPhysicalDevicePipelineCreationCacheControlFeaturesVkPhysicalDeviceVulkan11FeaturesVkPhysicalDeviceVulkan12FeaturesVkPhysicalDeviceVulkan13FeaturesshaderZeroInitializeWorkgroupMemoryVkPhysicalDeviceCoherentMemoryFeaturesAMDVkPhysicalDeviceCustomBorderColorFeaturesEXTcustomBorderColorWithoutFormatVkPhysicalDeviceBorderColorSwizzleFeaturesEXTVkPhysicalDeviceExtendedDynamicStateFeaturesEXTVkPhysicalDeviceExtendedDynamicState2FeaturesEXTextendedDynamicState2PatchControlPointsVkPhysicalDeviceExtendedDynamicState3FeaturesEXTextendedDynamicState3TessellationDomainOriginextendedDynamicState3DepthClampEnableextendedDynamicState3PolygonModeextendedDynamicState3RasterizationSamplesextendedDynamicState3SampleMaskextendedDynamicState3AlphaToCoverageEnableextendedDynamicState3AlphaToOneEnableextendedDynamicState3LogicOpEnableextendedDynamicState3ColorBlendEnableextendedDynamicState3ColorBlendEquationextendedDynamicState3ColorWriteMaskextendedDynamicState3RasterizationStreamextendedDynamicState3ConservativeRasterizationModeextendedDynamicState3ExtraPrimitiveOverestimationSizeextendedDynamicState3DepthClipEnableextendedDynamicState3SampleLocationsEnableextendedDynamicState3ColorBlendAdvancedextendedDynamicState3ProvokingVertexModeextendedDynamicState3LineRasterizationModeextendedDynamicState3LineStippleEnableextendedDynamicState3DepthClipNegativeOneToOneextendedDynamicState3ViewportWScalingEnableextendedDynamicState3ViewportSwizzleextendedDynamicState3CoverageToColorEnableextendedDynamicState3CoverageToColorLocationextendedDynamicState3CoverageModulationModeextendedDynamicState3CoverageModulationTableEnableextendedDynamicState3CoverageModulationTableextendedDynamicState3CoverageReductionModeextendedDynamicState3RepresentativeFragmentTestEnableextendedDynamicState3ShadingRateImageEnableVkPhysicalDeviceDiagnosticsConfigFeaturesNVVkPhysicalDeviceZeroInitializeWorkgroupMemoryFeaturesVkPhysicalDeviceShaderSubgroupUniformControlFlowFeaturesKHRshaderSubgroupUniformControlFlowVkPhysicalDeviceRobustness2FeaturesEXTVkPhysicalDeviceImageRobustnessFeaturesVkPhysicalDeviceWorkgroupMemoryExplicitLayoutFeaturesKHRworkgroupMemoryExplicitLayoutScalarBlockLayoutworkgroupMemoryExplicitLayout8BitAccessworkgroupMemoryExplicitLayout16BitAccessVkPhysicalDevice4444FormatsFeaturesEXTVkPhysicalDeviceSubpassShadingFeaturesHUAWEIVkPhysicalDeviceClusterCullingShaderFeaturesHUAWEIVkPhysicalDeviceShaderImageAtomicInt64FeaturesEXTVkPhysicalDeviceFragmentShadingRateFeaturesKHRVkPhysicalDeviceShaderTerminateInvocationFeaturesVkPhysicalDeviceFragmentShadingRateEnumsFeaturesNVsupersampleFragmentShadingRatesnoInvocationFragmentShadingRatesVkPhysicalDeviceImage2DViewOf3DFeaturesEXTVkPhysicalDeviceImageSlicedViewOf3DFeaturesEXTVkPhysicalDeviceAttachmentFeedbackLoopDynamicStateFeaturesEXTattachmentFeedbackLoopDynamicStateVkPhysicalDeviceMutableDescriptorTypeFeaturesEXTVkPhysicalDeviceDepthClipControlFeaturesEXTVkPhysicalDeviceVertexInputDynamicStateFeaturesEXTVkPhysicalDeviceExternalMemoryRDMAFeaturesNVVkPhysicalDeviceColorWriteEnableFeaturesEXTVkPhysicalDeviceSynchronization2FeaturesVkPhysicalDeviceHostImageCopyFeaturesEXTVkPhysicalDevicePrimitivesGeneratedQueryFeaturesEXTprimitivesGeneratedQueryWithRasterizerDiscardprimitivesGeneratedQueryWithNonZeroStreamsVkPhysicalDeviceLegacyDitheringFeaturesEXTVkPhysicalDeviceMultisampledRenderToSingleSampledFeaturesEXTmultisampledRenderToSingleSampledVkPhysicalDevicePipelineProtectedAccessFeaturesEXTVkPhysicalDeviceVideoMaintenance1FeaturesKHRVkPhysicalDeviceInheritedViewportScissorFeaturesNVVkPhysicalDeviceYcbcr2Plane444FormatsFeaturesEXTVkPhysicalDeviceProvokingVertexFeaturesEXTtransformFeedbackPreservesProvokingVertexVkPhysicalDeviceDescriptorBufferFeaturesEXTdescriptorBufferImageLayoutIgnoreddescriptorBufferPushDescriptorsVkPhysicalDeviceShaderIntegerDotProductFeaturesVkPhysicalDeviceFragmentShaderBarycentricFeaturesKHRVkPhysicalDeviceRayTracingMotionBlurFeaturesNVrayTracingMotionBlurPipelineTraceRaysIndirectVkPhysicalDeviceRGBA10X6FormatsFeaturesEXTformatRgba10x6WithoutYCbCrSamplerVkPhysicalDeviceDynamicRenderingFeaturesVkPhysicalDeviceImageViewMinLodFeaturesEXTVkPhysicalDeviceRasterizationOrderAttachmentAccessFeaturesEXTrasterizationOrderColorAttachmentAccessrasterizationOrderDepthAttachmentAccessrasterizationOrderStencilAttachmentAccessVkPhysicalDeviceLinearColorAttachmentFeaturesNVVkPhysicalDeviceGraphicsPipelineLibraryFeaturesEXTVkPhysicalDeviceDescriptorSetHostMappingFeaturesVALVEVkPhysicalDeviceNestedCommandBufferFeaturesEXTnestedCommandBufferSimultaneousUseVkPhysicalDeviceShaderModuleIdentifierFeaturesEXTVkPhysicalDeviceImageCompressionControlFeaturesEXTVkPhysicalDeviceImageCompressionControlSwapchainFeaturesEXTimageCompressionControlSwapchainVkPhysicalDeviceSubpassMergeFeedbackFeaturesEXTVkPhysicalDeviceOpacityMicromapFeaturesEXTVkPhysicalDevicePipelinePropertiesFeaturesEXTVkPhysicalDeviceShaderEarlyAndLateFragmentTestsFeaturesAMDshaderEarlyAndLateFragmentTestsVkPhysicalDeviceNonSeamlessCubeMapFeaturesEXTVkPhysicalDevicePipelineRobustnessFeaturesEXTVkPhysicalDeviceImageProcessingFeaturesQCOMVkPhysicalDeviceTilePropertiesFeaturesQCOMVkPhysicalDeviceAmigoProfilingFeaturesSECVkPhysicalDeviceAttachmentFeedbackLoopLayoutFeaturesEXTVkPhysicalDeviceDepthClampZeroOneFeaturesEXTVkPhysicalDeviceAddressBindingReportFeaturesEXTVkPhysicalDeviceOpticalFlowFeaturesNVVkPhysicalDeviceFaultFeaturesEXTVkPhysicalDevicePipelineLibraryGroupHandlesFeaturesEXTVkPhysicalDeviceShaderCoreBuiltinsFeaturesARMVkPhysicalDeviceFrameBoundaryFeaturesEXTVkPhysicalDeviceDynamicRenderingUnusedAttachmentsFeaturesEXTdynamicRenderingUnusedAttachmentsVkPhysicalDeviceSwapchainMaintenance1FeaturesEXTVkPhysicalDeviceDepthBiasControlFeaturesEXTleastRepresentableValueForceUnormRepresentationVkPhysicalDeviceRayTracingInvocationReorderFeaturesNVVkPhysicalDeviceExtendedSparseAddressSpaceFeaturesNVVkPhysicalDeviceMultiviewPerViewViewportsFeaturesQCOMVkPhysicalDeviceRayTracingPositionFetchFeaturesKHRVkPhysicalDeviceMultiviewPerViewRenderAreasFeaturesQCOMVkPhysicalDeviceShaderObjectFeaturesEXTVkPhysicalDeviceShaderTileImageFeaturesEXTshaderTileImageColorReadAccessshaderTileImageDepthReadAccessshaderTileImageStencilReadAccessVkPhysicalDeviceCooperativeMatrixFeaturesKHRVkPhysicalDeviceCubicClampFeaturesQCOMVkPhysicalDeviceYcbcrDegammaFeaturesQCOMVkPhysicalDeviceCubicWeightsFeaturesQCOMVkPhysicalDeviceImageProcessing2FeaturesQCOMVkPhysicalDeviceDescriptorPoolOverallocationFeaturesNVVkPhysicalDevicePerStageDescriptorSetFeaturesNVVkPhysicalDeviceSchedulingControlsFeaturesARMVkPhysicalDeviceRelaxedLineRasterizationFeaturesIMGVkPhysicalDeviceRenderPassStripedFeaturesARMVkPhysicalDeviceShaderMaximalReconvergenceFeaturesKHRVkPhysicalDeviceShaderSubgroupRotateFeaturesKHRVkPhysicalDeviceShaderExpectAssumeFeaturesKHRVkPhysicalDeviceShaderFloatControls2FeaturesKHRVkPhysicalDeviceDynamicRenderingLocalReadFeaturesKHRVkPhysicalDeviceShaderQuadControlFeaturesKHRVkPhysicalDeviceShaderAtomicFloat16VectorFeaturesNVVkPhysicalDeviceMapMemoryPlacedFeaturesEXT../src/vulkan/runtime/vk_queue.ckernel context creation failedDOOM 64VkPhysicalDeviceFeatures%s.%s not supporteddeviceGeneratedCommandsdeviceGeneratedComputeprivateDatavariablePointersStorageBuffervariablePointersmultiviewmultiviewGeometryShadermultiviewTessellationShaderpresentIdpresentWaitstorageBuffer16BitAccessstoragePushConstant16storageInputOutput16shaderSubgroupExtendedTypessamplerYcbcrConversionprotectedMemorymultiDrawinlineUniformBlockmaintenance4maintenance5maintenance6shaderDrawParametersshaderFloat16shaderInt8hostQueryResetglobalPriorityQuerydeviceMemoryReportruntimeDescriptorArraytimelineSemaphorestorageBuffer8BitAccessstoragePushConstant8conditionalRenderinginheritedConditionalRenderingvulkanMemoryModelvulkanMemoryModelDeviceScopeshaderBufferInt64AtomicsshaderSharedInt64AtomicsshaderBufferFloat32AtomicsshaderBufferFloat32AtomicAddshaderBufferFloat64AtomicsshaderBufferFloat64AtomicAddshaderSharedFloat32AtomicsshaderSharedFloat32AtomicAddshaderSharedFloat64AtomicsshaderSharedFloat64AtomicAddshaderImageFloat32AtomicsshaderImageFloat32AtomicAddsparseImageFloat32AtomicssparseImageFloat32AtomicAddshaderBufferFloat16AtomicsshaderBufferFloat16AtomicAddshaderSharedFloat16AtomicsshaderSharedFloat16AtomicAdddecodeModeSharedExponenttransformFeedbackgeometryStreamsrepresentativeFragmentTestexclusiveScissorcornerSampledImagecomputeDerivativeGroupQuadscomputeDerivativeGroupLinearimageFootprintindirectCopymemoryDecompressionshadingRateImageshadingRateCoarseSampleOrderinvocationMasktaskShadermeshShadermultiviewMeshShadermeshShaderQueriesaccelerationStructurerayTracingPipelinerayTraversalPrimitiveCullingrayQueryrayTracingMaintenance1fragmentDensityMapfragmentDensityMapDynamicfragmentDensityMapDeferredfragmentDensityMapOffsetscalarBlockLayoutuniformBufferStandardLayoutdepthClipEnablememoryPrioritypageableDeviceLocalMemorybufferDeviceAddressimagelessFramebuffertextureCompressionASTC_HDRcooperativeMatrixycbcrImageArrayspresentBarrierperformanceCounterQueryPoolscoverageReductionModeshaderIntegerFunctions2shaderSubgroupClockshaderDeviceClockindexTypeUint8shaderSMBuiltinsfragmentShaderSampleInterlockfragmentShaderPixelInterlockseparateDepthStencilLayoutsprimitiveTopologyListRestartpipelineExecutableInfotexelBufferAlignmentsubgroupSizeControlcomputeFullSubgroupsrectangularLinesbresenhamLinessmoothLinesstippledRectangularLinesstippledBresenhamLinesstippledSmoothLinespipelineCreationCacheControlsamplerMirrorClampToEdgedrawIndirectCountdescriptorIndexingsamplerFilterMinmaxshaderOutputViewportIndexshaderOutputLayersubgroupBroadcastDynamicIdrobustImageAccessshaderTerminateInvocationsynchronization2dynamicRenderingshaderIntegerDotProductdeviceCoherentMemorycustomBorderColorsborderColorSwizzleborderColorSwizzleFromImageextendedDynamicStateextendedDynamicState2extendedDynamicState2LogicOpdiagnosticsConfigrobustBufferAccess2robustImageAccess2nullDescriptorworkgroupMemoryExplicitLayoutformatA4R4G4B4formatA4B4G4R4subpassShadingclustercullingShadermultiviewClusterCullingShadershaderImageInt64AtomicssparseImageInt64AtomicspipelineFragmentShadingRateprimitiveFragmentShadingRateattachmentFragmentShadingRatefragmentShadingRateEnumsimage2DViewOf3Dsampler2DViewOf3DimageSlicedViewOf3DmutableDescriptorTypedepthClipControlvertexInputDynamicStateexternalMemoryRDMAcolorWriteEnablehostImageCopyprimitivesGeneratedQuerylegacyDitheringpipelineProtectedAccessvideoMaintenance1inheritedViewportScissor2Dycbcr2plane444FormatsprovokingVertexLastdescriptorBufferdescriptorBufferCaptureReplayfragmentShaderBarycentricrayTracingMotionBlurminLodlinearColorAttachmentgraphicsPipelineLibrarydescriptorSetHostMappingnestedCommandBuffernestedCommandBufferRenderingshaderModuleIdentifierimageCompressionControlsubpassMergeFeedbackmicromapmicromapCaptureReplaymicromapHostCommandspipelinePropertiesIdentifiernonSeamlessCubeMappipelineRobustnesstextureSampleWeightedtextureBoxFiltertextureBlockMatchtilePropertiesamigoProfilingattachmentFeedbackLoopLayoutdepthClampZeroOnereportAddressBindingopticalFlowdeviceFaultdeviceFaultVendorBinarypipelineLibraryGroupHandlesshaderCoreBuiltinsframeBoundaryswapchainMaintenance1depthBiasControlfloatRepresentationdepthBiasExactrayTracingInvocationReorderextendedSparseAddressSpacemultiviewPerViewViewportsrayTracingPositionFetchmultiviewPerViewRenderAreasshaderObjectcubicRangeClampycbcrDegammaselectableCubicWeightstextureBlockMatch2descriptorPoolOverallocationperStageDescriptorSetdynamicPipelineLayoutschedulingControlsrelaxedLineRasterizationrenderPassStripedshaderMaximalReconvergenceshaderSubgroupRotateshaderSubgroupRotateClusteredshaderExpectAssumeshaderFloatControls2dynamicRenderingLocalReadshaderQuadControlshaderFloat16VectorAtomicsmemoryMapPlacedmemoryMapRangePlacedmemoryUnmapReserveMESA_VK_ENABLE_SUBMIT_THREADINTEL_DECODEcnd_init failedpthread_mutex_init failed: %mgeneral pooldynamic poolinstruction poolsurface state poolworkaroundbinding table poolhasvk%s 24.1.2 build fullfloatssurfacesaccumulatevb-data??????????VK_KHR_8bit_storageVK_KHR_16bit_storageVK_KHR_acceleration_structure VK_KHR_bind_memory2VK_KHR_buffer_device_addressVK_KHR_calibrated_timestampsVK_KHR_cooperative_matrixVK_KHR_copy_commands2VK_KHR_create_renderpass2VK_KHR_dedicated_allocationVK_KHR_deferred_host_operationsVK_KHR_depth_stencil_resolveVK_KHR_descriptor_update_templateVK_KHR_device_groupVK_KHR_display_swapchain VK_KHR_draw_indirect_countVK_KHR_driver_propertiesVK_KHR_dynamic_renderingVK_KHR_dynamic_rendering_local_readVK_KHR_external_fenceVK_KHR_external_fence_fdVK_KHR_external_fence_win32VK_KHR_external_memoryVK_KHR_external_memory_fdVK_KHR_external_memory_win32VK_KHR_external_semaphoreVK_KHR_external_semaphore_fdVK_KHR_external_semaphore_win32VK_KHR_format_feature_flags2VK_KHR_fragment_shader_barycentricVK_KHR_fragment_shading_rateVK_KHR_get_memory_requirements2VK_KHR_global_priorityVK_KHR_image_format_listVK_KHR_imageless_framebufferVK_KHR_incremental_presentVK_KHR_index_type_uint8VK_KHR_line_rasterizationVK_KHR_load_store_op_noneVK_KHR_maintenance1VK_KHR_maintenance2VK_KHR_maintenance3VK_KHR_maintenance4VK_KHR_maintenance5VK_KHR_maintenance6VK_KHR_map_memory2VK_KHR_multiviewVK_KHR_performance_queryVK_KHR_pipeline_executable_propertiesVK_KHR_pipeline_libraryVK_KHR_portability_subsetVK_KHR_present_idVK_KHR_present_waitVK_KHR_push_descriptorVK_KHR_ray_queryVK_KHR_ray_tracing_maintenance1VK_KHR_ray_tracing_pipelineVK_KHR_ray_tracing_position_fetchVK_KHR_relaxed_block_layoutVK_KHR_sampler_mirror_clamp_to_edgeVK_KHR_sampler_ycbcr_conversionVK_KHR_separate_depth_stencil_layoutsVK_KHR_shader_atomic_int64VK_KHR_shader_clockVK_KHR_shader_draw_parametersVK_KHR_shader_expect_assumeVK_KHR_shader_float16_int8VK_KHR_shader_float_controlsVK_KHR_shader_float_controls2VK_KHR_shader_integer_dot_productVK_KHR_shader_maximal_reconvergenceVK_KHR_shader_non_semantic_infoVK_KHR_shader_quad_controlVK_KHR_shader_subgroup_extended_typesVK_KHR_shader_subgroup_rotateVK_KHR_shader_subgroup_uniform_control_flowVK_KHR_shader_terminate_invocationVK_KHR_shared_presentable_imageVK_KHR_spirv_1_4VK_KHR_storage_buffer_storage_classVK_KHR_swapchainFVK_KHR_swapchain_mutable_formatVK_KHR_synchronization2VK_KHR_timeline_semaphoreVK_KHR_uniform_buffer_standard_layoutVK_KHR_variable_pointersVK_KHR_vertex_attribute_divisorVK_KHR_video_decode_av1VK_KHR_video_decode_h264 VK_KHR_video_decode_h265VK_KHR_video_decode_queueVK_KHR_video_encode_h264VK_KHR_video_encode_h265VK_KHR_video_encode_queue VK_KHR_video_maintenance1VK_KHR_video_queueVK_KHR_vulkan_memory_modelVK_KHR_win32_keyed_mutexVK_KHR_workgroup_memory_explicit_layoutVK_KHR_zero_initialize_workgroup_memoryVK_EXT_4444_formatsVK_EXT_astc_decode_modeVK_EXT_attachment_feedback_loop_dynamic_stateVK_EXT_attachment_feedback_loop_layoutVK_EXT_blend_operation_advancedVK_EXT_border_color_swizzleVK_EXT_buffer_device_addressVK_EXT_calibrated_timestampsVK_EXT_color_write_enableVK_EXT_conditional_renderingVK_EXT_conservative_rasterizationVK_EXT_custom_border_color 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ad_intersection_opaque_amdload_invocation_idload_is_indexed_drawload_kernel_inputload_layer_idload_lds_ngg_scratch_base_amdload_leaf_opaque_intelload_leaf_procedural_intelload_line_coordload_line_widthload_local_invocation_idload_local_invocation_indexload_local_pixel_agxload_local_shared_r600load_lshs_vertex_stride_amdload_merged_wave_info_amdload_mesh_inline_data_intelload_mesh_view_countload_mesh_view_indicesload_multisampled_panload_num_subgroupsload_num_verticesload_num_workgroupsload_ordered_id_amdload_outputload_paramload_patch_vertices_inload_per_primitive_outputload_per_vertex_inputload_per_vertex_outputload_persp_center_rhw_ir3load_pixel_coordload_point_coordload_poly_line_smooth_enabledload_polygon_stipple_agxload_preambleload_primitive_idload_primitive_location_ir3load_printf_buffer_addressload_provoking_lastload_provoking_vtx_amdload_push_constantload_push_constant_zinkload_raw_output_panload_ray_base_mem_addr_intelload_ray_flagsload_ray_geometry_indexload_ray_hit_kindload_ray_hit_sbt_addr_intelload_ray_hit_sbt_stride_intelload_ray_hw_stack_size_intelload_ray_launch_idload_ray_launch_sizeload_ray_miss_sbt_addr_intelload_ray_object_directionload_ray_object_originload_ray_object_to_worldload_ray_query_global_intelload_ray_sw_stack_size_intelload_ray_t_maxload_ray_t_minload_ray_world_directionload_ray_world_originload_ray_world_to_objectload_regload_reg_indirectload_rel_patch_id_ir3load_reloc_const_intelload_ring_attr_amdload_ring_attr_offset_amdload_ring_es2gs_offset_amdload_ring_esgs_amdload_ring_gs2vs_offset_amdload_ring_gsvs_amdload_ring_mesh_scratch_amdload_ring_task_draw_amdload_ring_task_payload_amdload_ring_tess_factors_amdload_ring_tess_offchip_amdload_rt_conversion_panload_sample_idload_sample_id_no_per_sampleload_sample_maskload_sample_mask_inload_sample_posload_sample_pos_from_idload_sample_pos_or_centerload_sample_positions_agxload_sample_positions_amdload_sample_positions_panload_sampler_handle_agxload_samples_log2_agxload_sbt_base_amdload_sbt_offset_amdload_sbt_stride_amdload_scalar_arg_amdload_scratchload_scratch_base_ptrload_shader_indexload_shader_part_tests_zs_agxload_shader_record_ptrload_sharedload_shared2_amdload_shared_base_ptrload_shared_block_intelload_shared_ir3load_simd_width_intelload_sm_count_nvload_sm_id_nvload_smem_amdload_ssboload_ssbo_addressload_ssbo_block_intelload_ssbo_ir3load_ssbo_uniform_block_intelload_stackload_stat_query_address_agxload_streamout_buffer_amdload_streamout_config_amdload_streamout_offset_amdload_subgroup_eq_maskload_subgroup_ge_maskload_subgroup_gt_maskload_subgroup_idload_subgroup_id_shift_ir3load_subgroup_invocationload_subgroup_le_maskload_subgroup_lt_maskload_subgroup_sizeload_sysval_agxload_sysval_nvload_task_payloadload_task_ring_entry_amdload_tcs_header_ir3load_tcs_in_param_base_r600load_tcs_num_patches_amdload_tcs_out_param_base_r600load_tcs_primitive_mode_amdload_tcs_rel_patch_id_r600load_tess_coordload_tess_coord_xyload_tess_factor_base_ir3load_tess_level_innerload_tess_level_inner_defaultload_tess_level_outerload_tess_level_outer_defaultload_tess_param_base_ir3load_tess_param_buffer_agxload_tess_rel_patch_id_amdload_tex_sprite_mask_agxload_texture_handle_agxload_texture_scaleload_texture_size_etnaload_tlb_color_v3dload_topology_id_intelload_typed_buffer_amdload_uboload_ubo_uniform_block_intelload_ubo_vec4load_uniformload_user_clip_planeload_user_data_amdload_uvs_index_agxload_vbo_base_agxload_vector_arg_amdload_vertex_idload_vertex_id_zero_baseload_view_indexload_viewport_offsetload_viewport_scaleload_viewport_x_offsetload_viewport_x_scaleload_viewport_y_offsetload_viewport_y_scaleload_viewport_z_offsetload_viewport_z_scaleload_vs_output_buffer_agxload_vs_output_buffer_ptr_agxload_vs_outputs_agxload_vs_primitive_stride_ir3load_vs_vertex_stride_ir3load_vulkan_descriptorload_warp_id_nvload_warps_per_sm_nvload_work_dimload_workgroup_idload_workgroup_id_zero_baseload_workgroup_indexload_workgroup_sizeload_xfb_addressload_xfb_index_bufferload_xfb_sizemasked_swizzle_amdmbcnt_amdmemcpy_derefoptimization_barrier_sgpr_amdoptimization_barrier_vgpr_amdoverwrite_tes_arguments_amdoverwrite_vs_arguments_amdpreamble_end_ir3preamble_start_ir3printfquad_broadcastquad_swap_diagonalquad_swap_horizontalquad_swap_verticalquad_swizzle_amdquad_vote_allquad_vote_anyread_first_invocationread_invocationread_invocation_cond_ir3reduce_clusters_ir3report_ray_intersectionresource_intelrotaterq_confirm_intersectionrq_generate_intersectionrq_initializerq_loadrq_proceedrq_terminatert_execute_callablert_resumert_return_amdrt_trace_raysendmsg_amdshader_clockshared_atomicshared_atomic_swapshuffleshuffle_downshuffle_upshuffle_xorsparse_residency_code_andssa_bar_nvssbo_atomicssbo_atomic_ir3ssbo_atomic_swapssbo_atomic_swap_ir3stack_map_agxstack_unmap_agxstore_buffer_amdstore_combined_output_panstore_derefstore_deref_block_intelstore_globalstore_global_2x32store_global_amdstore_global_block_intelstore_global_ir3store_hit_attrib_amdstore_local_pixel_agxstore_local_shared_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FINISHME: support YUV colorspace with DRM format modifiers%s:%d: FINISHME: support more multi-planar formats with DRM modifiersVK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT requires VK_IMAGE_TYPE_2DVK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT requires VK_IMAGE_TILING_LINEAR or VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXTVK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT requires VK_IMAGE_TILING_LINEAR or VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXTunsupported VkExternalMemoryTypeFlagBits 0x%x../src/intel/vulkan_hasvk/anv_image.cVkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts[]::offset is misalignedVkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts[]::offset is too smallinternal error: overflow in %sVkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts[]::offset is too largeVkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts[%u]::rowPitch is 0VkImageDrmFormatModifierExplicitCreateInfoEXT::pPlaneLayouts[%u]::offset is %luWARNING: batch size exceeds INTEL_MEASURE limit: %d. Data has been dropped. Increase setting with INTEL_MEASURE=batch_size={count} atomic_add_gs_emit_prim_count_amdatomic_add_shader_invocation_count_amdatomic_counter_comp_swap_derefbindless_image_fragment_mask_load_amdbindless_image_samples_identicalbindless_image_store_raw_intelcopy_push_const_to_uniform_ir3finalize_incoming_node_payloadimage_deref_fragment_mask_load_amdlaunch_mesh_workgroups_with_payload_derefload_active_subgroup_invocation_agxload_barycentric_coord_at_offsetload_barycentric_coord_at_sampleload_barycentric_coord_centroidload_base_global_invocation_idload_blend_const_color_a_floatload_blend_const_color_aaaa8888_unormload_blend_const_color_b_floatload_blend_const_color_g_floatload_blend_const_color_r_floatload_blend_const_color_rgba8888_unormload_btd_global_arg_addr_intelload_btd_resume_sbt_addr_intelload_callable_sbt_stride_intelload_cull_back_face_enabled_amdload_cull_front_face_enabled_amdload_cull_small_prim_precision_amdload_cull_small_primitives_enabled_amdload_desc_set_dynamic_index_intelload_geometry_param_buffer_agxload_global_constant_uniform_block_intelload_global_invocation_id_zero_baseload_hs_out_patch_data_offset_amdload_input_assembly_buffer_agxload_lds_ngg_gs_out_vertex_base_amdload_num_vertices_per_primitive_amdload_packed_passthrough_primitive_amdload_pipeline_stat_query_enabled_amdload_point_coord_maybe_flippedload_prim_gen_query_enabled_amdload_prim_xfb_query_enabled_amdload_provoking_vtx_in_prim_amdload_rasterization_primitive_amdload_rasterization_samples_amdload_ray_instance_custom_indexload_ray_miss_sbt_stride_intelload_ray_num_dss_rt_stacks_intelload_ray_tracing_stack_base_lvpload_ray_triangle_vertex_positionsload_resume_shader_address_amdload_ring_mesh_scratch_offset_amdload_ring_tess_factors_offset_amdload_ring_tess_offchip_offset_amdload_rt_arg_scratch_offset_amdload_rt_dynamic_callable_stack_base_amdload_sampler_lod_parameters_panload_shader_call_data_offset_lvpload_shared_uniform_block_intelload_streamout_write_index_amdload_tcs_tess_factor_base_r600load_tcs_tess_levels_to_tes_amdload_viewport_xy_scale_and_offsetload_workgroup_num_input_primitives_amdload_workgroup_num_input_vertices_amdordered_xfb_counter_add_gfx11_amdset_vertex_and_primitive_countI915_FORMAT_MOD_Y_TILED_GEN12_RC_CCSI915_FORMAT_MOD_Y_TILED_GEN12_MC_CCSI915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CCI915_FORMAT_MOD_4_TILED_DG2_RC_CCSI915_FORMAT_MOD_4_TILED_DG2_MC_CCSI915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CCI915_FORMAT_MOD_4_TILED_MTL_RC_CCSI915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CCI915_FORMAT_MOD_4_TILED_MTL_MC_CCS22<<22<2<2<222 1tZtZtZZdYZZZZdYdYZtZdYdYdY;;;;;tZ\`|``_<`L`\`\`l`\`\`\`\`\`\`\`\`;' ;;ኢ;;;;;;;?;?5?;?;?;?;?;?;?;?;?;U:鉢ۉ͉::::::::::뉢݉ω::m:::::::??3D?(??&?????X?t??6?2??=view index@`k@?0(((0@@00((((((((m{SiV-(++99999(9999999(999999999999999(14elk_fs_visitor18elk_backend_shaderN3elk12vec4_visitorEN3elk15gfx6_gs_visitorEN3elk15vec4_gs_visitorE|x xxHf ../src/intel/vulkan_hasvk/anv_perf.cNIR (from SPIR-V) for %s shader: ../src/vulkan/runtime/vk_pipeline_cache.cRan out of memory serializing NIR shaderVulkan push constants and API paramsDescriptor buffer for set %d (start=%dB)Inline shader constant data (start=%dB)UBO (set=%d binding=%d start=%dB)/proc/sys/dev/i915/perf_stream_paranoidDRM fd is not a character device as expected /sys/dev/char/%d:%d/device/drm/sys/dev/char/%d:%d/device/drm/%sFailed to find cardX directory under /sys/dev/char/%d:%d/device/drm metric set: %s (already loaded) Failed to load "%s" (%s) metrics set in kernel: %s ../src/intel/vulkan_hasvk/anv_pipeline.cFound a partial pipeline in the cache. This is most likely caused by an incomplete pipeline cache import or export%.8s-%.4s-%.4s-%.4s-%.12s%s/metrics/%s/idi915-perf config failed: %mPush constant ranges: RANGE%d (%dB): INTEL_EXTENDED_METRICSFailed to stat DRM fd Failed to open %s: %m gt_min_freq_mhzgt_max_freq_mhzmetric set: %s (added) layer IDzero_init_iteratorunnamedGS Input GS Output %s geometry shader %sMESA_SHADER_VERTEXMESA_SHADER_TESS_CTRLMESA_SHADER_TESS_EVALMESA_SHADER_GEOMETRYMESA_SHADER_FRAGMENTMESA_SHADER_COMPUTEMESA_SHADER_TASKMESA_SHADER_MESHMESA_SHADER_RAYGENMESA_SHADER_ANY_HITMESA_SHADER_CLOSEST_HITMESA_SHADER_MISSMESA_SHADER_INTERSECTIONMESA_SHADER_CALLABLEMESA_SHADER_KERNEL?=SIMDvec%s%d %sfragment%s%d %s shaderpc: emit PC=( ) reason: %s +dc_flush +hdc_flush +tile_flush +const_inval +vf_inval +ic_inval +pb_stall +cs_stall +utdp_flushrendervideovideo-enhunknownutracetraceq%s%uafter transition RTnew cmd bufferbefore blorp prep fast clearpipe barrierintel_begin_cmd_bufferintel_begin_stallINTEL_MEASURE failed to read control fifo: %s INTEL_MEASURE invalid frame count on control fifo. org.freedesktop.mesa.intel.gpu%u../src/intel/vulkan_hasvk/genX_cmd_buffer.cDoing a potentially unnecessary fast-clear to define an MCS buffer.SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d 0wvXwHw8w7ȘTvϣУ0Уϣ0УϣϣϣУϣϣϣϣϣϣϣУϣϣϣϣϣϣϣϣϣϣϣϣϣϣϣPУgfx7_cmd_buffer_config_l3gfx7_cmd_buffer_emit_state_base_addressgfx7_emit_apply_pipe_flushes   !!""##$$%&'()*+,-./012334567899:;<=>?@A  !""#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'(()))*+,-./012334567789:;<=>?@ABCDDEEFFGGHHIJJKKLLMMNNOOPPQRRSSTUUVWXYZ[\]^_`abcdefghijklmnopqrstuuvvwwxxyyzz{{||}}~~ @ @ @ Instruction CounNumber of GEN instructions in the final generated shader executaNumber of instructions in the final generated shader executable which access external units such as the constant cache or the saNumber of loops (not unrolled) in the final generated shader exeEstimate of the number of EU cycles required to execute the final generated executable. This is an estimate only and may vary greatly from actual run-time perfNumber of scratch spill operations. This gives a rough estimate of the cost incurred due to spilling temporary values to memory. If this is non-zero, you may want to adjust your shader to reduce register prh fill operations. This gives a rough estimate of the cost incurred due to spilling temporary values to memory. If this is non-zero, you may want to adjust your shader to reduce register preScratch Memory SNumber of bytes of scratch memory required by the generated shader executable. If this is non-zero, you may want to adjust your shader to reduce register pressWorkgroup Memoryof workgroup shared memory used by this shader including any padFinal NIR before going into the back-end compileFinal GEN assembly for the generated shader binaBound a image to a descriptor where the descriptor does not have NonReadable set and the image does not have a corresponding SPIR-V format enum.anvbefore SO_BUFFER change WAdraw indexedintel_begin_draw_indexedintel_end_draw_indexedintel_begin_draw_multiintel_end_draw_multiintel_begin_drawintel_end_drawTṿ̣,̣\ˣDʣʣʣtͣtͣϣͣϣͣͣ$Σ$Σtͣ gfx7_cmd_buffer_flush_gfx_state&'()*+,-./Fdraw indexed_multidraw indirectdraw indexed indirectintel_begin_draw_indirectintel_end_draw_indirectintel_end_draw_indexed_multi%s:%d: FINISHME: Multiview + indirect draw requires MI_MATH; MI_MATH is not supported on Ivy Bridgeintel_begin_draw_indexed_indirectintel_end_draw_indexed_indirectintel_begin_draw_indexed_multibegin transform feedbackend transform feedbackdraw indirect countdraw indexed indirect countflush compute statevkCmdDispatchIndirectcompute indirectintel_begin_computeintel_end_computeintel_end_draw_indirect_countcmd parser version %d is required for %sintel_begin_draw_indexed_indirect_countintel_end_draw_indexed_indirect_countintel_begin_draw_indirect_countgfx7_cmd_buffer_emit_gfx7_depth_flushperf counter isolationwait eventMSAA resolveintel_end_cmd_bufferintel_begin_render_pass%s:%d: FINISHME: Implement events on gfx7flush and invalidate for PIPELINE_SELECTCannot fast-clear to colors which would require format conversion on resolveRendering with multi-lod or multi-layer framebuffer with LOAD_OP_LOAD and baseMipLevel > 0 or baseArrayLayer > 0. Not fast clearing.Rendering to a multi-layer framebuffer with LOAD_OP_CLEAR. Only fast-clearing the first sliceafter copy_fast_clear_dwords. Avoid potential hangafter copy_fast_clear_dwords surface state updateemit_isp_disablegfx7_cmd_emit_timestampgfx7_CmdResetEvent2gfx7_CmdSetEvent2 ܞlܞl@p@@/////@@@@@//@,3'?333333333333     ??>>> ?@?>@>> ?P?P?0?0?@>>`??=>>>@??p?>`?p?=?>>0?P??>@>@>P?=>0?p?p?=>>`?>> ? ?`?@?@?>>??## #(#0#8#@#H###"  query-poolquery timeout../src/intel/vulkan_hasvk/genX_query.cvkCmdResetQueryPool of timestamps%s:%d: FINISHME: Queries not yet supported on Ivy Bridge../src/intel/vulkan_hasvk/genX_state.c../src/intel/vulkan_hasvk/genX_pipeline.cEnabled dual-src blend factors without writing both targets in the shader. Disabling blending to avoid GPU hangs.yA`AC>@Ap?CGˡE/@\RHSRHSVR4SR4SZZYY3X[VVWWW@W4WpppboXoTv§§§`§§ §gfx75_cmd_buffer_config_l3gfx75_cmd_buffer_emit_state_base_addressgfx75_emit_apply_pipe_flushesgfx75_cmd_buffer_flush_gfx_statedraw indirect byte countintel_begin_draw_indirect_byte_countintel_end_draw_indirect_byte_countgfx75_cmd_buffer_emit_gfx7_depth_flushemit_isp_disablegfx75_cmd_emit_timestampgfx75_CmdResetEvent2gfx75_CmdSetEvent2CopyQueryPoolResultsX XX0DDjrjw`dHd d:b0b88$$j;+QEbXTvgfx8_cmd_buffer_emit_state_base_addressgfx8_emit_apply_pipe_flushesTv$$$#"""%%'L%W(L%L%l&l&%)OPxO)OxO)O)O)OO)O)O)O)O)O)O)OAP)O)O)O)O)O)O)O)O)O)O)O)O)O)O)OOgfx8_cmd_buffer_config_l3vb > 32b rangeSecondary cmd buffer not tracked in VF cacheemit_isp_disablegfx8_cmd_emit_timestampgfx8_CmdResetEvent2gfx8_CmdSetEvent2tte``b™6ҚPh  00@@_VARIABLE_REFRESH2,:?>>0?P??>@>@>P?=>0?p?p?=>>`?>> ? ?`?@?@?>>??MESA: failed to import sync file '%s'Use of VkSurfacePresentModeCompatibilityEXT without a VkSurfacePresentModeEXT set. This is an application bug. vulkan: No DRI3 support detected - required for presentation Note: you can probably enable DRI3 in your Xorg config wp_linux_drm_syncobj_manager_v1Unsupported MESA_VK_WSI_PRESENT_MODE value! mesa vk surface %d swapchain %d queueCould not remove trace trigger file, ignoring wp_linux_drm_syncobj_surface_v1wp_linux_drm_syncobj_timeline_v1SYNCDRI3PresentRANDRXFIXESXWAYLANDMIT-SHMATIFGLRXDRINV-CONTROLWSI swapchain queuezwp_linux_dmabuf_v1wp_presentationwp_tearing_control_manager_v1mesa-sharedWSI swapchain eventset_presentation_hintdestroysync_outputpresenteduuuuuuudiscardedset_acquire_pointouuset_release_pointformat_tablehumain_devicetranche_donetranche_target_devicetranche_formatstranche_flagscreatedhuuuuucreatecreate_immed2niiuuget_tearing_controlclock_idget_surfaceimport_timeline3uuucreate_paramsget_default_feedback4nget_surface_feedback4nowp_tearing_control_v1zwp_linux_buffer_params_v1wp_presentation_feedbackzwp_linux_dmabuf_feedback_v1>@>P??>0?= ?`?>>>@??monitorDPMSCONNECTOR_IDiiiisiciSiCi3i#iihhhhhvh)hh hggggggggygigYgIg9g)gg gfffffRYfIf9f)ff feeeerebeReBe2e"edtdddTdDd4d$dddccc}cmc]cMcbbbvbfbVbaaaaaaaavafaVaFa6a&aaa````````/```_________o___O_?_/___^^^^^^^^^o^_^O^?^/^^^]]]][[[s[c[S[C[3[#[[[ZZZZZ]]]]]o]]]\Z\\[[[[[(ZZZ}YmY]YXXXuXWWeXsWcWWW{VkV[VKV;V+VVUUU3UTT.TSSYSi2XR24,XR24@@$@?iW>%^D' 뿱ʿcK4% ྱ¾iG% ⽱ý`C켱gQ>/һzdQB/̺pW>,幱ҹsE丱ǸtI0跱ϷnV8 ٶƶ^*tbO<)״ŴuV,䳱ҳ|jXF4"貱ֲIJygUA/౱αm[I3!갱װİt^A+㯱Яq^K8"߮zdQ>+ ୱƭsc-../src/vulkan/runtime/vk_acceleration_structure.c../src/vulkan/runtime/vk_command_pool.cvertexPipelineStoresAndAtomicsshaderTessellationAndGeometryPointSizeshaderStorageImageExtendedFormatsshaderStorageImageReadWithoutFormatshaderStorageImageWriteWithoutFormatshaderUniformBufferArrayDynamicIndexingshaderSampledImageArrayDynamicIndexingshaderStorageBufferArrayDynamicIndexingshaderStorageImageArrayDynamicIndexingmesa: Unfreed resources detected at device destroy, there may be memory leaks! robustBufferAccessfullDrawIndexUint32imageCubeArrayindependentBlendgeometryShadertessellationShadersampleRateShadingdualSrcBlendlogicOpmultiDrawIndirectdrawIndirectFirstInstancedepthClampdepthBiasClampfillModeNonSoliddepthBoundswideLineslargePointsalphaToOnemultiViewportsamplerAnisotropytextureCompressionETC2textureCompressionASTC_LDRtextureCompressionBCocclusionQueryPrecisepipelineStatisticsQueryfragmentStoresAndAtomicsshaderImageGatherExtendedshaderStorageImageMultisampleshaderClipDistanceshaderCullDistanceshaderFloat64shaderInt64shaderInt16shaderResourceResidencyshaderResourceMinLodsparseBindingsparseResidencyBuffersparseResidencyImage2DsparseResidencyImage3DsparseResidency2SamplessparseResidency4SamplessparseResidency8SamplessparseResidency16SamplessparseResidencyAliasedvariableMultisampleRateinheritedQueries(00poppppppppptphp\pPpDp8p,p#ppppooooPyyzzy\yLy4zzz{DzTzdztzzzzzzzz{$zVK_OBJECT_TYPE_UNKNOWNUnknown VkObjectType value.VK_OBJECT_TYPE_DEVICEVK_OBJECT_TYPE_QUEUEVK_OBJECT_TYPE_SEMAPHOREVK_OBJECT_TYPE_COMMAND_BUFFERVK_OBJECT_TYPE_FENCEVK_OBJECT_TYPE_DEVICE_MEMORYVK_OBJECT_TYPE_BUFFERVK_OBJECT_TYPE_IMAGEVK_OBJECT_TYPE_EVENTVK_OBJECT_TYPE_QUERY_POOLVK_OBJECT_TYPE_BUFFER_VIEWVK_OBJECT_TYPE_IMAGE_VIEWVK_OBJECT_TYPE_SHADER_MODULEVK_OBJECT_TYPE_PIPELINE_CACHEVK_OBJECT_TYPE_RENDER_PASSVK_OBJECT_TYPE_PIPELINEVK_OBJECT_TYPE_SAMPLERVK_OBJECT_TYPE_DESCRIPTOR_SETVK_OBJECT_TYPE_FRAMEBUFFERVK_OBJECT_TYPE_COMMAND_POOLVK_OBJECT_TYPE_SURFACE_KHRVK_OBJECT_TYPE_SWAPCHAIN_KHRVK_OBJECT_TYPE_DISPLAY_KHRVK_OBJECT_TYPE_CU_MODULE_NVXVK_OBJECT_TYPE_CUDA_MODULE_NVVK_OBJECT_TYPE_MICROMAP_EXTVK_OBJECT_TYPE_SHADER_EXTVK_OBJECT_TYPE_MAX_ENUMVK_OBJECT_TYPE_INSTANCE%s:%dVK_ERROR_NOT_PERMITTED_KHRVK_ERROR_FRAGMENTATIONVK_ERROR_OUT_OF_POOL_MEMORYVK_ERROR_INVALID_SHADER_NVVK_ERROR_OUT_OF_DATE_KHRVK_ERROR_SURFACE_LOST_KHRVK_ERROR_UNKNOWNVK_ERROR_FRAGMENTED_POOLVK_ERROR_FORMAT_NOT_SUPPORTEDVK_ERROR_TOO_MANY_OBJECTSVK_ERROR_INCOMPATIBLE_DRIVERVK_ERROR_FEATURE_NOT_PRESENTVK_ERROR_LAYER_NOT_PRESENTVK_ERROR_MEMORY_MAP_FAILEDVK_ERROR_DEVICE_LOSTVK_ERROR_OUT_OF_DEVICE_MEMORYVK_ERROR_OUT_OF_HOST_MEMORYVK_SUCCESSVK_NOT_READYVK_TIMEOUTVK_EVENT_SETVK_EVENT_RESETVK_INCOMPLETEVK_SUBOPTIMAL_KHRVK_THREAD_IDLE_KHRVK_THREAD_DONE_KHRVK_OPERATION_DEFERRED_KHRVK_OPERATION_NOT_DEFERRED_KHRVK_PIPELINE_COMPILE_REQUIREDVK_RESULT_MAX_ENUMUnknown VkResult value.%s (%s)EMULATEDASSISTEDNATIVETimeline mode is %s.MESA_VK_ABORT_ON_DEVICE_LOSScnd_wait failedTime point >= %lu not foundcnd_broadcast failedthrd_create failedMESA_VK_MAX_TIMEOUTMaximum timeout exceeded!Wait for time points failedqueue::driver_submit failedcnd_timedwait failedVK_OBJECT_TYPE_PHYSICAL_DEVICEVK_OBJECT_TYPE_PIPELINE_LAYOUTVK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUTVK_OBJECT_TYPE_DESCRIPTOR_POOLVK_OBJECT_TYPE_DISPLAY_MODE_KHRVK_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXTVK_OBJECT_TYPE_VIDEO_SESSION_KHRVK_OBJECT_TYPE_VIDEO_SESSION_PARAMETERS_KHRVK_OBJECT_TYPE_CU_FUNCTION_NVXVK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATEVK_OBJECT_TYPE_DEBUG_UTILS_MESSENGER_EXTVK_OBJECT_TYPE_ACCELERATION_STRUCTURE_KHRVK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSIONVK_OBJECT_TYPE_VALIDATION_CACHE_EXTVK_OBJECT_TYPE_ACCELERATION_STRUCTURE_NVVK_OBJECT_TYPE_PERFORMANCE_CONFIGURATION_INTELVK_OBJECT_TYPE_DEFERRED_OPERATION_KHRVK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVVK_OBJECT_TYPE_PRIVATE_DATA_SLOTVK_OBJECT_TYPE_CUDA_FUNCTION_NVVK_OBJECT_TYPE_BUFFER_COLLECTION_FUCHSIAVK_OBJECT_TYPE_OPTICAL_FLOW_SESSION_NVvk_log*() called with NULL object vk_log*() called with client-invisible object %p of type %sVK_ERROR_COMPRESSION_EXHAUSTED_EXTVK_ERROR_INVALID_VIDEO_STD_PARAMETERS_KHRVK_ERROR_INVALID_DEVICE_ADDRESS_EXTVK_ERROR_FULL_SCREEN_EXCLUSIVE_MODE_LOST_EXTVK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXTVK_ERROR_INVALID_EXTERNAL_HANDLEVK_ERROR_VIDEO_STD_VERSION_NOT_SUPPORTED_KHRVK_ERROR_VIDEO_PROFILE_CODEC_NOT_SUPPORTED_KHRVK_ERROR_VIDEO_PROFILE_FORMAT_NOT_SUPPORTED_KHRVK_ERROR_VIDEO_PROFILE_OPERATION_NOT_SUPPORTED_KHRVK_ERROR_VIDEO_PICTURE_LAYOUT_NOT_SUPPORTED_KHRVK_ERROR_IMAGE_USAGE_NOT_SUPPORTED_KHRVK_ERROR_VALIDATION_FAILED_EXTVK_ERROR_INCOMPATIBLE_DISPLAY_KHRVK_ERROR_NATIVE_WINDOW_IN_USE_KHRVK_ERROR_EXTENSION_NOT_PRESENTVK_ERROR_INITIALIZATION_FAILEDVK_INCOMPATIBLE_SHADER_BINARY_EXT../src/vulkan/runtime/vk_sync_timeline.c../src/vulkan/runtime/vk_pipeline_layout.cDRM_IOCTL_SYNCOBJ_CREATE failed: %m../src/vulkan/runtime/vk_drm_syncobj.cDRM_IOCTL_SYNCOBJ_SIGNAL failed: %mDRM_IOCTL_SYNCOBJ_QUERY failed: %mDRM_IOCTL_SYNCOBJ_RESET failed: %mDRM_IOCTL_SYNCOBJ_WAIT failed: %mDRM_IOCTL_SYNCOBJ_FD_TO_HANDLE failed: %mDRM_IOCTL_SYNCOBJ_HANDLE_TO_FD failed: %m../src/vulkan/runtime/vk_descriptor_update_template.cCombination of external handle types is unsupported for VkFence creation.../src/vulkan/runtime/vk_fence.cCombination of external handle types is unsupported for VkSemaphore creation.../src/vulkan/runtime/vk_semaphore.c../src/vulkan/runtime/vk_sync.cTried to signal a timeline with value 0Cannot export a timeline semaphore as SYNC_FDTimeline values must only ever strictly increase.Cannot temporarily import into a timeline semaphoreԲԲԲԲԲԲԲԲ(8 LO{{{{O{{{{hQ{{{{{{{{{Q{{{{{{{{{PtQWWWWOWWWWOWWWWWWWWWRWWWWWWWWWQWWWWRWWWWTRWWWWWWWWWRWWWWWWWWWWWWWWWWWWWQWWWWWWWWW>EC>A B? >BCDnE@A~?=BvCYD2E@AB?=tB:CDDQ@lA?Y=```ˋˋȋpۋۋwwH؋@㋳㋳WWp0 0pp`ppЍ @0pppppppppЍ pppppЍppPTddd$$4dDDTTTDD䈳䈳DtttTTDTDDDDT4444444ԈԈ4ĈĈ4444pЄ`0HԈĈ4$aaaataaaaaaaadaaaaaaaTDaaaaaaaaaaaaaaaaaaaaaaȆ膳؆44ĈĈ䈳䈳DDD444ddttddd䓳dĔ\TTܚTԗTTT˛˛$4˛˛˛D43333333VUUUUUUU$I$I$43333333 ;;E]tE6P^Cy  +)}A_q>cp>@IG8p[as  d8ַ1%re9;9y$*r긍p-s8 2a58rP#t>FDm= 5#3#VDrE݅E@{FyFC|>ء0N svUZ}44h-tmZ.tifgfAi.:ֳ.:sqW )'ꍋ{ [4#Y4#XE”E@gFgFW y͌w͌h#rt*r7Z7373L,\t-\tffffo.:.:%#DD陙癙è 1:3#/:3#EE@qgfFogfFǰ̌@ZtFZt s z 33(3A3[3u333gggCgvggggDxF{;XBB0 {       nV^ PCcd>8WffZD$1~p VR!@}"C#%')gj+A-.M01U4R797*@BDHL]vORUXYY[# ^ cgUlptl}x#3|isl_calc_phys_level0_extent_sa%s/%s.foz%s/%s_idx.foz%s/%sMESA_LOGMESA_LOG_FILEerrorwarningdebuginvalid message formatno supported tiling../src/intel/isl/isl.c../src/intel/isl/isl_gfx8.cformat does not support msaa../src/intel/isl/isl_gfx7.c../src/intel/isl/isl_gfx6.ccalculated row pitch is zero%s/%c%c/%sMESA_SHADER_CACHE_DISABLEMESA_GLSL_CACHE_DISABLEmesa_shader_cache_sfmesa_shader_cachemesa_shader_cache_dbMESA_SHADER_CACHE_DIRMESA_GLSL_CACHE_DIRXDG_CACHE_HOME.cachefoz_cachea+bmesa_cache.db%s/part%ur+bmesa_cache.idx%s/markerMESA_SHADER_CACHE_SHOW_STATS%s/indexMESA_SHADER_CACHE_MAX_SIZEMESA_GLSL_CACHE_MAX_SIZEdisk$/dev/urandommake_check_uncompressed%s/%02lx%s.tmp%s/%c%csyslogandroidwindbgCannot use %s for shader cache (not a directory)---disabling. Failed to create %s for shader cache (%s)---disabling. msaa only supported on 2D surfacesmsaa not supported with LOD > 1cannot require array & interleaved msaa layouts%s:%s: compression block with depth > 1requested row pitch (%uB) less than minimum allowed (%uB)requested row pitch (%uB) doesn't satisfy the minimum alignment requirement (%uB)calculated size (%luB) exceeds platform limit of %luBrow pitch (%uB) not in range of 3DSTATE_STENCIL_BUFFER/3DSTATE_DEPTH_BUFFER::SurfacePitchrow pitch (%uB) not in range of 3DSTATE_HIER_DEPTH_BUFFER::SurfacePitchrow pitch (%uB) not in range of 3DSTATE_DEPTH_BUFFER::SurfacePitchrow_pitch_tl=%u not in range of RENDER_SURFACE_STATE::AuxiliarySurfacePitchrow pitch (%uB) not in range of RENDER_SURFACE_STATE::SurfacePitchmsaa requires vertical alignment of four, but format requires vertical alignment of twodisk shader cache: hits = %u, misses = %u *** MESA_GLSL_CACHE_DISABLE is deprecated; use MESA_SHADER_CACHE_DISABLE instead *** *** MESA_GLSL_CACHE_DIR is deprecated; use MESA_SHADER_CACHE_DIR instead *** MESA_DISK_CACHE_READ_ONLY_FOZ_DBSMESA_DISK_CACHE_READ_ONLY_FOZ_DBS_DYNAMIC_LISTMESA_DISK_CACHE_DATABASE_NUM_PARTS*** MESA_GLSL_CACHE_MAX_SIZE is deprecated; use MESA_SHADER_CACHE_MAX_SIZE instead *** MESA_DISK_CACHE_DATABASE_EVICTION_SCORE_2X_PERIODK9?.M;RNAvT>= ?Ga=G<~G|Gj"CEND OF FRAME %u ELAPSED: %lu ns %016lu %+9d: %s: %016lu %+9d: %s ]{ "frame": %u, "batches": [ { "events": [ ], "duration_ns": %lu { "event": "%s", "time_ns": "%016lu", "params": {} } ] } MESA_PROCESS_NAME/proc/self/exe/proc/meminfoMemAvailable:MemAvailable: %luEnable printMESA_GPU_TRACEShelp%s: help for %s: | %*s [0x%0*lx]%s%s MESA_GPU_TRACEFILE%s%ifalseyestrueGALLIUM_DUMP_CPUCPU <-> L3 cache mapping: - L3 %u mask = %08x GALLIUM_OVERRIDE_CPU_CAPSnossesse2ssse3sse4.1avxutil_cpu_caps.nr_cpus = %u util_cpu_caps.cacheline = %u util_cpu_caps.has_mmx = %u util_cpu_caps.has_mmx2 = %u util_cpu_caps.has_sse = %u util_cpu_caps.has_sse2 = %u util_cpu_caps.has_sse3 = %u util_cpu_caps.has_ssse3 = %u util_cpu_caps.has_avx = %u util_cpu_caps.has_avx2 = %u util_cpu_caps.has_f16c = %u util_cpu_caps.has_3dnow = %u util_cpu_caps.has_xop = %u util_cpu_caps.has_vsx = %u util_cpu_caps.has_neon = %u util_cpu_caps.has_msa = %u util_cpu_caps.has_daz = %u GALLIUM_NOSSEINTEL_DEBUGINTEL_SIMD_DEBUGINTEL_DEBUG_BATCH_FRAME_STARTINTEL_DEBUG_BATCH_FRAME_STOPMESA_DBfs8fs16fs32fs2x8fs4x8fs2x16cs8cs16cs32ts8ts16ts32ms8ms16ms32fallperfperfmonbatbufsubmitwmurbclipno16nodualobjoptimizerannno8no-oaconfigspill_fsspill_vec4hexnocompacthstcsdo32norbcnoccsnohizreemitsoft64btpcnofcno32shaderstaskcapture-allperf-symbol-namesswsb-stallheapsisldraw_bkpbat-statsprint_jsonEnable print in JSONmarkersEnable marker trace+----- NS -----+ +-- Δ --+ +----- MSG ----- /sys/devices/system/cpu/cpu%u/cpu_capacityCannot set thread affinity for any thread. util_cpu_caps.x86_cpu_type = %u util_cpu_caps.has_sse4_1 = %u util_cpu_caps.has_sse4_2 = %u util_cpu_caps.has_popcnt = %u util_cpu_caps.has_3dnow_ext = %u util_cpu_caps.has_altivec = %u util_cpu_caps.has_avx512f = %u util_cpu_caps.has_avx512dq = %u util_cpu_caps.has_avx512ifma = %u util_cpu_caps.has_avx512pf = %u util_cpu_caps.has_avx512er = %u util_cpu_caps.has_avx512cd = %u util_cpu_caps.has_avx512bw = %u util_cpu_caps.has_avx512vl = %u util_cpu_caps.has_avx512vbmi = %u util_cpu_caps.has_clflushopt = %u util_cpu_caps.num_L3_caches = %u util_cpu_caps.num_cpu_mask_bits = %u INTEL_DEBUG_BKP_BEFORE_DRAW_COUNTINTEL_DEBUG_BKP_AFTER_DRAW_COUNTg jgrn<:ORQhك[0w,aQ mjp5c飕d2yҗ+L |~-d jHqA}mQDžӃVlkdzbeO\lcc=  n;^iLA`rqgjm Zjz  ' }Dңhi]Wbgeq6lknv+ӉZzJgo߹ﾎCՎ`~ѡ8ROggW?K6H+ L J6`zA`Ugn1yiFafo%6hRw G "/&U;( Z+j\1е,[d&c윣ju m ?6grWJz+{8 Ғ |! ӆBhn[&wowGZpj;f\ eibkaElx TN³9a&g`MGiIwn>JjѮZf @;7SŞϲG0򽽊º0S$6к)WTg#.zfJah]+o*7 Z-debug_parse_flags_option0123456789abcdef X! (!pp @H @x $+<+T+l++++++++++++++++++++++++++++++++++++++++++++++++++ +....R.Z.}...---.-----..<-<-Unhandled Xe memory classKGBY@ @??Render Metrics Basic setRenderBasicCompute Metrics Basic setComputeBasicCompute Metrics Extended setComputeExtendedMemory Reads Distribution setMemoryReadsMemoryWritesMetric set SamplerBalanceRenderPipeProfileComputeL3CacheDataPortReadsCoalescingDataPortWritesCoalescingMetric set HDCAndSFMetric set L3_1Metric set L3_2Metric set L3_3Metric set L3_4RasterizerAndPixelBackendMetric set Sampler_1Metric set Sampler_2Metric set TDL_1Metric set TDL_2Compute Metrics Extra setComputeExtraMedia Vme Pipe metric setVMEPipeGpu Rings BusynessGpuBusynessMDAPI testing setMetric set PMA StallSTC_PmaStalla490e9d2-55b3-4db0-8dab-53011032c5f3b344c8cb-a291-4cbf-aa9c-b40213bfc96f480f9795-cf6a-4204-a9e3-cd7015515f8d399d3001-97d6-4240-b065-4fb843138e17Memory Writes Distribution setf3c1ff4b-d0da-4ffa-8780-2c6b98f3f2d5e111cda4-19c3-41ee-b326-f99ac44ebf78b541bd57-0e0f-4154-b4c0-5858010a2bf735fbc9b2-a891-40a6-a38d-022bb7057552Render Metrics for 3D Pipeline Profile233d0544-fff7-4281-8291-e02f222aff72Memory Reads Distribution metric set2b255d48-2117-4fef-a8f7-f151e1d25a2cMemory Writes Distribution metric setf7fd3220-b466-4a4d-9f98-b0caf3f2394cCompute Metrics Extended metric sete99ccaca-821c-4df9-97a7-96bdb7204e43Compute Metrics L3 Cache metric set27a364dc-8225-4ecb-b607-d6f1925598d9Data Port Reads Coalescing metric set857fc630-2f09-4804-85f1-084adfadd5abData Port Writes Coalescing metric set343ebc99-4a55-414c-8c17-d8e259cf5e2078490af2-10fa-430b-ae3c-94ec04d5214ec0abdd97-3b13-4cad-814c-bd178804e02cad665281-a7cf-483a-bd10-0e07c43f61c7930a15aa-4300-4fce-a9ba-edb0b9e880bed7793b26-b5e3-4f0f-ad78-7ebc9d0b4c7dMetric set RasterizerAndPixelBackendda0f7875-1143-4d73-a39c-9128a951c46a52c186e4-39e3-4534-87cd-41bd47763df9edcb8c31-764d-451a-9ecd-c9c89fb54f8d729fc3f4-ccff-4902-be6b-f1a22cc92c0229598975-4785-43ab-a981-1dfa58d0e8358fb61ba2-2fbb-454c-a136-2dec5a8a595ee1743ca0-7fc8-410b-a066-de7bbb9280b70a9eb7be-feee-4275-a139-6d9cedf0fdb0d6de6f55-e526-4f79-a6a6-d7315c09044ee713f347-953e-4d8c-b02f-6be31df2db2b9d8a3af5-c02c-4a4a-b947-f1672469e0fbf522a89c-ecd1-4522-8331-3383c54af5f5a9ccc03d-a943-4e6b-9cd6-13e06307592733af8252-7a51-4aa3-b0ba-1b946f209d7b78f52900-5317-4417-8067-966fbf215a1f0db4fe4a-2648-4064-bd6a-89c06d0c27b30de6539e-33b4-4aee-83c4-9ab45a579b94be74c9d6-268f-4d7f-b2e8-8d91d444188331bc1ff3-8d09-4497-9d79-59c4f943b50205450fec-bb5c-4b0a-8995-e03631168a34883c8a56-8767-4de8-beec-a99462c6674beb97e523-d9ac-48a9-b7f8-9cc909ddbf14dff6158e-8409-452c-be76-91c9946330bd4a534b07-cba3-414d-8d60-874830e883aaXPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@t??@t4\@= ???XZZ@Z@[ @ *@8 @9P994@@  @ @ @ P P   %*'*#@@   !*#T@@@@ @ @ @@S Ec G!1M?OEA@PXPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@? ?@ 4;> ??? YZZ@Z @  @9P994@@  @   @P P  %*'*#@@   !*#T@@@@ @ @ @@SEBG!1M?ODA@PXPXX XP\P\R0\TP@'D''' '$'0p'`t'x'|'''?'''`'''@;U<  9z9P  zB;;<@> ?@YZ  `9 99@9B B @  ( R#j%)' @@  !*#@@TU@@@@ @ @  DM=@OCQEDSG!1?@A@PXPXX XP\P\R0\TP@'D'''p '$'p't'x'0|'' '@ @ @P@  %@@@@   s @ ` @@s@@@s @   *'U# %@@@@ @ @  *# !P@@@@ @ @ @@S!G!1Md ?O A@PXPXX XP\P\R0\TP@'D'''p '$'p't'x'0|'' '@25RU\ @\\\== X @XXP[[[[@[  %88@8@8@8@8 8 9 9999 9::: s @ `  @0@1s2233@3455@P@QsRR SS@S T TUUU '*#%*# !P@@@@ @ @ @@S!G!1Md ?O A@PXPXX XP\P\R0\TP@'D''' '$'0p't'x'|'''''''''@`M`.5`MU\\@\== X[@[@[ [  @888@8@8 @8 999 9:: 033 4@4555SSTUU@  @T@@j @ p ŕ @  ŵ   %*'*#@ U !*#@TU@@@@ @ @  OB CQcESG!1M?BA@PXPXX XP\P\R0\TP@'D''' '$'0p't'x'|'''''''''@5U`.`M`.\\\ @\ ==XX@X @[X[ [@8@8U*8999 9 9:` @P344 55 5 5*ST U UU@@@ @@@@   ϕ ǵ `  ZU%'U#@@@@ @ @  !*#@TU@@@@ @ @  OCQESG!1M?b A@P@'D'''$' 'p't'x'|'''''''''''''@YY3f%@GW#Y@XPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@??@@? ??+?,?Z ZZZ@Z44 @ 8 P9 P9@9P99 9@:  @%'*# !*#T@@@@ @ @ @@SEG!1M?O`A@PXPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@@ +, @44 @  P P@P @   %*'U#@@@@@ @ @   !*#T@@@@ @ @ @@SEG!1M?O`A@PXPXX XP\P\R0\TP@'D''' '$'p't'@2\2X28222D`\K\\ XKX@[@[ `8K@8@8@88 8 999 9% % @%T   %*'*#T    !*#PU@@@@ @ @ @@@QCESb G!1MB?OA@PXPXPX$PX4P\DP\TP\dP$' '''p't'x'|''''z'''''''''_@YY&((''-') '+)@@"@:@$ 2 1@@ PP  !'UUUUACEGIKK(M*OQKSIU WY@XPXX Xw\x\\'' '$'@YYX.8.O5@=BX@X LXKXXXUUB8@8 L8K88DD8UU:UUt}|ACEG*I*K*M*OQSUY@XPXX XP\P\R0\TP@''' '$'@YYZ(,.1,1.+O5XZZ ZZU D89f:01 FD00111 F111D3  PU! /.-,Ut#}%PUPUPUA CE GIKMOQSUWY@XPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@? ?@ 4;> ??? YZZ@Z @  @9P994@@  @   @P P  %*'*#@@   !*#T@@@@ @ @ @@SEBG!1M?ODA@PXPXX XP\P\R0\TP@'D''' '$'0p'`t'x'|'''?'''`'''@;U<  9z9P  zB;;<@> ?@YZ  `9 99@9B B @  ( R#j%)' @@  !*#@@TU@@@@ @ @  DM=@OCQEDSG!1?@A@PXPXX XP\P\R0\TP@'D'''p '$'p't'x'0|'' '@ @ @P@  %@@@@   s @ ` @@s@@@s @   *'U# %@@@@ @ @  *# !P@@@@ @ @ @@S!G!1Md ?O A@PXPXX XP\P\R0\TP@'D'''p '$'p't'x'0|'' '@25RU\ @\\\== X @XXP[[[[@[  %88@8@8@8@8 8 9 9999 9::: s @ `  @0@1s2233@3455@P@QsRR SS@S T TUUU '*#%*# !P@@@@ @ @ @@S!G!1Md ?O A@PXPXX XP\P\R0\TP@'D''' '$'0p't'x'|'''''''''@`M`.5`MU\\@\== X[@[@[ [  @888@8@8 @8 999 9:: 033 4@4555SSTUU@  @T@@j @ p ŕ @  ŵ   %*'*#@ U !*#@TU@@@@ @ @  OB CQcESG!1M?BA@PXPXX XP\P\R0\TP@'D''' '$'0p't'x'|'''''''''@5U`.`M`.\\\ @\ ==XX@X @[X[ [@8@8U*8999 9 9:` @P344 55 5 5*ST U UU@@@ @@@@   ϕ ǵ `  ZU%'U#@@@@ @ @  !*#@TU@@@@ @ @  OCQESG!1M?b A@PXX0XPX\\Q \@'D''' '$'@5U\=@X@[[ @8@8 8 9 9: 3 455S @TUU@@ @@ Õ@ 5#%@@@ !@@@@ @ @ @@!M@ ?OA1@XPX@''' '$'0p'0t'x'|'''''''''?@X0X22@\\\\ \ ==(=@XXX@[@[[*[ *@8@8@8U8 9999 9 GQa@@0 00 1 Qa2 2*33* #PU%'!#@@T@ @M=OCQESG!1@@''' '$'p't'@p@$#%  !U@ @ @@@ppp$!M?OA1@@'D'''$' 'p't'x'|'''''''''''''@f%!@ @@!OA1@@''' '$'p't'@ J #P% !@@T@ @ @@M=OCQE!1@XPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@t??@t4\@= ???XZZ@Z@[ @ *@8 @9P994@@  @ @ @ P P   %*'*#@@   !*#T@@@@ @ @ @@S Ec G!1M?OEA@PXPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@??@@? ??+?,?Z ZZZ@Z44 @ 8 P9 P9@9P99 9@:  @%'*# !*#T@@@@ @ @ @@SEG!1M?O`A@PXPXX XP\P\R0\TP@'D''' '$'p'pt'x'@|''''@'''''?''''?@@@ +, @44 @  P P@P @   %*'U#@@@@@ @ @   !*#T@@@@ @ @ @@SEG!1M?O`A@PXPXX XP\P\R0\TP@'D''' '$'p't'@2\2X28222D`\K\\ XKX@[@[ `8K@8@8@88 8 999 9% % @%T   %*'*#T    !*#PU@@@@ @ @ @@@QCESb G!1MB?OA@PXPXX Xw\x\\$' '''L'H'D'w3@'p'rt'пx'b|'п'B'п''п''п''п''п''п@= =$=/X[\\\\ \@\\==== ==== B"XgXOXXXX j[@[@[T[A[@[[ @[  @8@8@88@8@8@8 @8 9999 9 99 cb#U%'*!(#@@TA@@@@ @ @  $ M=OCQE!1S G!?AA@XPXX Xw\x\\$' '''L'H'D'w3@'p't'x'|'''''''''߿''''@= $=/X U[\\\\ \ \@\\==== = ===B"XgXOXXXX X c[[@[@[U[@[[ @[  @8@8@8U8@8@8@8 @8 9999 9 9 99 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T!$T!T(T@đP@'D''' '$'@ddSkd{dqqPPP SSSUThPiPkPkkkxy{{{B{aa$T T(TJ@đP3D Pipe/Clipper3D Pipe/Domain Shader3D Pipe/Fragment Shader3D Pipe/Geometry Shader3D Pipe/Hull Shader3D Pipe/Input Assembler3D Pipe/Output Merger3D Pipe/Rasterizer3D Pipe/Rasterizer/Barycentric Calc3D Pipe/Rasterizer/Early Depth Test3D Pipe/Rasterizer/Hi-Depth Test3D Pipe/Rasterizer/Strip-Fans3D Pipe/Stream Output3D Pipe/Vertex ShaderAMFSColorPipeDataportDepthPipeEU ArrayEU Array/BarrierEU Array/Compute ShaderEU Array/Control ShaderEU Array/Domain ShaderEU Array/Evaluation ShaderEU Array/Fragment ShaderEU Array/Geometry ShaderEU Array/Hull ShaderEU Array/PipesEU Array/Pipes/InstructionsEU Array/Pixel ShaderEU Array/Vertex ShaderFrontEndGPUGPU/3D PipeGPU/3D Pipe/Strip-FansGPU/Data PortGPU/RasterizerGPU/Rasterizer/Early Depth TestGPU/SamplerGPU/Stencil CacheGPU/Thread DispatcherGTIGTI/3D PipeGTI/3D Pipe/Command StreamerGTI/3D Pipe/Resource StreamerGTI/3D Pipe/Stream OutputGTI/3D Pipe/Vertex FetchGTI/Color CacheGTI/Depth CacheGTI/L3GeometryL1CacheL3L3/Data PortL3/Data Port/AtomicsL3/Data Port/SLML3/ICL3/SamplerL3/TAGL3CacheLLCMediaMemoryRasterizerRayTracingSamplerSampler/Sampler CacheSampler/Sampler InputTestThreadDispatcherURBVME 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urationHsEmActiveHsEuActiveHsEuActivePerThreadHsEuStallHsEuStallPerThreadHsFpuActiveHsSendActiveHsStallHsThreadsICACHE_HIT_BANK0_XECORE0ICACHE_HIT_BANK0_XECORE1ICACHE_HIT_BANK0_XECORE10ICACHE_HIT_BANK0_XECORE11ICACHE_HIT_BANK0_XECORE12ICACHE_HIT_BANK0_XECORE13ICACHE_HIT_BANK0_XECORE14ICACHE_HIT_BANK0_XECORE15ICACHE_HIT_BANK0_XECORE16ICACHE_HIT_BANK0_XECORE17ICACHE_HIT_BANK0_XECORE18ICACHE_HIT_BANK0_XECORE19ICACHE_HIT_BANK0_XECORE2ICACHE_HIT_BANK0_XECORE20ICACHE_HIT_BANK0_XECORE21ICACHE_HIT_BANK0_XECORE22ICACHE_HIT_BANK0_XECORE23ICACHE_HIT_BANK0_XECORE24ICACHE_HIT_BANK0_XECORE25ICACHE_HIT_BANK0_XECORE26ICACHE_HIT_BANK0_XECORE27ICACHE_HIT_BANK0_XECORE28ICACHE_HIT_BANK0_XECORE29ICACHE_HIT_BANK0_XECORE3ICACHE_HIT_BANK0_XECORE30ICACHE_HIT_BANK0_XECORE31ICACHE_HIT_BANK0_XECORE4ICACHE_HIT_BANK0_XECORE5ICACHE_HIT_BANK0_XECORE6ICACHE_HIT_BANK0_XECORE7ICACHE_HIT_BANK0_XECORE8ICACHE_HIT_BANK0_XECORE9ICACHE_HIT_BANK1_XECORE0ICACHE_HIT_BANK1_XECORE1ICACHE_HIT_BANK1_XECORE10ICACHE_HIT_BANK1_XECORE11ICACHE_HIT_BANK1_XECORE12ICACHE_HIT_BANK1_XECORE13ICACHE_HIT_BANK1_XECORE14ICACHE_HIT_BANK1_XECORE15ICACHE_HIT_BANK1_XECORE16ICACHE_HIT_BANK1_XECORE17ICACHE_HIT_BANK1_XECORE18ICACHE_HIT_BANK1_XECORE19ICACHE_HIT_BANK1_XECORE2ICACHE_HIT_BANK1_XECORE20ICACHE_HIT_BANK1_XECORE21ICACHE_HIT_BANK1_XECORE22ICACHE_HIT_BANK1_XECORE23ICACHE_HIT_BANK1_XECORE24ICACHE_HIT_BANK1_XECORE25ICACHE_HIT_BANK1_XECORE26ICACHE_HIT_BANK1_XECORE27ICACHE_HIT_BANK1_XECORE28ICACHE_HIT_BANK1_XECORE29ICACHE_HIT_BANK1_XECORE3ICACHE_HIT_BANK1_XECORE30ICACHE_HIT_BANK1_XECORE31ICACHE_HIT_BANK1_XECORE4ICACHE_HIT_BANK1_XECORE5ICACHE_HIT_BANK1_XECORE6ICACHE_HIT_BANK1_XECORE7ICACHE_HIT_BANK1_XECORE8ICACHE_HIT_BANK1_XECORE9ICACHE_HIT_BANK2_XECORE0ICACHE_HIT_BANK2_XECORE1ICACHE_HIT_BANK2_XECORE10ICACHE_HIT_BANK2_XECORE11ICACHE_HIT_BANK2_XECORE12ICACHE_HIT_BANK2_XECORE13ICACHE_HIT_BANK2_XECORE14ICACHE_HIT_BANK2_XECORE15ICACHE_HIT_BANK2_XECORE16ICACHE_HIT_BANK2_XECORE17ICACHE_HIT_BANK2_XECORE18ICACHE_HIT_BANK2_XECORE19ICACHE_HIT_BANK2_XECORE2ICACHE_HIT_BANK2_XECORE20ICACHE_HIT_BANK2_XECORE21ICACHE_HIT_BANK2_XECORE22ICACHE_HIT_BANK2_XECORE23ICACHE_HIT_BANK2_XECORE24ICACHE_HIT_BANK2_XECORE25ICACHE_HIT_BANK2_XECORE26ICACHE_HIT_BANK2_XECORE27ICACHE_HIT_BANK2_XECORE28ICACHE_HIT_BANK2_XECORE29ICACHE_HIT_BANK2_XECORE3ICACHE_HIT_BANK2_XECORE30ICACHE_HIT_BANK2_XECORE31ICACHE_HIT_BANK2_XECORE4ICACHE_HIT_BANK2_XECORE5ICACHE_HIT_BANK2_XECORE6ICACHE_HIT_BANK2_XECORE7ICACHE_HIT_BANK2_XECORE8ICACHE_HIT_BANK2_XECORE9ICACHE_HIT_BANK3_XECORE0ICACHE_HIT_BANK3_XECORE1ICACHE_HIT_BANK3_XECORE10ICACHE_HIT_BANK3_XECORE11ICACHE_HIT_BANK3_XECORE12ICACHE_HIT_BANK3_XECORE13ICACHE_HIT_BANK3_XECORE14ICACHE_HIT_BANK3_XECORE15ICACHE_HIT_BANK3_XECORE16ICACHE_HIT_BANK3_XECORE17ICACHE_HIT_BANK3_XECORE18ICACHE_HIT_BANK3_XECORE19ICACHE_HIT_BANK3_XECORE2ICACHE_HIT_BANK3_XECORE20ICACHE_HIT_BANK3_XECORE21ICACHE_HIT_BANK3_XECORE22ICACHE_HIT_BANK3_XECORE23ICACHE_HIT_BANK3_XECORE24ICACHE_HIT_BANK3_XECORE25ICACHE_HIT_BANK3_XECORE26ICACHE_HIT_BANK3_XECORE27ICACHE_HIT_BANK3_XECORE28ICACHE_HIT_BANK3_XECORE29ICACHE_HIT_BANK3_XECORE3ICACHE_HIT_BANK3_XECORE30ICACHE_HIT_BANK3_XECORE31ICACHE_HIT_BANK3_XECORE4ICACHE_HIT_BANK3_XECORE5ICACHE_HIT_BANK3_XECORE6ICACHE_HIT_BANK3_XECORE7ICACHE_HIT_BANK3_XECORE8ICACHE_HIT_BANK3_XECORE9ICACHE_L3_HIT_L3BANK0ICACHE_L3_HIT_L3BANK1ICACHE_L3_HIT_L3BANK10ICACHE_L3_HIT_L3BANK11ICACHE_L3_HIT_L3BANK12ICACHE_L3_HIT_L3BANK13ICACHE_L3_HIT_L3BANK14ICACHE_L3_HIT_L3BANK15ICACHE_L3_HIT_L3BANK16ICACHE_L3_HIT_L3BANK17ICACHE_L3_HIT_L3BANK18ICACHE_L3_HIT_L3BANK19ICACHE_L3_HIT_L3BANK2ICACHE_L3_HIT_L3BANK20ICACHE_L3_HIT_L3BANK21ICACHE_L3_HIT_L3BANK22ICACHE_L3_HIT_L3BANK23ICACHE_L3_HIT_L3BANK24ICACHE_L3_HIT_L3BANK25ICACHE_L3_HIT_L3BANK26ICACHE_L3_HIT_L3BANK27ICACHE_L3_HIT_L3BANK28ICACHE_L3_HIT_L3BANK29ICACHE_L3_HIT_L3BANK3ICACHE_L3_HIT_L3BANK30ICACHE_L3_HIT_L3BANK31ICACHE_L3_HIT_L3BANK4ICACHE_L3_HIT_L3BANK5ICACHE_L3_HIT_L3BANK6ICACHE_L3_HIT_L3BANK7ICACHE_L3_HIT_L3BANK8ICACHE_L3_HIT_L3BANK9ICACHE_L3_READ_L3BANK0ICACHE_L3_READ_L3BANK1ICACHE_L3_READ_L3BANK10ICACHE_L3_READ_L3BANK11ICACHE_L3_READ_L3BANK12ICACHE_L3_READ_L3BANK13ICACHE_L3_READ_L3BANK14ICACHE_L3_READ_L3BANK15ICACHE_L3_READ_L3BANK16ICACHE_L3_READ_L3BANK17ICACHE_L3_READ_L3BANK18ICACHE_L3_READ_L3BANK19ICACHE_L3_READ_L3BANK2ICACHE_L3_READ_L3BANK20ICACHE_L3_READ_L3BANK21ICACHE_L3_READ_L3BANK22ICACHE_L3_READ_L3BANK23ICACHE_L3_READ_L3BANK24ICACHE_L3_READ_L3BANK25ICACHE_L3_READ_L3BANK26ICACHE_L3_READ_L3BANK27ICACHE_L3_READ_L3BANK28ICACHE_L3_READ_L3BANK29ICACHE_L3_READ_L3BANK3ICACHE_L3_READ_L3BANK30ICACHE_L3_READ_L3BANK31ICACHE_L3_READ_L3BANK4ICACHE_L3_READ_L3BANK5ICACHE_L3_READ_L3BANK6ICACHE_L3_READ_L3BANK7ICACHE_L3_READ_L3BANK8ICACHE_L3_READ_L3BANK9ICACHE_MISS_BANK0_XECORE0ICACHE_MISS_BANK0_XECORE1ICACHE_MISS_BANK0_XECORE10ICACHE_MISS_BANK0_XECORE11ICACHE_MISS_BANK0_XECORE12ICACHE_MISS_BANK0_XECORE13ICACHE_MISS_BANK0_XECORE14ICACHE_MISS_BANK0_XECORE15ICACHE_MISS_BANK0_XECORE16ICACHE_MISS_BANK0_XECORE17ICACHE_MISS_BANK0_XECORE18ICACHE_MISS_BANK0_XECORE19ICACHE_MISS_BANK0_XECORE2ICACHE_MISS_BANK0_XECORE20ICACHE_MISS_BANK0_XECORE21ICACHE_MISS_BANK0_XECORE22ICACHE_MISS_BANK0_XECORE23ICACHE_MISS_BANK0_XECORE24ICACHE_MISS_BANK0_XECORE25ICACHE_MISS_BANK0_XECORE26ICACHE_MISS_BANK0_XECORE27ICACHE_MISS_BANK0_XECORE28ICACHE_MISS_BANK0_XECORE29ICACHE_MISS_BANK0_XECORE3ICACHE_MISS_BANK0_XECORE30ICACHE_MISS_BANK0_XECORE31ICACHE_MISS_BANK0_XECORE4ICACHE_MISS_BANK0_XECORE5ICACHE_MISS_BANK0_XECORE6ICACHE_MISS_BANK0_XECORE7ICACHE_MISS_BANK0_XECORE8ICACHE_MISS_BANK0_XECORE9ICACHE_MISS_BANK1_XECORE0ICACHE_MISS_BANK1_XECORE1ICACHE_MISS_BANK1_XECORE10ICACHE_MISS_BANK1_XECORE11ICACHE_MISS_BANK1_XECORE12ICACHE_MISS_BANK1_XECORE13ICACHE_MISS_BANK1_XECORE14ICACHE_MISS_BANK1_XECORE15ICACHE_MISS_BANK1_XECORE16ICACHE_MISS_BANK1_XECORE17ICACHE_MISS_BANK1_XECORE18ICACHE_MISS_BANK1_XECORE19ICACHE_MISS_BANK1_XECORE2ICACHE_MISS_BANK1_XECORE20ICACHE_MISS_BANK1_XECORE21ICACHE_MISS_BANK1_XECORE22ICACHE_MISS_BANK1_XECORE23ICACHE_MISS_BANK1_XECORE24ICACHE_MISS_BANK1_XECORE25ICACHE_MISS_BANK1_XECORE26ICACHE_MISS_BANK1_XECORE27ICACHE_MISS_BANK1_XECORE28ICACHE_MISS_BANK1_XECORE29ICACHE_MISS_BANK1_XECORE3ICACHE_MISS_BANK1_XECORE30ICACHE_MISS_BANK1_XECORE31ICACHE_MISS_BANK1_XECORE4ICACHE_MISS_BANK1_XECORE5ICACHE_MISS_BANK1_XECORE6ICACHE_MISS_BANK1_XECORE7ICACHE_MISS_BANK1_XECORE8ICACHE_MISS_BANK1_XECORE9ICACHE_MISS_BANK2_XECORE0ICACHE_MISS_BANK2_XECORE1ICACHE_MISS_BANK2_XECORE10ICACHE_MISS_BANK2_XECORE11ICACHE_MISS_BANK2_XECORE12ICACHE_MISS_BANK2_XECORE13ICACHE_MISS_BANK2_XECORE14ICACHE_MISS_BANK2_XECORE15ICACHE_MISS_BANK2_XECORE16ICACHE_MISS_BANK2_XECORE17ICACHE_MISS_BANK2_XECORE18ICACHE_MISS_BANK2_XECORE19ICACHE_MISS_BANK2_XECORE2ICACHE_MISS_BANK2_XECORE20ICACHE_MISS_BANK2_XECORE21ICACHE_MISS_BANK2_XECORE22ICACHE_MISS_BANK2_XECORE23ICACHE_MISS_BANK2_XECORE24ICACHE_MISS_BANK2_XECORE25ICACHE_MISS_BANK2_XECORE26ICACHE_MISS_BANK2_XECORE27ICACHE_MISS_BANK2_XECORE28ICACHE_MISS_BANK2_XECORE29ICACHE_MISS_BANK2_XECORE3ICACHE_MISS_BANK2_XECORE30ICACHE_MISS_BANK2_XECORE31ICACHE_MISS_BANK2_XECORE4ICACHE_MISS_BANK2_XECORE5ICACHE_MISS_BANK2_XECORE6ICACHE_MISS_BANK2_XECORE7ICACHE_MISS_BANK2_XECORE8ICACHE_MISS_BANK2_XECORE9ICACHE_MISS_BANK3_XECORE0ICACHE_MISS_BANK3_XECORE1ICACHE_MISS_BANK3_XECORE10ICACHE_MISS_BANK3_XECORE11ICACHE_MISS_BANK3_XECORE12ICACHE_MISS_BANK3_XECORE13ICACHE_MISS_BANK3_XECORE14ICACHE_MISS_BANK3_XECORE15ICACHE_MISS_BANK3_XECORE16ICACHE_MISS_BANK3_XECORE17ICACHE_MISS_BANK3_XECORE18ICACHE_MISS_BANK3_XECORE19ICACHE_MISS_BANK3_XECORE2ICACHE_MISS_BANK3_XECORE20ICACHE_MISS_BANK3_XECORE21ICACHE_MISS_BANK3_XECORE22ICACHE_MISS_BANK3_XECORE23ICACHE_MISS_BANK3_XECORE24ICACHE_MISS_BANK3_XECORE25ICACHE_MISS_BANK3_XECORE26ICACHE_MISS_BANK3_XECORE27ICACHE_MISS_BANK3_XECORE28ICACHE_MISS_BANK3_XECORE29ICACHE_MISS_BANK3_XECORE3ICACHE_MISS_BANK3_XECORE30ICACHE_MISS_BANK3_XECORE31ICACHE_MISS_BANK3_XECORE4ICACHE_MISS_BANK3_XECORE5ICACHE_MISS_BANK3_XECORE6ICACHE_MISS_BANK3_XECORE7ICACHE_MISS_BANK3_XECORE8ICACHE_MISS_BANK3_XECORE9IZ_OUTPUT_READY_ZPIPE0IZ_OUTPUT_READY_ZPIPE1IZ_OUTPUT_READY_ZPIPE10IZ_OUTPUT_READY_ZPIPE11IZ_OUTPUT_READY_ZPIPE12IZ_OUTPUT_READY_ZPIPE13IZ_OUTPUT_READY_ZPIPE14IZ_OUTPUT_READY_ZPIPE15IZ_OUTPUT_READY_ZPIPE2IZ_OUTPUT_READY_ZPIPE3IZ_OUTPUT_READY_ZPIPE4IZ_OUTPUT_READY_ZPIPE5IZ_OUTPUT_READY_ZPIPE6IZ_OUTPUT_READY_ZPIPE7IZ_OUTPUT_READY_ZPIPE8IZ_OUTPUT_READY_ZPIPE9IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE10IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE11IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE12IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE13IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE14IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE15IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE4IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE5IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE6IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE7IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE8IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE9L30Bank0ActiveL30Bank0InputAvailableL30Bank0OutputReadyL30Bank0StalledL30Bank1ActiveL30Bank1InputAvailableL30Bank1OutputReadyL30Bank1StalledL30Bank2ActiveL30Bank2InputAvailableL30Bank2OutputReadyL30Bank2StalledL30Bank3ActiveL30Bank3InputAvailableL30Bank3OutputReadyL30Bank3StalledL30Bank4ActiveL30Bank4InputAvailableL30Bank4OutputReadyL30Bank4StalledL30Bank5ActiveL30Bank5InputAvailableL30Bank5OutputReadyL30Bank5StalledL30Bank6ActiveL30Bank6InputAvailableL30Bank6OutputReadyL30Bank7ActiveL30Bank7InputAvailableL30Bank7OutputReadyL31Bank0ActiveL31Bank0InputAvailableL31Bank0OutputReadyL31Bank0StalledL31Bank1ActiveL31Bank1InputAvailableL31Bank1OutputReadyL31Bank1StalledL31Bank2ActiveL31Bank2InputAvailableL31Bank2OutputReadyL31Bank2StalledL31Bank3ActiveL31Bank3InputAvailableL31Bank3OutputReadyL31Bank3StalledL31Bank4InputAvailableL31Bank4OutputReadyL31Bank5InputAvailableL31Bank5OutputReadyL31Bank6InputAvailableL31Bank6OutputReadyL31Bank7InputAvailableL31Bank7OutputReadyL32Bank0InputAvailableL32Bank0OutputReadyL32Bank1InputAvailableL32Bank1OutputReadyL32Bank2InputAvailableL32Bank2OutputReadyL32Bank3InputAvailableL32Bank3OutputReadyL32Bank4InputAvailableL32Bank4OutputReadyL32Bank5InputAvailableL32Bank5OutputReadyL32Bank6InputAvailableL32Bank6OutputReadyL32Bank7InputAvailableL32Bank7OutputReadyL33Bank0InputAvailableL33Bank0OutputReadyL33Bank1InputAvailableL33Bank1OutputReadyL33Bank2InputAvailableL33Bank2OutputReadyL33Bank3InputAvailableL33Bank3OutputReadyL33Bank4InputAvailableL33Bank4OutputReadyL33Bank5InputAvailableL33Bank5OutputReadyL33Bank6InputAvailableL33Bank6OutputReadyL33Bank7InputAvailableL33Bank7OutputReadyL3AccessesL3Bank00AccessesL3Bank00IcAccessesL3Bank00IcHitsL3Bank01AccessesL3Bank02AccessesL3Bank03AccessesL3Bank04AccessesL3Bank05AccessesL3Bank06AccessesL3Bank07AccessesL3Bank10AccessesL3Bank10IcAccessesL3Bank10IcHitsL3Bank11AccessesL3Bank12AccessesL3Bank13AccessesL3LookupsL3MissesL3SamplerThroughputL3ShaderThroughputL3TotalThroughputL3_ATOMIC_ACCESS_L3BANK0L3_ATOMIC_ACCESS_L3BANK1L3_ATOMIC_ACCESS_L3BANK10L3_ATOMIC_ACCESS_L3BANK11L3_ATOMIC_ACCESS_L3BANK12L3_ATOMIC_ACCESS_L3BANK13L3_ATOMIC_ACCESS_L3BANK14L3_ATOMIC_ACCESS_L3BANK15L3_ATOMIC_ACCESS_L3BANK16L3_ATOMIC_ACCESS_L3BANK17L3_ATOMIC_ACCESS_L3BANK18L3_ATOMIC_ACCESS_L3BANK19L3_ATOMIC_ACCESS_L3BANK2L3_ATOMIC_ACCESS_L3BANK20L3_ATOMIC_ACCESS_L3BANK21L3_ATOMIC_ACCESS_L3BANK22L3_ATOMIC_ACCESS_L3BANK23L3_ATOMIC_ACCESS_L3BANK24L3_ATOMIC_ACCESS_L3BANK25L3_ATOMIC_ACCESS_L3BANK26L3_ATOMIC_ACCESS_L3BANK27L3_ATOMIC_ACCESS_L3BANK28L3_ATOMIC_ACCESS_L3BANK29L3_ATOMIC_ACCESS_L3BANK3L3_ATOMIC_ACCESS_L3BANK30L3_ATOMIC_ACCESS_L3BANK31L3_ATOMIC_ACCESS_L3BANK4L3_ATOMIC_ACCESS_L3BANK5L3_ATOMIC_ACCESS_L3BANK6L3_ATOMIC_ACCESS_L3BANK7L3_ATOMIC_ACCESS_L3BANK8L3_ATOMIC_ACCESS_L3BANK9L3_BUSY_L3BANK0L3_BUSY_L3BANK1L3_BUSY_L3BANK10L3_BUSY_L3BANK11L3_BUSY_L3BANK12L3_BUSY_L3BANK13L3_BUSY_L3BANK14L3_BUSY_L3BANK15L3_BUSY_L3BANK16L3_BUSY_L3BANK17L3_BUSY_L3BANK18L3_BUSY_L3BANK19L3_BUSY_L3BANK2L3_BUSY_L3BANK20L3_BUSY_L3BANK21L3_BUSY_L3BANK22L3_BUSY_L3BANK23L3_BUSY_L3BANK24L3_BUSY_L3BANK25L3_BUSY_L3BANK26L3_BUSY_L3BANK27L3_BUSY_L3BANK28L3_BUSY_L3BANK29L3_BUSY_L3BANK3L3_BUSY_L3BANK30L3_BUSY_L3BANK31L3_BUSY_L3BANK4L3_BUSY_L3BANK5L3_BUSY_L3BANK6L3_BUSY_L3BANK7L3_BUSY_L3BANK8L3_BUSY_L3BANK9L3_BYTE_READL3_BYTE_WRITEL3_HIT_L3BANK0L3_HIT_L3BANK1L3_HIT_L3BANK10L3_HIT_L3BANK11L3_HIT_L3BANK12L3_HIT_L3BANK13L3_HIT_L3BANK14L3_HIT_L3BANK15L3_HIT_L3BANK16L3_HIT_L3BANK17L3_HIT_L3BANK18L3_HIT_L3BANK19L3_HIT_L3BANK2L3_HIT_L3BANK20L3_HIT_L3BANK21L3_HIT_L3BANK22L3_HIT_L3BANK23L3_HIT_L3BANK24L3_HIT_L3BANK25L3_HIT_L3BANK26L3_HIT_L3BANK27L3_HIT_L3BANK28L3_HIT_L3BANK29L3_HIT_L3BANK3L3_HIT_L3BANK30L3_HIT_L3BANK31L3_HIT_L3BANK4L3_HIT_L3BANK5L3_HIT_L3BANK6L3_HIT_L3BANK7L3_HIT_L3BANK8L3_HIT_L3BANK9L3_INPUT_AVAILABLE_L3BANK0L3_INPUT_AVAILABLE_L3BANK1L3_INPUT_AVAILABLE_L3BANK10L3_INPUT_AVAILABLE_L3BANK11L3_INPUT_AVAILABLE_L3BANK12L3_INPUT_AVAILABLE_L3BANK13L3_INPUT_AVAILABLE_L3BANK14L3_INPUT_AVAILABLE_L3BANK15L3_INPUT_AVAILABLE_L3BANK16L3_INPUT_AVAILABLE_L3BANK17L3_INPUT_AVAILABLE_L3BANK18L3_INPUT_AVAILABLE_L3BANK19L3_INPUT_AVAILABLE_L3BANK2L3_INPUT_AVAILABLE_L3BANK20L3_INPUT_AVAILABLE_L3BANK21L3_INPUT_AVAILABLE_L3BANK22L3_INPUT_AVAILABLE_L3BANK23L3_INPUT_AVAILABLE_L3BANK24L3_INPUT_AVAILABLE_L3BANK25L3_INPUT_AVAILABLE_L3BANK26L3_INPUT_AVAILABLE_L3BANK27L3_INPUT_AVAILABLE_L3BANK28L3_INPUT_AVAILABLE_L3BANK29L3_INPUT_AVAILABLE_L3BANK3L3_INPUT_AVAILABLE_L3BANK30L3_INPUT_AVAILABLE_L3BANK31L3_INPUT_AVAILABLE_L3BANK4L3_INPUT_AVAILABLE_L3BANK5L3_INPUT_AVAILABLE_L3BANK6L3_INPUT_AVAILABLE_L3BANK7L3_INPUT_AVAILABLE_L3BANK8L3_INPUT_AVAILABLE_L3BANK9L3_MISS_L3BANK0L3_MISS_L3BANK1L3_MISS_L3BANK10L3_MISS_L3BANK11L3_MISS_L3BANK12L3_MISS_L3BANK13L3_MISS_L3BANK14L3_MISS_L3BANK15L3_MISS_L3BANK16L3_MISS_L3BANK17L3_MISS_L3BANK18L3_MISS_L3BANK19L3_MISS_L3BANK2L3_MISS_L3BANK20L3_MISS_L3BANK21L3_MISS_L3BANK22L3_MISS_L3BANK23L3_MISS_L3BANK24L3_MISS_L3BANK25L3_MISS_L3BANK26L3_MISS_L3BANK27L3_MISS_L3BANK28L3_MISS_L3BANK29L3_MISS_L3BANK3L3_MISS_L3BANK30L3_MISS_L3BANK31L3_MISS_L3BANK4L3_MISS_L3BANK5L3_MISS_L3BANK6L3_MISS_L3BANK7L3_MISS_L3BANK8L3_MISS_L3BANK9L3_OUTPUT_READY_L3BANK0L3_OUTPUT_READY_L3BANK1L3_OUTPUT_READY_L3BANK10L3_OUTPUT_READY_L3BANK11L3_OUTPUT_READY_L3BANK12L3_OUTPUT_READY_L3BANK13L3_OUTPUT_READY_L3BANK14L3_OUTPUT_READY_L3BANK15L3_OUTPUT_READY_L3BANK16L3_OUTPUT_READY_L3BANK17L3_OUTPUT_READY_L3BANK18L3_OUTPUT_READY_L3BANK19L3_OUTPUT_READY_L3BANK2L3_OUTPUT_READY_L3BANK20L3_OUTPUT_READY_L3BANK21L3_OUTPUT_READY_L3BANK22L3_OUTPUT_READY_L3BANK23L3_OUTPUT_READY_L3BANK24L3_OUTPUT_READY_L3BANK25L3_OUTPUT_READY_L3BANK26L3_OUTPUT_READY_L3BANK27L3_OUTPUT_READY_L3BANK28L3_OUTPUT_READY_L3BANK29L3_OUTPUT_READY_L3BANK3L3_OUTPUT_READY_L3BANK30L3_OUTPUT_READY_L3BANK31L3_OUTPUT_READY_L3BANK4L3_OUTPUT_READY_L3BANK5L3_OUTPUT_READY_L3BANK6L3_OUTPUT_READY_L3BANK7L3_OUTPUT_READY_L3BANK8L3_OUTPUT_READY_L3BANK9L3_READ_L3BANK0L3_READ_L3BANK1L3_READ_L3BANK10L3_READ_L3BANK11L3_READ_L3BANK12L3_READ_L3BANK13L3_READ_L3BANK14L3_READ_L3BANK15L3_READ_L3BANK16L3_READ_L3BANK17L3_READ_L3BANK18L3_READ_L3BANK19L3_READ_L3BANK2L3_READ_L3BANK20L3_READ_L3BANK21L3_READ_L3BANK22L3_READ_L3BANK23L3_READ_L3BANK24L3_READ_L3BANK25L3_READ_L3BANK26L3_READ_L3BANK27L3_READ_L3BANK28L3_READ_L3BANK29L3_READ_L3BANK3L3_READ_L3BANK30L3_READ_L3BANK31L3_READ_L3BANK4L3_READ_L3BANK5L3_READ_L3BANK6L3_READ_L3BANK7L3_READ_L3BANK8L3_READ_L3BANK9L3_STALL_L3BANK0L3_STALL_L3BANK1L3_STALL_L3BANK10L3_STALL_L3BANK11L3_STALL_L3BANK12L3_STALL_L3BANK13L3_STALL_L3BANK14L3_STALL_L3BANK15L3_STALL_L3BANK16L3_STALL_L3BANK17L3_STALL_L3BANK18L3_STALL_L3BANK19L3_STALL_L3BANK2L3_STALL_L3BANK20L3_STALL_L3BANK21L3_STALL_L3BANK22L3_STALL_L3BANK23L3_STALL_L3BANK24L3_STALL_L3BANK25L3_STALL_L3BANK26L3_STALL_L3BANK27L3_STALL_L3BANK28L3_STALL_L3BANK29L3_STALL_L3BANK3L3_STALL_L3BANK30L3_STALL_L3BANK31L3_STALL_L3BANK4L3_STALL_L3BANK5L3_STALL_L3BANK6L3_STALL_L3BANK7L3_STALL_L3BANK8L3_STALL_L3BANK9L3_SUPERQ_FULL_L3BANK0L3_SUPERQ_FULL_L3BANK1L3_SUPERQ_FULL_L3BANK10L3_SUPERQ_FULL_L3BANK11L3_SUPERQ_FULL_L3BANK12L3_SUPERQ_FULL_L3BANK13L3_SUPERQ_FULL_L3BANK14L3_SUPERQ_FULL_L3BANK15L3_SUPERQ_FULL_L3BANK16L3_SUPERQ_FULL_L3BANK17L3_SUPERQ_FULL_L3BANK18L3_SUPERQ_FULL_L3BANK19L3_SUPERQ_FULL_L3BANK2L3_SUPERQ_FULL_L3BANK20L3_SUPERQ_FULL_L3BANK21L3_SUPERQ_FULL_L3BANK22L3_SUPERQ_FULL_L3BANK23L3_SUPERQ_FULL_L3BANK24L3_SUPERQ_FULL_L3BANK25L3_SUPERQ_FULL_L3BANK26L3_SUPERQ_FULL_L3BANK27L3_SUPERQ_FULL_L3BANK28L3_SUPERQ_FULL_L3BANK29L3_SUPERQ_FULL_L3BANK3L3_SUPERQ_FULL_L3BANK30L3_SUPERQ_FULL_L3BANK31L3_SUPERQ_FULL_L3BANK4L3_SUPERQ_FULL_L3BANK5L3_SUPERQ_FULL_L3BANK6L3_SUPERQ_FULL_L3BANK7L3_SUPERQ_FULL_L3BANK8L3_SUPERQ_FULL_L3BANK9L3_WRITE_L3BANK0L3_WRITE_L3BANK1L3_WRITE_L3BANK10L3_WRITE_L3BANK11L3_WRITE_L3BANK12L3_WRITE_L3BANK13L3_WRITE_L3BANK14L3_WRITE_L3BANK15L3_WRITE_L3BANK16L3_WRITE_L3BANK17L3_WRITE_L3BANK18L3_WRITE_L3BANK19L3_WRITE_L3BANK2L3_WRITE_L3BANK20L3_WRITE_L3BANK21L3_WRITE_L3BANK22L3_WRITE_L3BANK23L3_WRITE_L3BANK24L3_WRITE_L3BANK25L3_WRITE_L3BANK26L3_WRITE_L3BANK27L3_WRITE_L3BANK28L3_WRITE_L3BANK29L3_WRITE_L3BANK3L3_WRITE_L3BANK30L3_WRITE_L3BANK31L3_WRITE_L3BANK4L3_WRITE_L3BANK5L3_WRITE_L3BANK6L3_WRITE_L3BANK7L3_WRITE_L3BANK8L3_WRITE_L3BANK9LOAD_STORE_CACHE_ACCESS_XECORE0LOAD_STORE_CACHE_ACCESS_XECORE1LOAD_STORE_CACHE_ACCESS_XECORE10LOAD_STORE_CACHE_ACCESS_XECORE11LOAD_STORE_CACHE_ACCESS_XECORE12LOAD_STORE_CACHE_ACCESS_XECORE13LOAD_STORE_CACHE_ACCESS_XECORE14LOAD_STORE_CACHE_ACCESS_XECORE15LOAD_STORE_CACHE_ACCESS_XECORE16LOAD_STORE_CACHE_ACCESS_XECORE17LOAD_STORE_CACHE_ACCESS_XECORE18LOAD_STORE_CACHE_ACCESS_XECORE19LOAD_STORE_CACHE_ACCESS_XECORE2LOAD_STORE_CACHE_ACCESS_XECORE20LOAD_STORE_CACHE_ACCESS_XECORE21LOAD_STORE_CACHE_ACCESS_XECORE22LOAD_STORE_CACHE_ACCESS_XECORE23LOAD_STORE_CACHE_ACCESS_XECORE24LOAD_STORE_CACHE_ACCESS_XECORE25LOAD_STORE_CACHE_ACCESS_XECORE26LOAD_STORE_CACHE_ACCESS_XECORE27LOAD_STORE_CACHE_ACCESS_XECORE28LOAD_STORE_CACHE_ACCESS_XECORE29LOAD_STORE_CACHE_ACCESS_XECORE3LOAD_STORE_CACHE_ACCESS_XECORE30LOAD_STORE_CACHE_ACCESS_XECORE31LOAD_STORE_CACHE_ACCESS_XECORE4LOAD_STORE_CACHE_ACCESS_XECORE5LOAD_STORE_CACHE_ACCESS_XECORE6LOAD_STORE_CACHE_ACCESS_XECORE7LOAD_STORE_CACHE_ACCESS_XECORE8LOAD_STORE_CACHE_ACCESS_XECORE9LOAD_STORE_CACHE_BYTE_READLOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE4LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE5LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE6LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE7LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE4LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE5LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE6LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE7LOAD_STORE_CACHE_BYTE_WRITELOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE4LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE5LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE6LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE7LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE4LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE5LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE6LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE7LOAD_STORE_CACHE_HIT_XECORE0LOAD_STORE_CACHE_HIT_XECORE1LOAD_STORE_CACHE_HIT_XECORE10LOAD_STORE_CACHE_HIT_XECORE11LOAD_STORE_CACHE_HIT_XECORE12LOAD_STORE_CACHE_HIT_XECORE13LOAD_STORE_CACHE_HIT_XECORE14LOAD_STORE_CACHE_HIT_XECORE15LOAD_STORE_CACHE_HIT_XECORE16LOAD_STORE_CACHE_HIT_XECORE17LOAD_STORE_CACHE_HIT_XECORE18LOAD_STORE_CACHE_HIT_XECORE19LOAD_STORE_CACHE_HIT_XECORE2LOAD_STORE_CACHE_HIT_XECORE20LOAD_STORE_CACHE_HIT_XECORE21LOAD_STORE_CACHE_HIT_XECORE22LOAD_STORE_CACHE_HIT_XECORE23LOAD_STORE_CACHE_HIT_XECORE24LOAD_STORE_CACHE_HIT_XECORE25LOAD_STORE_CACHE_HIT_XECORE26LOAD_STORE_CACHE_HIT_XECORE27LOAD_STORE_CACHE_HIT_XECORE28LOAD_STORE_CACHE_HIT_XECORE29LOAD_STORE_CACHE_HIT_XECORE3LOAD_STORE_CACHE_HIT_XECORE30LOAD_STORE_CACHE_HIT_XECORE31LOAD_STORE_CACHE_HIT_XECORE4LOAD_STORE_CACHE_HIT_XECORE5LOAD_STORE_CACHE_HIT_XECORE6LOAD_STORE_CACHE_HIT_XECORE7LOAD_STORE_CACHE_HIT_XECORE8LOAD_STORE_CACHE_HIT_XECORE9LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE10LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE11LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE12LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE13LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE14LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE15LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE16LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE17LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE18LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE19LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE20LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE21LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE22LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE23LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE24LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE25LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE26LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE27LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE28LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE29LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE30LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE31LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE8LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE9LOAD_STORE_CACHE_L3_READ_XECORE0LOAD_STORE_CACHE_L3_READ_XECORE1LOAD_STORE_CACHE_L3_READ_XECORE10LOAD_STORE_CACHE_L3_READ_XECORE11LOAD_STORE_CACHE_L3_READ_XECORE12LOAD_STORE_CACHE_L3_READ_XECORE13LOAD_STORE_CACHE_L3_READ_XECORE14LOAD_STORE_CACHE_L3_READ_XECORE15LOAD_STORE_CACHE_L3_READ_XECORE16LOAD_STORE_CACHE_L3_READ_XECORE17LOAD_STORE_CACHE_L3_READ_XECORE18LOAD_STORE_CACHE_L3_READ_XECORE19LOAD_STORE_CACHE_L3_READ_XECORE2LOAD_STORE_CACHE_L3_READ_XECORE20LOAD_STORE_CACHE_L3_READ_XECORE21LOAD_STORE_CACHE_L3_READ_XECORE22LOAD_STORE_CACHE_L3_READ_XECORE23LOAD_STORE_CACHE_L3_READ_XECORE24LOAD_STORE_CACHE_L3_READ_XECORE25LOAD_STORE_CACHE_L3_READ_XECORE26LOAD_STORE_CACHE_L3_READ_XECORE27LOAD_STORE_CACHE_L3_READ_XECORE28LOAD_STORE_CACHE_L3_READ_XECORE29LOAD_STORE_CACHE_L3_READ_XECORE3LOAD_STORE_CACHE_L3_READ_XECORE30LOAD_STORE_CACHE_L3_READ_XECORE31LOAD_STORE_CACHE_L3_READ_XECORE4LOAD_STORE_CACHE_L3_READ_XECORE5LOAD_STORE_CACHE_L3_READ_XECORE6LOAD_STORE_CACHE_L3_READ_XECORE7LOAD_STORE_CACHE_L3_READ_XECORE8LOAD_STORE_CACHE_L3_READ_XECORE9LOAD_STORE_CACHE_L3_WRITE_XECORE0LOAD_STORE_CACHE_L3_WRITE_XECORE1LOAD_STORE_CACHE_L3_WRITE_XECORE10LOAD_STORE_CACHE_L3_WRITE_XECORE11LOAD_STORE_CACHE_L3_WRITE_XECORE12LOAD_STORE_CACHE_L3_WRITE_XECORE13LOAD_STORE_CACHE_L3_WRITE_XECORE14LOAD_STORE_CACHE_L3_WRITE_XECORE15LOAD_STORE_CACHE_L3_WRITE_XECORE16LOAD_STORE_CACHE_L3_WRITE_XECORE17LOAD_STORE_CACHE_L3_WRITE_XECORE18LOAD_STORE_CACHE_L3_WRITE_XECORE19LOAD_STORE_CACHE_L3_WRITE_XECORE2LOAD_STORE_CACHE_L3_WRITE_XECORE20LOAD_STORE_CACHE_L3_WRITE_XECORE21LOAD_STORE_CACHE_L3_WRITE_XECORE22LOAD_STORE_CACHE_L3_WRITE_XECORE23LOAD_STORE_CACHE_L3_WRITE_XECORE24LOAD_STORE_CACHE_L3_WRITE_XECORE25LOAD_STORE_CACHE_L3_WRITE_XECORE26LOAD_STORE_CACHE_L3_WRITE_XECORE27LOAD_STORE_CACHE_L3_WRITE_XECORE28LOAD_STORE_CACHE_L3_WRITE_XECORE29LOAD_STORE_CACHE_L3_WRITE_XECORE3LOAD_STORE_CACHE_L3_WRITE_XECORE30LOAD_STORE_CACHE_L3_WRITE_XECORE31LOAD_STORE_CACHE_L3_WRITE_XECORE4LOAD_STORE_CACHE_L3_WRITE_XECORE5LOAD_STORE_CACHE_L3_WRITE_XECORE6LOAD_STORE_CACHE_L3_WRITE_XECORE7LOAD_STORE_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EXTURE_CACHE_MISS_XECORE11SAMPLER_TEXTURE_CACHE_MISS_XECORE12SAMPLER_TEXTURE_CACHE_MISS_XECORE13SAMPLER_TEXTURE_CACHE_MISS_XECORE14SAMPLER_TEXTURE_CACHE_MISS_XECORE15SAMPLER_TEXTURE_CACHE_MISS_XECORE16SAMPLER_TEXTURE_CACHE_MISS_XECORE17SAMPLER_TEXTURE_CACHE_MISS_XECORE18SAMPLER_TEXTURE_CACHE_MISS_XECORE19SAMPLER_TEXTURE_CACHE_MISS_XECORE2SAMPLER_TEXTURE_CACHE_MISS_XECORE20SAMPLER_TEXTURE_CACHE_MISS_XECORE21SAMPLER_TEXTURE_CACHE_MISS_XECORE22SAMPLER_TEXTURE_CACHE_MISS_XECORE23SAMPLER_TEXTURE_CACHE_MISS_XECORE24SAMPLER_TEXTURE_CACHE_MISS_XECORE25SAMPLER_TEXTURE_CACHE_MISS_XECORE26SAMPLER_TEXTURE_CACHE_MISS_XECORE27SAMPLER_TEXTURE_CACHE_MISS_XECORE28SAMPLER_TEXTURE_CACHE_MISS_XECORE29SAMPLER_TEXTURE_CACHE_MISS_XECORE3SAMPLER_TEXTURE_CACHE_MISS_XECORE30SAMPLER_TEXTURE_CACHE_MISS_XECORE31SAMPLER_TEXTURE_CACHE_MISS_XECORE4SAMPLER_TEXTURE_CACHE_MISS_XECORE5SAMPLER_TEXTURE_CACHE_MISS_XECORE6SAMPLER_TEXTURE_CACHE_MISS_XECORE7SAMPLER_TEXTURE_CACHE_MISS_XECORE8SAMPLER_TEXTURE_CACHE_MISS_XECORE9SLM_ACCESS_COUNT_BANK0_XECORE0SLM_ACCESS_COUNT_BANK0_XECORE1SLM_ACCESS_COUNT_BANK0_XECORE2SLM_ACCESS_COUNT_BANK0_XECORE3SLM_ACCESS_COUNT_BANK0_XECORE4SLM_ACCESS_COUNT_BANK0_XECORE5SLM_ACCESS_COUNT_BANK0_XECORE6SLM_ACCESS_COUNT_BANK0_XECORE7SLM_ACCESS_COUNT_BANK1_XECORE0SLM_ACCESS_COUNT_BANK1_XECORE1SLM_ACCESS_COUNT_BANK1_XECORE2SLM_ACCESS_COUNT_BANK1_XECORE3SLM_ACCESS_COUNT_BANK1_XECORE4SLM_ACCESS_COUNT_BANK1_XECORE5SLM_ACCESS_COUNT_BANK1_XECORE6SLM_ACCESS_COUNT_BANK1_XECORE7SLM_ACCESS_COUNT_XECORE0SLM_ACCESS_COUNT_XECORE1SLM_ACCESS_COUNT_XECORE10SLM_ACCESS_COUNT_XECORE11SLM_ACCESS_COUNT_XECORE12SLM_ACCESS_COUNT_XECORE13SLM_ACCESS_COUNT_XECORE14SLM_ACCESS_COUNT_XECORE15SLM_ACCESS_COUNT_XECORE16SLM_ACCESS_COUNT_XECORE17SLM_ACCESS_COUNT_XECORE18SLM_ACCESS_COUNT_XECORE19SLM_ACCESS_COUNT_XECORE2SLM_ACCESS_COUNT_XECORE20SLM_ACCESS_COUNT_XECORE21SLM_ACCESS_COUNT_XECORE22SLM_ACCESS_COUNT_XECORE23SLM_ACCESS_COUNT_XECORE24SLM_ACCESS_COUNT_XECORE25SLM_ACCESS_COUNT_XECORE26SLM_ACCESS_COUNT_XECORE27SLM_ACCESS_COUNT_XECORE28SLM_ACCESS_COUNT_XECORE29SLM_ACCESS_COUNT_XECORE3SLM_ACCESS_COUNT_XECORE30SLM_ACCESS_COUNT_XECORE31SLM_ACCESS_COUNT_XECORE4SLM_ACCESS_COUNT_XECORE5SLM_ACCESS_COUNT_XECORE6SLM_ACCESS_COUNT_XECORE7SLM_ACCESS_COUNT_XECORE8SLM_ACCESS_COUNT_XECORE9SLM_BANK_CONFLICT_COUNTSLM_BANK_CONFLICT_COUNT_XECORE0SLM_BANK_CONFLICT_COUNT_XECORE1SLM_BANK_CONFLICT_COUNT_XECORE10SLM_BANK_CONFLICT_COUNT_XECORE11SLM_BANK_CONFLICT_COUNT_XECORE12SLM_BANK_CONFLICT_COUNT_XECORE13SLM_BANK_CONFLICT_COUNT_XECORE14SLM_BANK_CONFLICT_COUNT_XECORE15SLM_BANK_CONFLICT_COUNT_XECORE16SLM_BANK_CONFLICT_COUNT_XECORE17SLM_BANK_CONFLICT_COUNT_XECORE18SLM_BANK_CONFLICT_COUNT_XECORE19SLM_BANK_CONFLICT_COUNT_XECORE2SLM_BANK_CONFLICT_COUNT_XECORE20SLM_BANK_CONFLICT_COUNT_XECORE21SLM_BANK_CONFLICT_COUNT_XECORE22SLM_BANK_CONFLICT_COUNT_XECORE23SLM_BANK_CONFLICT_COUNT_XECORE24SLM_BANK_CONFLICT_COUNT_XECORE25SLM_BANK_CONFLICT_COUNT_XECORE26SLM_BANK_CONFLICT_COUNT_XECORE27SLM_BANK_CONFLICT_COUNT_XECORE28SLM_BANK_CONFLICT_COUNT_XECORE29SLM_BANK_CONFLICT_COUNT_XECORE3SLM_BANK_CONFLICT_COUNT_XECORE30SLM_BANK_CONFLICT_COUNT_XECORE31SLM_BANK_CONFLICT_COUNT_XECORE4SLM_BANK_CONFLICT_COUNT_XECORE5SLM_BANK_CONFLICT_COUNT_XECORE6SLM_BANK_CONFLICT_COUNT_XECORE7SLM_BANK_CONFLICT_COUNT_XECORE8SLM_BANK_CONFLICT_COUNT_XECORE9SLM_BYTE_READSLM_BYTE_READ_BANK0_XECORE0SLM_BYTE_READ_BANK0_XECORE1SLM_BYTE_READ_BANK0_XECORE2SLM_BYTE_READ_BANK0_XECORE3SLM_BYTE_READ_BANK0_XECORE4SLM_BYTE_READ_BANK0_XECORE5SLM_BYTE_READ_BANK0_XECORE6SLM_BYTE_READ_BANK0_XECORE7SLM_BYTE_READ_BANK1_XECORE0SLM_BYTE_READ_BANK1_XECORE1SLM_BYTE_READ_BANK1_XECORE2SLM_BYTE_READ_BANK1_XECORE3SLM_BYTE_READ_BANK1_XECORE4SLM_BYTE_READ_BANK1_XECORE5SLM_BYTE_READ_BANK1_XECORE6SLM_BYTE_READ_BANK1_XECORE7SLM_BYTE_READ_BANK2_XECORE0SLM_BYTE_READ_BANK2_XECORE1SLM_BYTE_READ_BANK2_XECORE2SLM_BYTE_READ_BANK2_XECORE3SLM_BYTE_READ_BANK2_XECORE4SLM_BYTE_READ_BANK2_XECORE5SLM_BYTE_READ_BANK2_XECORE6SLM_BYTE_READ_BANK2_XECORE7SLM_BYTE_READ_BANK3_XECORE0SLM_BYTE_READ_BANK3_XECORE1SLM_BYTE_READ_BANK3_XECORE2SLM_BYTE_READ_BANK3_XECORE3SLM_BYTE_READ_BANK3_XECORE4SLM_BYTE_READ_BANK3_XECORE5SLM_BYTE_READ_BANK3_XECORE6SLM_BYTE_READ_BANK3_XECORE7SLM_BYTE_WRITESLM_BYTE_WRITE_BANK0_XECORE0SLM_BYTE_WRITE_BANK0_XECORE1SLM_BYTE_WRITE_BANK0_XECORE2SLM_BYTE_WRITE_BANK0_XECORE3SLM_BYTE_WRITE_BANK0_XECORE4SLM_BYTE_WRITE_BANK0_XECORE5SLM_BYTE_WRITE_BANK0_XECORE6SLM_BYTE_WRITE_BANK0_XECORE7SLM_BYTE_WRITE_BANK1_XECORE0SLM_BYTE_WRITE_BANK1_XECORE1SLM_BYTE_WRITE_BANK1_XECORE2SLM_BYTE_WRITE_BANK1_XECORE3SLM_BYTE_WRITE_BANK1_XECORE4SLM_BYTE_WRITE_BANK1_XECORE5SLM_BYTE_WRITE_BANK1_XECORE6SLM_BYTE_WRITE_BANK1_XECORE7SLM_BYTE_WRITE_BANK2_XECORE0SLM_BYTE_WRITE_BANK2_XECORE1SLM_BYTE_WRITE_BANK2_XECORE2SLM_BYTE_WRITE_BANK2_XECORE3SLM_BYTE_WRITE_BANK2_XECORE4SLM_BYTE_WRITE_BANK2_XECORE5SLM_BYTE_WRITE_BANK2_XECORE6SLM_BYTE_WRITE_BANK2_XECORE7SLM_BYTE_WRITE_BANK3_XECORE0SLM_BYTE_WRITE_BANK3_XECORE1SLM_BYTE_WRITE_BANK3_XECORE2SLM_BYTE_WRITE_BANK3_XECORE3SLM_BYTE_WRITE_BANK3_XECORE4SLM_BYTE_WRITE_BANK3_XECORE5SLM_BYTE_WRITE_BANK3_XECORE6SLM_BYTE_WRITE_BANK3_XECORE7STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE2STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE3STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE4STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE5STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE6STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE7STRIPSFAN_OBJECTS_CULL_SLICE0STRIPSFAN_OBJECTS_CULL_SLICE1STRIPSFAN_OBJECTS_CULL_SLICE2STRIPSFAN_OBJECTS_CULL_SLICE3STRIPSFAN_OBJECTS_CULL_SLICE4STRIPSFAN_OBJECTS_CULL_SLICE5STRIPSFAN_OBJECTS_CULL_SLICE6STRIPSFAN_OBJECTS_CULL_SLICE7STRIPSFAN_OBJECT_COUNT_SLICE0STRIPSFAN_OBJECT_COUNT_SLICE1STRIPSFAN_OBJECT_COUNT_SLICE2STRIPSFAN_OBJECT_COUNT_SLICE3STRIPSFAN_OBJECT_COUNT_SLICE4STRIPSFAN_OBJECT_COUNT_SLICE5STRIPSFAN_OBJECT_COUNT_SLICE6STRIPSFAN_OBJECT_COUNT_SLICE7STRIPSFAN_OUTPUT_READY_SLICE0STRIPSFAN_OUTPUT_READY_SLICE1STRIPSFAN_OUTPUT_READY_SLICE2STRIPSFAN_OUTPUT_READY_SLICE3STRIPSFAN_OUTPUT_READY_SLICE4STRIPSFAN_OUTPUT_READY_SLICE5STRIPSFAN_OUTPUT_READY_SLICE6STRIPSFAN_OUTPUT_READY_SLICE7SYSMEM_BYTE_READSYSMEM_BYTE_WRITESYSMEM_TRANSACTION_READSYSMEM_TRANSACTION_WRITESampler00BottleneckSampler00BusySampler00InputAvailableSampler00OutputReadySampler01InputAvailableSampler01OutputReadySampler02InputAvailableSampler02OutputReadySampler03InputAvailableSampler03OutputReadySampler04InputAvailableSampler04OutputReadySampler05InputAvailableSampler05OutputReadySampler06InputAvailableSampler06OutputReadySampler07InputAvailableSampler07OutputReadySampler0BottleneckSampler0BusySampler0L2CacheMissesSampler0TexelsSampler10InputAvailableSampler10OutputReadySampler11InputAvailableSampler11OutputReadySampler12InputAvailableSampler12OutputReadySampler13InputAvailableSampler13OutputReadySampler1BottleneckSampler1BusySampler1L2CacheMissesSampler1TexelsSampler20BottleneckSampler20BusySampler20InputAvailableSampler20OutputReadySampler21InputAvailableSampler21OutputReadySampler22InputAvailableSampler22OutputReadySampler23InputAvailableSampler23OutputReadySampler2L2CacheMissesSampler30InputAvailableSampler30OutputReadySampler31InputAvailableSampler31OutputReadySampler32InputAvailableSampler32OutputReadySampler33InputAvailableSampler33OutputReadySampler3L2CacheMissesSampler40InputAvailableSampler40OutputReadySampler41InputAvailableSampler41OutputReadySampler42InputAvailableSampler42OutputReadySampler43InputAvailableSampler43OutputReadySampler50InputAvailableSampler50OutputReadySampler51InputAvailableSampler51OutputReadySampler52InputAvailableSampler52OutputReadySampler53InputAvailableSampler53OutputReadySampler60InputAvailableSampler60OutputReadySampler61InputAvailableSampler61OutputReadySampler62InputAvailableSampler62OutputReadySampler63InputAvailableSampler63OutputReadySampler70InputAvailableSampler70OutputReadySampler71InputAvailableSampler71OutputReadySampler72InputAvailableSampler72OutputReadySampler73InputAvailableSampler73OutputReadySamplerAccessesSamplerBottleneckSamplerL1MissesSamplerL2CacheMissesSamplerTexelMissesSamplerTexelsSamplersBusySamplesBlendedSamplesKilledInPsSamplesWrittenSendActiveSf0BottleneckSf0StallSf1BottleneckSf1StallSf2BottleneckSf2StallSf3BottleneckSf3StallSf4BottleneckSf4StallSf5BottleneckSf5StallSf6BottleneckSf6StallSf7BottleneckSf7StallSfBottleneckSfStallShaderAtomicsShaderBarriersShaderMemoryAccessesSlmBytesReadSlmBytesWrittenSlmReadsSlmWritesSo0BottleneckSo0StallSo1BottleneckSo1StallSo2BottleneckSo2StallSo3BottleneckSo3StallSo4BottleneckSo4StallSo5BottleneckSo5StallSo6BottleneckSo6StallSo7BottleneckSo7StallSoBottleneckSoStallStcPMAStallTASK_THREADGROUP_COUNT_XECORE0TASK_THREADGROUP_COUNT_XECORE1TASK_THREADGROUP_COUNT_XECORE10TASK_THREADGROUP_COUNT_XECORE11TASK_THREADGROUP_COUNT_XECORE12TASK_THREADGROUP_COUNT_XECORE13TASK_THREADGROUP_COUNT_XECORE14TASK_THREADGROUP_COUNT_XECORE15TASK_THREADGROUP_COUNT_XECORE16TASK_THREADGROUP_COUNT_XECORE17TASK_THREADGROUP_COUNT_XECORE18TASK_THREADGROUP_COUNT_XECORE19TASK_THREADGROUP_COUNT_XECORE2TASK_THREADGROUP_COUNT_XECORE20TASK_THREADGROUP_COUNT_XECORE21TASK_THREADGROUP_COUNT_XECORE22TASK_THREADGROUP_COUNT_XECORE23TASK_THREADGROUP_COUNT_XECORE24TASK_THREADGROUP_COUNT_XECORE25TASK_THREADGROUP_COUNT_XECORE26TASK_THREADGROUP_COUNT_XECORE27TASK_THREADGROUP_COUNT_XECORE28TASK_THREADGROUP_COUNT_XECORE29TASK_THREADGROUP_COUNT_XECORE3TASK_THREADGROUP_COUNT_XECORE30TASK_THREADGROUP_COUNT_XECORE31TASK_THREADGROUP_COUNT_XECORE4TASK_THREADGROUP_COUNT_XECORE5TASK_THREADGROUP_COUNT_XECORE6TASK_THREADGROUP_COUNT_XECORE7TASK_THREADGROUP_COUNT_XECORE8TASK_THREADGROUP_COUNT_XECORE9TASK_THREAD_EXIT_COUNT_XECORE0TASK_THREAD_EXIT_COUNT_XECORE1TASK_THREAD_EXIT_COUNT_XECORE10TASK_THREAD_EXIT_COUNT_XECORE11TASK_THREAD_EXIT_COUNT_XECORE12TASK_THREAD_EXIT_COUNT_XECORE13TASK_THREAD_EXIT_COUNT_XECORE14TASK_THREAD_EXIT_COUNT_XECORE15TASK_THREAD_EXIT_COUNT_XECORE16TASK_THREAD_EXIT_COUNT_XECORE17TASK_THREAD_EXIT_COUNT_XECORE18TASK_THREAD_EXIT_COUNT_XECORE19TASK_THREAD_EXIT_COUNT_XECORE2TASK_THREAD_EXIT_COUNT_XECORE20TASK_T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NCE_MESSAGE_COUNT_XECORE20XVE_SLM_FENCE_MESSAGE_COUNT_XECORE21XVE_SLM_FENCE_MESSAGE_COUNT_XECORE22XVE_SLM_FENCE_MESSAGE_COUNT_XECORE23XVE_SLM_FENCE_MESSAGE_COUNT_XECORE24XVE_SLM_FENCE_MESSAGE_COUNT_XECORE25XVE_SLM_FENCE_MESSAGE_COUNT_XECORE26XVE_SLM_FENCE_MESSAGE_COUNT_XECORE27XVE_SLM_FENCE_MESSAGE_COUNT_XECORE28XVE_SLM_FENCE_MESSAGE_COUNT_XECORE29XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3XVE_SLM_FENCE_MESSAGE_COUNT_XECORE30XVE_SLM_FENCE_MESSAGE_COUNT_XECORE31XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7XVE_SLM_FENCE_MESSAGE_COUNT_XECORE8XVE_SLM_FENCE_MESSAGE_COUNT_XECORE9XVE_SLM_READ_MESSAGE_COUNT_XECORE0XVE_SLM_READ_MESSAGE_COUNT_XECORE1XVE_SLM_READ_MESSAGE_COUNT_XECORE10XVE_SLM_READ_MESSAGE_COUNT_XECORE11XVE_SLM_READ_MESSAGE_COUNT_XECORE12XVE_SLM_READ_MESSAGE_COUNT_XECORE13XVE_SLM_READ_MESSAGE_COUNT_XECORE14XVE_SLM_READ_MESSAGE_COUNT_XECORE15XVE_SLM_READ_MESSAGE_COUNT_XECORE16XVE_SLM_READ_MESSAGE_COUNT_XECORE17XVE_SLM_READ_MESSAGE_COUNT_XECORE18XVE_SLM_READ_MESSAGE_COUNT_XECORE19XVE_SLM_READ_MESSAGE_COUNT_XECORE2XVE_SLM_READ_MESSAGE_COUNT_XECORE20XVE_SLM_READ_MESSAGE_COUNT_XECORE21XVE_SLM_READ_MESSAGE_COUNT_XECORE22XVE_SLM_READ_MESSAGE_COUNT_XECORE23XVE_SLM_READ_MESSAGE_COUNT_XECORE24XVE_SLM_READ_MESSAGE_COUNT_XECORE25XVE_SLM_READ_MESSAGE_COUNT_XECORE26XVE_SLM_READ_MESSAGE_COUNT_XECORE27XVE_SLM_READ_MESSAGE_COUNT_XECORE28XVE_SLM_READ_MESSAGE_COUNT_XECORE29XVE_SLM_READ_MESSAGE_COUNT_XECORE3XVE_SLM_READ_MESSAGE_COUNT_XECORE30XVE_SLM_READ_MESSAGE_COUNT_XECORE31XVE_SLM_READ_MESSAGE_COUNT_XECORE4XVE_SLM_READ_MESSAGE_COUNT_XECORE5XVE_SLM_READ_MESSAGE_COUNT_XECORE6XVE_SLM_READ_MESSAGE_COUNT_XECORE7XVE_SLM_READ_MESSAGE_COUNT_XECORE8XVE_SLM_READ_MESSAGE_COUNT_XECORE9XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1XVE_SLM_WRITE_MESSAGE_COUNT_XECORE10XVE_SLM_WRITE_MESSAGE_COUNT_XECORE11XVE_SLM_WRITE_MESSAGE_COUNT_XECORE12XVE_SLM_WRITE_MESSAGE_COUNT_XECORE13XVE_SLM_WRITE_MESSAGE_COUNT_XECORE14XVE_SLM_WRITE_MESSAGE_COUNT_XECORE15XVE_SLM_WRITE_MESSAGE_COUNT_XECORE16XVE_SLM_WRITE_MESSAGE_COUNT_XECORE17XVE_SLM_WRITE_MESSAGE_COUNT_XECORE18XVE_SLM_WRITE_MESSAGE_COUNT_XECORE19XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2XVE_SLM_WRITE_MESSAGE_COUNT_XECORE20XVE_SLM_WRITE_MESSAGE_COUNT_XECORE21XVE_SLM_WRITE_MESSAGE_COUNT_XECORE22XVE_SLM_WRITE_MESSAGE_COUNT_XECORE23XVE_SLM_WRITE_MESSAGE_COUNT_XECORE24XVE_SLM_WRITE_MESSAGE_COUNT_XECORE25XVE_SLM_WRITE_MESSAGE_COUNT_XECORE26XVE_SLM_WRITE_MESSAGE_COUNT_XECORE27XVE_SLM_WRITE_MESSAGE_COUNT_XECORE28XVE_SLM_WRITE_MESSAGE_COUNT_XECORE29XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3XVE_SLM_WRITE_MESSAGE_COUNT_XECORE30XVE_SLM_WRITE_MESSAGE_COUNT_XECORE31XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7XVE_SLM_WRITE_MESSAGE_COUNT_XECORE8XVE_SLM_WRITE_MESSAGE_COUNT_XECORE9XVE_STALLXVE_STALL_ALUWR_XECORE0_XVE0_THREAD0XVE_STALL_ALUWR_XECORE10_XVE0_THREAD0XVE_STALL_ALUWR_XECORE11_XVE0_THREAD0XVE_STALL_ALUWR_XECORE12_XVE0_THREAD0XVE_STALL_ALUWR_XECORE13_XVE0_THREAD0XVE_STALL_ALUWR_XECORE14_XVE0_THREAD0XVE_STALL_ALUWR_XECORE15_XVE0_THREAD0XVE_STALL_ALUWR_XECORE16_XVE0_THREAD0XVE_STALL_ALUWR_XECORE17_XVE0_THREAD0XVE_STALL_ALUWR_XECORE18_XVE0_THREAD0XVE_STALL_ALUWR_XECORE19_XVE0_THREAD0XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0XVE_STALL_ALUWR_XECORE20_XVE0_THREAD0XVE_STALL_ALUWR_XECORE21_XVE0_THREAD0XVE_STALL_ALUWR_XECORE22_XVE0_THREAD0XVE_STALL_ALUWR_XECORE23_XVE0_THREAD0XVE_STALL_ALUWR_XECORE24_XVE0_THREAD0XVE_STALL_ALUWR_XECORE25_XVE0_THREAD0XVE_STALL_ALUWR_XECORE26_XVE0_THREAD0XVE_STALL_ALUWR_XECORE27_XVE0_THREAD0XVE_STALL_ALUWR_XECORE28_XVE0_THREAD0XVE_STALL_ALUWR_XECORE29_XVE0_THREAD0XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0XVE_STALL_ALUWR_XECORE30_XVE0_THREAD0XVE_STALL_ALUWR_XECORE31_XVE0_THREAD0XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0XVE_STALL_ALUWR_XECORE8_XVE0_THREAD0XVE_STALL_ALUWR_XECORE9_XVE0_THREAD0XVE_STALL_ASYNC_CSXVE_STALL_BARRIER_XECORE0_XVE0_THREAD0XVE_STALL_BARRIER_XECORE10_XVE0_THREAD0XVE_STALL_BARRIER_XECORE11_XVE0_THREAD0XVE_STALL_BARRIER_XECORE12_XVE0_THREAD0XVE_STALL_BARRIER_XECORE13_XVE0_THREAD0XVE_STALL_BARRIER_XECORE14_XVE0_THREAD0XVE_STALL_BARRIER_XECORE15_XVE0_THREAD0XVE_STALL_BARRIER_XECORE16_XVE0_THREAD0XVE_STALL_BARRIER_XECORE17_XVE0_THREAD0XVE_STALL_BARRIER_XECORE18_XVE0_THREAD0XVE_STALL_BARRIER_XECORE19_XVE0_THREAD0XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0XVE_STALL_BARRIER_XECORE20_XVE0_THREAD0XVE_STALL_BARRIER_XECORE21_XVE0_THREAD0XVE_STALL_BARRIER_XECORE22_XVE0_THREAD0XVE_STALL_BARRIER_XECORE23_XVE0_THREAD0XVE_STALL_BARRIER_XECORE24_XVE0_THREAD0XVE_STALL_BARRIER_XECORE25_XVE0_THREAD0XVE_STALL_BARRIER_XECORE26_XVE0_THREAD0XVE_STALL_BARRIER_XECORE27_XVE0_THREAD0XVE_STALL_BARRIER_XECORE28_XVE0_THREAD0XVE_STALL_BARRIER_XECORE29_XVE0_THREAD0XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0XVE_STALL_BARRIER_XECORE30_XVE0_THREAD0XVE_STALL_BARRIER_XECORE31_XVE0_THREAD0XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0XVE_STALL_BARRIER_XECORE8_XVE0_THREAD0XVE_STALL_BARRIER_XECORE9_XVE0_THREAD0XVE_STALL_CONTROL_XECORE0_XVE0_THREAD0XVE_STALL_CONTROL_XECORE1_XVE0_THREAD0XVE_STALL_CONTROL_XECORE2_XVE0_THREAD0XVE_STALL_CONTROL_XECORE3_XVE0_THREAD0XVE_STALL_CONTROL_XECORE4_XVE0_THREAD0XVE_STALL_CONTROL_XECORE5_XVE0_THREAD0XVE_STALL_CONTROL_XECORE6_XVE0_THREAD0XVE_STALL_CONTROL_XECORE7_XVE0_THREAD0XVE_STALL_CSXVE_STALL_CYCLESXVE_STALL_CYCLES_ASYNC_CSXVE_STALL_CYCLES_CSXVE_STALL_CYCLES_DSXVE_STALL_CYCLES_GSXVE_STALL_CYCLES_HSXVE_STALL_CYCLES_MSXVE_STALL_CYCLES_PSXVE_STALL_CYCLES_RTXVE_STALL_CYCLES_TSXVE_STALL_CYCLES_VSXVE_STALL_DSXVE_STALL_GSXVE_STALL_HSXVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE10_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE11_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE12_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE13_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE14_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE15_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE16_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE17_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE18_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE19_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE20_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE21_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE22_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE23_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE24_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE25_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE26_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE27_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE28_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE29_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE30_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE31_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE8_XVE0_THREAD0XVE_STALL_INSTFETCH_XECORE9_XVE0_THREAD0XVE_STALL_MSXVE_STALL_OTHER_XECORE0_XVE0_THREAD0XVE_STALL_OTHER_XECORE10_XVE0_THREAD0XVE_STALL_OTHER_XECORE11_XVE0_THREAD0XVE_STALL_OTHER_XECORE12_XVE0_THREAD0XVE_STALL_OTHER_XECORE13_XVE0_THREAD0XVE_STALL_OTHER_XECORE14_XVE0_THREAD0XVE_STALL_OTHER_XECORE15_XVE0_THREAD0XVE_STALL_OTHER_XECORE16_XVE0_THREAD0XVE_STALL_OTHER_XECORE17_XVE0_THREAD0XVE_STALL_OTHER_XECORE18_XVE0_THREAD0XVE_STALL_OTHER_XECORE19_XVE0_THREAD0XVE_STALL_OTHER_XECORE1_XVE0_THREAD0XVE_STALL_OTHER_XECORE20_XVE0_THREAD0XVE_STALL_OTHER_XECORE21_XVE0_THREAD0XVE_STALL_OTHER_XECORE22_XVE0_THREAD0XVE_STALL_OTHER_XECORE23_XVE0_THREAD0XVE_STALL_OTHER_XECORE24_XVE0_THREAD0XVE_STALL_OTHER_XECORE25_XVE0_THREAD0XVE_STALL_OTHER_XECORE26_XVE0_THREAD0XVE_STALL_OTHER_XECORE27_XVE0_THREAD0XVE_STALL_OTHER_XECORE28_XVE0_THREAD0XVE_STALL_OTHER_XECORE29_XVE0_THREAD0XVE_STALL_OTHER_XECORE2_XVE0_THREAD0XVE_STALL_OTHER_XECORE30_XVE0_THREAD0XVE_STALL_OTHER_XECORE31_XVE0_THREAD0XVE_STALL_OTHER_XECORE3_XVE0_THREAD0XVE_STALL_OTHER_XECORE4_XVE0_THREAD0XVE_STALL_OTHER_XECORE5_XVE0_THREAD0XVE_STALL_OTHER_XECORE6_XVE0_THREAD0XVE_STALL_OTHER_XECORE7_XVE0_THREAD0XVE_STALL_OTHER_XECORE8_XVE0_THREAD0XVE_STALL_OTHER_XECORE9_XVE0_THREAD0XVE_STALL_PIPESTALL_XECORE0_XVE0XVE_STALL_PIPESTALL_XECORE1_XVE0XVE_STALL_PIPESTALL_XECORE2_XVE0XVE_STALL_PIPESTALL_XECORE3_XVE0XVE_STALL_PIPESTALL_XECORE4_XVE0XVE_STALL_PIPESTALL_XECORE5_XVE0XVE_STALL_PIPESTALL_XECORE6_XVE0XVE_STALL_PIPESTALL_XECORE7_XVE0XVE_STALL_PSXVE_STALL_RTXVE_STALL_SBID_XECORE0_XVE0_THREAD0XVE_STALL_SBID_XECORE10_XVE0_THREAD0XVE_STALL_SBID_XECORE11_XVE0_THREAD0XVE_STALL_SBID_XECORE12_XVE0_THREAD0XVE_STALL_SBID_XECORE13_XVE0_THREAD0XVE_STALL_SBID_XECORE14_XVE0_THREAD0XVE_STALL_SBID_XECORE15_XVE0_THREAD0XVE_STALL_SBID_XECORE16_XVE0_THREAD0XVE_STALL_SBID_XECORE17_XVE0_THREAD0XVE_STALL_SBID_XECORE18_XVE0_THREAD0XVE_STALL_SBID_XECORE19_XVE0_THREAD0XVE_STALL_SBID_XECORE1_XVE0_THREAD0XVE_STALL_SBID_XECORE20_XVE0_THREAD0XVE_STALL_SBID_XECORE21_XVE0_THREAD0XVE_STALL_SBID_XECORE22_XVE0_THREAD0XVE_STALL_SBID_XECORE23_XVE0_THREAD0XVE_STALL_SBID_XECORE24_XVE0_THREAD0XVE_STALL_SBID_XECORE25_XVE0_THREAD0XVE_STALL_SBID_XECORE26_XVE0_THREAD0XVE_STALL_SBID_XECORE27_XVE0_THREAD0XVE_STALL_SBID_XECORE28_XVE0_THREAD0XVE_STALL_SBID_XECORE29_XVE0_THREAD0XVE_STALL_SBID_XECORE2_XVE0_THREAD0XVE_STALL_SBID_XECORE30_XVE0_THREAD0XVE_STALL_SBID_XECORE31_XVE0_THREAD0XVE_STALL_SBID_XECORE3_XVE0_THREAD0XVE_STALL_SBID_XECORE4_XVE0_THREAD0XVE_STALL_SBID_XECORE5_XVE0_THREAD0XVE_STALL_SBID_XECORE6_XVE0_THREAD0XVE_STALL_SBID_XECORE7_XVE0_THREAD0XVE_STALL_SBID_XECORE8_XVE0_THREAD0XVE_STALL_SBID_XECORE9_XVE0_THREAD0XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0XVE_STALL_SENDWR_XECORE10_XVE0_THREAD0XVE_STALL_SENDWR_XECORE11_XVE0_THREAD0XVE_STALL_SENDWR_XECORE12_XVE0_THREAD0XVE_STALL_SENDWR_XECORE13_XVE0_THREAD0XVE_STALL_SENDWR_XECORE14_XVE0_THREAD0XVE_STALL_SENDWR_XECORE15_XVE0_THREAD0XVE_STALL_SENDWR_XECORE16_XVE0_THREAD0XVE_STALL_SENDWR_XECORE17_XVE0_THREAD0XVE_STALL_SENDWR_XECORE18_XVE0_THREAD0XVE_STALL_SENDWR_XECORE19_XVE0_THREAD0XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0XVE_STALL_SENDWR_XECORE20_XVE0_THREAD0XVE_STALL_SENDWR_XECORE21_XVE0_THREAD0XVE_STALL_SENDWR_XECORE22_XVE0_THREAD0XVE_STALL_SENDWR_XECORE23_XVE0_THREAD0XVE_STALL_SENDWR_XECORE24_XVE0_THREAD0XVE_STALL_SENDWR_XECORE25_XVE0_THREAD0XVE_STALL_SENDWR_XECORE26_XVE0_THREAD0XVE_STALL_SENDWR_XECORE27_XVE0_THREAD0XVE_STALL_SENDWR_XECORE28_XVE0_THREAD0XVE_STALL_SENDWR_XECORE29_XVE0_THREAD0XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0XVE_STALL_SENDWR_XECORE30_XVE0_THREAD0XVE_STALL_SENDWR_XECORE31_XVE0_THREAD0XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0XVE_STALL_SENDWR_XECORE8_XVE0_THREAD0XVE_STALL_SENDWR_XECORE9_XVE0_THREAD0XVE_STALL_TSXVE_STALL_VSXVE_THREADS_OCCUPANCY_ALLXVE_THREADS_OCCUPANCY_CYCLES_ALLXmxActiveXveActiveXveAvgIpcRateXveFpuEmActiveXveFpuFlt16XveFpuFlt32XveFpuFlt64XveFpuXmxActiveXveStallXveThreadOccupancyZ_L3_ACCESS_L3BANK0Z_L3_ACCESS_L3BANK1Z_L3_ACCESS_L3BANK2Z_L3_ACCESS_L3BANK3Z_L3_ACCESS_L3BANK4Z_L3_ACCESS_L3BANK5Z_L3_ACCESS_L3BANK6Z_L3_ACCESS_L3BANK7Z_L3_HIT_L3BANK0Z_L3_HIT_L3BANK1Z_L3_HIT_L3BANK10Z_L3_HIT_L3BANK11Z_L3_HIT_L3BANK12Z_L3_HIT_L3BANK13Z_L3_HIT_L3BANK14Z_L3_HIT_L3BANK15Z_L3_HIT_L3BANK16Z_L3_HIT_L3BANK17Z_L3_HIT_L3BANK18Z_L3_HIT_L3BANK19Z_L3_HIT_L3BANK2Z_L3_HIT_L3BANK20Z_L3_HIT_L3BANK21Z_L3_HIT_L3BANK22Z_L3_HIT_L3BANK23Z_L3_HIT_L3BANK24Z_L3_HIT_L3BANK25Z_L3_HIT_L3BANK26Z_L3_HIT_L3BANK27Z_L3_HIT_L3BANK28Z_L3_HIT_L3BANK29Z_L3_HIT_L3BANK3Z_L3_HIT_L3BANK30Z_L3_HIT_L3BANK31Z_L3_HIT_L3BANK4Z_L3_HIT_L3BANK5Z_L3_HIT_L3BANK6Z_L3_HIT_L3BANK7Z_L3_HIT_L3BANK8Z_L3_HIT_L3BANK9Any XVE thread loaded. Unit: events.Average EU bytes read per L3 cache line. Average EU bytes written per L3 cache line. Average GPU Core Frequency in the measurement. Unit: Hz.Coalescing ratio of EU read requests to L3 cache lines. Coalescing ratio of EU write requests to L3 cache lines. Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth Unit: gbps.Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth Unit: gbps.HW test counter 0. Factor: 0.0 Unit: events.HW test counter 1. Factor: 1.0 Unit: events.HW test counter 2. Factor: 1.0 Unit: events.HW test counter 3. Factor: 0.5 Unit: events.HW test counter 4. Factor: 0.333 Unit: events.HW test counter 4. Factor: 0.3333 Unit: events.HW test counter 5. Factor: 0.333 Unit: events.HW test counter 5. Factor: 0.3333 Unit: events.HW test counter 6. Factor: 0.166 Unit: events.HW test counter 6. Factor: 0.16666 Unit: events.HW test counter 7. Factor: 0.666 Unit: events.HW test counter 7. Factor: 0.6666 Unit: events.HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode Unit: events.HW test counter 8. Should be equal to 1. Unit: events.HW test counter 9. Should be equal to 1 in query. Unit: events.Number of 2x2 pixels written to all render targets Unit: pixels.Number of 2x2 texel block requested from Sampler Unit: texels.Number of 2x2 that were lit from Rasterizer but failed the depth stencil test or alpha test Unit: pixels.Number of AMFS accesses to L3 Unit: events.Number of AMFS atomics to L3 Unit: events.Number of AMFS writes to L3 Unit: events.Number of Async GPGPU EOT messages received Unit: events.Number of Async GPGPU threadgroups dispatched Unit: events.Number of BVH cache misses for RayQuery only Unit: events.Number of BVH nodes processed Unit: events.Number of Clipper early cull primitives Unit: events.Number of Clipper input vertices Unit: events.Number of DRAW and MESH commands parsed on the 3D engine Unit: events.Number of DS thread dispatches Unit: events.Number of GPGPU threadgroups dispatched Unit: events.Number of GS thread dispatches Unit: events.Number of GTI memory reads Unit: events.Number of GTI memory reads from L3 caused by L3 Cache misses Unit: events.Number of GTI memory writes Unit: events.Number of GTI memory writes from L3 caused by L3 invalidations Unit: events.Number of HS thread dispatches Unit: events.Number of Instruction Cache Hits Unit: events.Number of Instruction Cache Misses Unit: events.Number of L3 accesses which hits in the L3 cache Unit: events.Number of L3 accesses which miss in the L3 cache Unit: events.Number of L3 hit requests resulting from Sampler local cache miss which hits in L3 Unit: events.Number of L3 hit requests resulting from sampler local cache miss which hits in L3 Unit: events.Number of L3 hits for requests coming from the Dataport Unit: events.Number of L3 read requests Unit: events.Number of L3 read requests coming from XVE Instruction Cache Unit: events.Number of L3 read requests coming from XVE via Dataport Unit: events.Number of L3 read requests resulting from Sampler local cache miss Unit: events.Number of L3 read requests resulting from Z local cache miss Unit: events.Number of L3 read requests resulting from Z local cache miss which hits in L3 Unit: events.Number of L3 read requests resulting from color local cache miss which hits in L3 Unit: events.Number of L3 read requests resulting from sampler local cache miss Unit: events.Number of L3 request resulting from color local cache miss Unit: events.Number of L3 write requests Unit: events.Number of L3 write requests coming from XVE via Dataport Unit: events.Number of Load Store Cache accesses Unit: events.Number of Load Store Cache accesses. Unit: events.Number of Load Store Cache banks accessed in a clock. Unit: events.Number of Load Store Cache hits Unit: events.Number of Load Store Cache hits. Unit: events.Number of PS thread dispatches Unit: events.Number of Ray Tracing Traversal input rays Unit: events.Number of Ray Tracing Traversal output rays Unit: events.Number of Render Cache allocations - cache miss signal for new allocation Unit: events.Number of Render Cache allocations Unit: events.Number of Render Cache hits Unit: events.Number of Render Cache reads Unit: events.Number of Render Cache writes Unit: events.Number of SLM accesses Unit: events.Number of SLM accesses resulting in a bank conflict Unit: events.Number of SLM accesses resulting in a bank conflict. Unit: events.Number of SLM accesses. Unit: events.Number of SLM atomic operations sent by XVEs Unit: events.Number of SLM fence operations sent by XVEs Unit: events.Number of SLM read messages sent by XVEs Unit: events.Number of SLM write messages sent by XVEs Unit: events.Number of Sampler L1 misses Unit: events.Number of Sampler L1 requests Unit: events.Number of Shading Request (evaluate) messages processed by AMFS Unit: events.Number of Stalling flushes at the top of the pipe Unit: events.Number of Task Shader EOT messages received Unit: events.Number of Task Shader threadgroups dispatched Unit: events.Number of URB reads Unit: events.Number of URB reads occurred from cross slices Unit: events.Number of URB writes Unit: events.Number of VS thread dispatches Unit: events.Number of XVE instruction cache requests that hit the L3 Unit: events.Number of any hit threads dispatched for RayQuery only Unit: events.Number of atomic accesses to L3 Bank Unit: events.Number of atomic accesses to L3 bank Unit: events.Number of atomic messages sent by XVEs to the Dataport Unit: events.Number of atomic operations sent by XVEs to the Load Store Cache Unit: events.Number of blended 2x2 pixels written to all render targets Unit: pixels.Number of bytes read by host from GPU local (HBM) memory (downstream) Unit: bytes.Number of bytes read from L3 Unit: bytes.Number of bytes read from SLM Unit: bytes.Number of bytes read out of the Load Store Cache, excluding SLM accesses. Unit: bytes.Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES Unit: bytes.Number of bytes read through the Dataport Unit: bytes.Number of bytes read through the Dataport Unit: events.Number of bytes written by host to GPU local (HBM) memory (downstream) Unit: bytes.Number of bytes written through the Dataport Unit: bytes.Number of bytes written to L3 Unit: bytes.Number of bytes written to SLM Unit: bytes.Number of bytes written to the Load Store Cache, excluding SLM accesses. Unit: bytes.Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES Unit: bytes.Number of cache misses in AMFS Unit: events.Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit Unit: events.Number of cache requests from the Dataport to the texture cache that resulted in a cache hit Unit: events.Number of cacheline read requests from the Load Store Cache to L3 Unit: events.Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses Unit: events.Number of cacheline requests from the Dataport to the texture cache not including uncached accesses Unit: events.Number of cacheline write requests from the Load Store Cache to L3 Unit: events.Number of callable threads dispatched for RayQuery only Unit: events.Number of clocks spent dispatching GPGPU threads to XVEs Unit: events.Number of closest hit threads dispatched for RayQuery only Unit: events.Number of compute shader hardware threads dispatched Unit: threads.Number of compute walker commands parsed on the 3D engine Unit: events.Number of compute walker commands parsed on the compute engine Unit: events.Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction Unit: events.Number of cycles any threads are loaded but not even a single pipe is active in XVE Unit: events.Number of cycles at least one pipe is active in XVE Unit: events.Number of cycles at least one pipe is active in XVE and there are Async Compute Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Domain Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Fragment Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Geometry Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Hull Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Mesh Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Task Shader threads loaded Unit: events.Number of cycles at least one pipe is active in XVE and there are Vertex Shader threads loaded Unit: events.Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction Unit: events.Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes Unit: bytes.Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B) Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B) Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes Unit: bytes.Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B) Unit: events.Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B) Unit: events.Number of elements pushed by Clipper into Stripsfan stage Unit: events.Number of execution slots taken by BF16 XMX instructions Unit: events.Number of execution slots taken by FP16 ALU instructions Unit: events.Number of execution slots taken by FP16 XMX instructions Unit: events.Number of execution slots taken by FP32 ALU instructions Unit: events.Number of execution slots taken by INT16 ALU instructions Unit: events.Number of execution slots taken by INT32 ALU instructions Unit: events.Number of execution slots taken by INT8 XMX instructions Unit: events.Number of execution slots taken by extended math instructions Unit: events.Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe Unit: events.Number of execution slots taken by instructions executed in XMX pipe Unit: events.Number of execution slots taken by instructions executed on ALU0 pipe Unit: events.Number of execution slots taken by instructions executed on ALU1 pipe Unit: events.Number of fence messages sent by XVEs to the Dataport Unit: events.Number of fence messages sent by XVEs to the Load Store Cache Unit: events.Number of hits in the AMFS cache Unit: events.Number of host reads to GPU local (HBM) memory (downstream) Unit: events.Number of host writes to GPU local (HBM) memory (downstream) Unit: events.Number of instance BVH nodes processed by the traversal function Unit: events.Number of instructions executed by Async Compute Shader threads on SEND pipe Unit: events.Number of instructions executed by BTD Any Hit Shader threads on SEND pipe Unit: events.Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe Unit: events.Number of instructions executed by BTD Miss Shader threads on SEND pipe Unit: events.Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe Unit: events.Number of instructions executed by Domain Shader threads on SEND pipe Unit: events.Number of instructions executed by Fragment Shader threads on SEND pipe Unit: events.Number of instructions executed by Geometry Shader threads on SEND pipe Unit: events.Number of instructions executed by Hull Shader threads on SEND pipe Unit: events.Number of instructions executed by Mesh Shader threads on SEND pipe Unit: events.Number of instructions executed by Task Shader threads on SEND pipe Unit: events.Number of instructions executed by Vertex Shader threads on SEND pipe Unit: events.Number of instructions executed on Jump Pipe Unit: events.Number of instructions executed on SEND pipe Unit: events.Number of instructions issued (decoded) to any pipe Unit: events.Number of internal BVH nodes processed by the traversal function Unit: events.Number of intersection threads dispatched for RayQuery only Unit: events.Number of lit samples emitted by Rasterizer Unit: pixels.Number of message payload transactions sent by XVEs to the Load Store Cache Unit: events.Number of message payload transactions sent from XVEs to the Dataport Unit: events.Number of message payload transactions sent from the Load Store Cache back to XVEs Unit: events.Number of miss threads dispatched for RayQuery only Unit: events.Number of nodes processed that use ray-quad intersection pipeline Unit: events.Number of non-promoted 2x2 that are ambiguous by hierarchical depth test Unit: bytes.Number of non-promoted 2x2 that are lit from Rasterizer Unit: events.Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ Unit: events.Number of non-promoted 2x2 that failed the hierarchical depth test Unit: bytes.Number of objects exiting Stripsfan stage Unit: events.Number of only HW transform accesses Unit: events.Number of primitives clipped by Clipper due to near/far planes Unit: events.Number of primitives going out of Clipper, must clip plus the trivial accept Unit: events.Number of procedural BVH nodes processed by the traversal function Unit: events.Number of promoted 2x2 passed by hierarchical depth test Unit: bytes.Number of promoted 2x2 that are ambiguous by hierarchical depth test Unit: bytes.Number of promoted 2x2 that are lit from Rasterizer Unit: events.Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ Unit: events.Number of promoted 2x2 that failed the hierarchical depth test Unit: bytes.Number of read messages sent by XVEs to the Dataport Unit: events.Number of read messages sent by XVEs to the Load Store Cache Unit: events.Number of read messages sent from Ray Tracing unit to the Load Store Cache Unit: events.Number of return message payload transactions sent from the Dataport to XVEs Unit: events.Number of sampler L2 cache misses (ss0) Unit: messages.Number of sampler L2 cache misses (ss1) Unit: messages.Number of sampler L2 cache misses (ss2) Unit: messages.Number of sampler L2 cache misses (ss3) Unit: messages.Number of sampler L2 cache misses Unit: messages.Number of shader atomic memory accesses Unit: messages.Number of shader barrier messages Unit: messages.Number of simple culled objects in Stripsfan stage Unit: events.Number of system memory bytes read (upstream) Unit: bytes.Number of system memory bytes written (upstream) Unit: bytes.Number of system memory reads (upstream) Unit: events.Number of system memory writes (upstream) Unit: events.Number of thread slots occupied Unit: events.Number of transactions pushed from Rasterizer to the Z pipe Unit: events.Number of triangle BVH nodes processed by the traversal function Unit: events.Number of valid SIMD lanes in the TraceRay message Unit: events.Number of vertices written by SOL Unit: events.Number of write messages sent by XVEs to the Dataport Unit: events.Number of write messages sent by XVEs to the Load Store Cache Unit: events.Number of write messages sent from Ray Tracing unit to the Load Store Cache Unit: events.Number of writes to the Load Store Cache that don't fill a subsector Unit: events.Percentage of execution slots taken by BF16 XMX instructions Unit: percent.Percentage of execution slots taken by FP16 ALU instructions Unit: percent.Percentage of execution slots taken by FP16 XMX instructions Unit: percent.Percentage of execution slots taken by FP32 ALU instructions Unit: percent.Percentage of execution slots taken by INT16 ALU instructions Unit: percent.Percentage of execution slots taken by INT32 ALU instructions Unit: percent.Percentage of execution slots taken by INT8 XMX instructions Unit: percent.Percentage of execution slots taken by extended math instructions Unit: percent.Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe Unit: percent.Percentage of execution slots taken by instructions executed in XMX pipe Unit: percent.Percentage of execution slots taken by instructions executed on ALU0 pipe Unit: percent.Percentage of execution slots taken by instructions executed on ALU1 pipe Unit: percent.Percentage of thread slots occupied Unit: percent.Percentage of time in which Ray Tracing Leaf has two Traversal inputs valid Unit: events.Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction Unit: percent.Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction Unit: percent.Percentage of time in which AMFS stalls at any of the color pipe inputs Unit: percent.Percentage of time in which AMFS stalls at both of the color pipe inputs Unit: percent.Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core Unit: percent.Percentage of time in which Clipper has input available (from Vertex Shader or SOL) Unit: percent.Percentage of time in which Clipper output ready Unit: percent.Percentage of time in which Color Pipeline input ready Unit: percent.Percentage of time in which Color Pipeline pixel output ready Unit: percent.Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full Unit: percent.Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full Unit: percent.Percentage of time in which HiZ latency hiding structure full Unit: percent.Percentage of time in which IZ has requests to different clients Unit: percent.Percentage of time in which IZ latency hiding structure full Unit: percent.Percentage of time in which L3 Bank Stalled Unit: percent.Percentage of time in which L3 Bank has input requests Unit: percent.Percentage of time in which L3 Bank has output ready Unit: percent.Percentage of time in which L3 bank has input requests Unit: percent.Percentage of time in which L3 bank has output ready Unit: percent.Percentage of time in which L3 bank stalled Unit: percent.Percentage of time in which L3 request queue has one or more requests pending Unit: percent.Percentage of time in which Pixel Shader data is available Unit: percent.Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core Unit: percent.Percentage of time in which Rasterizer input is available Unit: percent.Percentage of time in which Rasterizer output is ready Unit: percent.Percentage of time in which Ray Tracing message input is stalled while accepting input Unit: percent.Percentage of time in which RayTracing Leaf has two Traversal inputs valid Unit: events.Percentage of time in which SQ is filled above a threshold (usually 48 entries) Unit: percent.Percentage of time in which Sampler input is available Unit: percent.Percentage of time in which Sampler output is ready Unit: percent.Percentage of time in which Sampler pipeline active Unit: percent.Percentage of time in which Sampler stalled due to latency hiding structure full Unit: percent.Percentage of time in which Thread Dispatch input is available Unit: percent.Percentage of time in which Thread Dispatch is stalled waiting for threads to be available Unit: percent.Percentage of time in which Thread Spawner has input available on queue 0 Unit: percent.Percentage of time in which Thread Spawner has input available on queue 1 Unit: percent.Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack) Unit: percent.Percentage of time in which Vertex Fetch input is available Unit: percent.Percentage of time in which Vertex Fetch output is ready Unit: percent.Percentage of time in which Vertex Shader output is ready Unit: percent.Percentage of time in which XVE requests stalled by Shared Function units Unit: percent.Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available Unit: percent.Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc) Unit: percent.Percentage of time in which XVEs have requests to the Dataport Unit: percent.Percentage of time in which all slots in L3 request queue are waiting for data return / response Unit: percent.Percentage of time in which any threads are loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which at least one pipe is active in XVE Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Async Compute Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Domain Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Fragment Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Geometry Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Hull Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Mesh Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Task Shader threads loaded Unit: percent.Percentage of time in which at least one pipe is active in XVE and there are Vertex Shader threads loaded Unit: percent.Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes Unit: percent.Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active Unit: percent.Percentage of time in which in which geometry pipeline output is ready Unit: percent.Percentage of time in which new message is accepted by Ray Tracing Frontend Unit: percent.Percentage of time in which non PS thread is ready for dispatch on thread dispatcher Unit: percent.Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core Unit: percent.Percentage of time in which the Dataport has data to return to XVEs Unit: percent.Percentage of time in which the Load Store Cache has input available Unit: percent.Percentage of time in which the Load Store Cache has output ready Unit: percent.Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE Unit: percent.Percentage of time in which there is a context loaded and active on the 3D queue Unit: percent.Percentage of time in which there is a context loaded and active on the compute queue Unit: percent.Percentage of time in which there is a context loaded and active on the copy queue Unit: percent.Percentage of time in which there is a context loaded and active on the copy queue. Unit: percent.Percentage of time in which there is a context loaded and active on the media queue Unit: percent.Percentage of time in which there is a context loaded and active on the video enhancement queue Unit: percent.Percentage of time spent dispatching GPGPU threads to XVEs Unit: events.Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Task Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe Unit: percent.Percentage of time taken by instructions executed on Jump Pipe Unit: percent.Percentage of time taken by instructions executed on SEND pipe Unit: percent.Percentage of time when the data at Pixel Backend output is ready Unit: percent.Percentage of time when the data is available at input of Pixel Backend Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice4) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice5) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice group 3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice4 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice5 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice6 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core2) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice7 Xe Core3) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss0) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss1) Unit: percent.Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (s0.ss2) Unit: percent.Percentage of time when Render Cache input is available Unit: percent.Percentage of time when Render Cache output is ready Unit: percent.Percentage of time when render cache input is available Unit: percent.Percentage of time when render cache output is ready Unit: percent.Percentage of time when stencil cache line and an overlapping pixel are causing stalls Unit: percent.Ratio of EU typed atomics requests to L3 cache line writes. Ratio of EU typed read requests to L3 cache line reads. Ratio of EU typed write requests to L3 cache line writes. Ratio of EU untyped read requests to L3 cache line reads. Ratio of EU untyped write requests to L3 cache line writes. Slice 0 Dualsubslice 0 typed atomics. Unit: messages.Slice 0 Dualsubslice 0 typed reads. Unit: messages.Slice 0 Dualsubslice 0 typed writes. Unit: messages.Slice 0 Dualsubslice 0 untyped reads (including SLM reads). Unit: messages.Slice 0 Dualsubslice 0 untyped writes (including SLM writes). Unit: messages.Slice 0 Subslice group 0 typed atomics. Unit: messages.Slice 0 Subslice group 0 typed reads. Unit: messages.Slice 0 Subslice group 0 typed writes. Unit: messages.Slice 0 Subslice group 0 untyped reads (including SLM reads). Unit: messages.Slice 0 Subslice group 0 untyped writes (including SLM writes). Unit: messages.Slice0 Dualsubslice 0 Eu 64 Untyped Reads Unit: messages.Slice0 Dualsubslice 0 Eu A32 Untyped Reads Unit: messages.Slice0 Dualsubslice 0 Eu A32 Untyped Writes Unit: messages.Slice0 Dualsubslice 0 Eu A64 Untyped Writes Unit: messages.Slice0 Dualsubslice 0 Eu Typed Atomics Unit: messages.Slice0 Dualsubslice 0 Eu Typed Reads Unit: messages.Slice0 Dualsubslice 0 Eu Typed Writes Unit: messages.Slice0 Subslice group 0 Eu 64 Untyped Reads Unit: messages.Slice0 Subslice group 0 Eu A32 Untyped Reads Unit: messages.Slice0 Subslice group 0 Eu A32 Untyped Writes Unit: messages.Slice0 Subslice group 0 Eu A64 Untyped Writes Unit: messages.Slice0 Subslice group 0 Eu Typed Atomics Unit: messages.Slice0 Subslice group 0 Eu Typed Reads Unit: messages.Slice0 Subslice group 0 Eu Typed Writes Unit: messages.The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which control shaders were stalled on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs. Unit: cycles.The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs. Unit: cycles.The average rate of IPC calculated for 2 FPU pipelines. The number of FLT64 instructions executed in ALU0 INT64 pipeline. Unit: events.The percentage of time in which EU EM pipeline was actively processing a domain shader instructions. Unit: percent.The percentage of time in which EU EM pipeline was actively processing a geometry shader instructions. Unit: percent.The percentage of time in which EU EM pipeline was actively processing a hull shader instructions. Unit: percent.The percentage of time in which EU EM pipeline was actively processing a pixel shader instruction. Unit: percent.The percentage of time in which EU EM pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which EU EM pipeline was actively processing. Unit: percent.The percentage of time in which EU FPU and EM pipelines were actively processing. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a domain shader instructions. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a geometry shader instructions. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a hull shader instruction. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a pixel shader instruction. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which EU FPU pipeline was actively processing. Unit: percent.The percentage of time in which EU FPU0 pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction. Unit: percent.The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which EU FPU0 pipeline was actively processing. Unit: percent.The percentage of time in which EU FPU1 pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction. Unit: percent.The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing Unit: percent.The percentage of time in which EU FPU1 pipeline was actively processing. Unit: percent.The percentage of time in which EU send pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing a domain shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing a geometry shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing a hull shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing a pixel shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which EU send pipeline was actively processing. Unit: percent.The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline. Unit: percent.The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline. Unit: percent.The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline. Unit: percent.The percentage of time in which GTI Read-Only port has been stalled. Unit: percent.The percentage of time in which GTI Read-Write port has been stalled. Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice4 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 dualsubslice5 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice4 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice5 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice6 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice0 subslice7 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher Unit: percent.The percentage of time in which PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher Unit: percent.The percentage of time in which PS00 output is available Unit: percent.The percentage of time in which PS01 output is available Unit: percent.The percentage of time in which PS10 output is available Unit: percent.The percentage of time in which PS11 output is available Unit: percent.The percentage of time in which PS20 output is available Unit: percent.The percentage of time in which PS21 output is available Unit: percent.The percentage of time in which PS30 output is available Unit: percent.The percentage of time in which PS31 output is available Unit: percent.The percentage of time in which Quad0 L3 bank0 has input available Unit: percent.The percentage of time in which Quad0 L3 bank1 has input available Unit: percent.The percentage of time in which Quad0 L3 bank2 has input available Unit: percent.The percentage of time in which Quad0 L3 bank3 has input available Unit: percent.The percentage of time in which Quad0 L3 bank4 has input available Unit: percent.The percentage of time in which Quad0 L3 bank5 has input available Unit: percent.The percentage of time in which Quad0 L3 bank6 has input available Unit: percent.The percentage of time in which Quad0 L3 bank7 has input available Unit: percent.The percentage of time in which Quad1 L3 bank0 has input available Unit: percent.The percentage of time in which Quad1 L3 bank1 has input available Unit: percent.The percentage of time in which Quad1 L3 bank2 has input available Unit: percent.The percentage of time in which Quad1 L3 bank3 has input available Unit: percent.The percentage of time in which Quad1 L3 bank4 has input available Unit: percent.The percentage of time in which Quad1 L3 bank5 has input available Unit: percent.The percentage of time in which Quad1 L3 bank6 has input available Unit: percent.The percentage of time in which Quad1 L3 bank7 has input available Unit: percent.The percentage of time in which Quad2 L3 bank0 has input available Unit: percent.The percentage of time in which Quad2 L3 bank1 has input available Unit: percent.The percentage of time in which Quad2 L3 bank2 has input available Unit: percent.The percentage of time in which Quad2 L3 bank3 has input available Unit: percent.The percentage of time in which Quad2 L3 bank4 has input available Unit: percent.The percentage of time in which Quad2 L3 bank5 has input available Unit: percent.The percentage of time in which Quad2 L3 bank6 has input available Unit: percent.The percentage of time in which Quad2 L3 bank7 has input available Unit: percent.The percentage of time in which Quad3 L3 bank0 has input available Unit: percent.The percentage of time in which Quad3 L3 bank1 has input available Unit: percent.The percentage of time in which Quad3 L3 bank2 has input available Unit: percent.The percentage of time in which Quad3 L3 bank3 has input available Unit: percent.The percentage of time in which Quad3 L3 bank4 has input available Unit: percent.The percentage of time in which Quad3 L3 bank5 has input available Unit: percent.The percentage of time in which Quad3 L3 bank6 has input available Unit: percent.The percentage of time in which Quad3 L3 bank7 has input available Unit: percent.The percentage of time in which Sampler 0 has been processing EU requests. Unit: percent.The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests. Unit: percent.The percentage of time in which Sampler 1 has been processing EU requests. Unit: percent.The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests. Unit: percent.The percentage of time in which Slice0 Sampler0 has been processing EU requests. Unit: percent.The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing EU requests. Unit: percent.The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing XVE requests. Unit: percent.The percentage of time in which Slice2 Sampler0 has been slowing down the pipe when processing XVE requests. Unit: percent.The percentage of time in which VME (IME or CRE) was actively processing data. Unit: percent.The percentage of time in which VS is sending vertices to CL bypassing other pipeline stages. Unit: percent.The percentage of time in which VS0 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS1 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS2 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS3 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS4 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS5 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS6 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which VS7 pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which XVE EM INT pipeline was actively processing. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which XVE FPU INT64 pipeline was actively processing. Unit: percent.The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing. Unit: percent.The percentage of time in which XVE XMX pipeline was actively processing. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a compute shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a domain shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a hull shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction. Unit: percent.The percentage of time in which XVE send pipeline was actively processing. Unit: percent.The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which both EU FPU pipelines were actively processing. Unit: percent.The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which clipper pipeline stage was stalled. Unit: percent.The percentage of time in which compute shaders were processed actively on the EUs. Unit: percent.The percentage of time in which compute shaders were stalled on the EUs. Unit: percent.The percentage of time in which control shaders were processed actively on the EUs. Unit: percent.The percentage of time in which control shaders were stalled on the EUs. Unit: percent.The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which domain shader pipeline stage was stalled. Unit: percent.The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which evaluation shaders were processed actively on the EUs. Unit: percent.The percentage of time in which evaluation shaders were stalled on the EUs. Unit: percent.The percentage of time in which execution units were actively processing binary instructions on FPU0. Unit: percent.The percentage of time in which execution units were actively processing binary instructions on FPU1. Unit: percent.The percentage of time in which execution units were actively processing hybrid instructions on FPU0. Unit: percent.The percentage of time in which execution units were actively processing hybrid instructions on FPU1. Unit: percent.The percentage of time in which execution units were actively processing move instructions on FPU0. Unit: percent.The percentage of time in which execution units were actively processing move instructions on FPU1. Unit: percent.The percentage of time in which execution units were actively processing ternary instructions on FPU0. Unit: percent.The percentage of time in which execution units were actively processing ternary instructions on FPU1. Unit: percent.The percentage of time in which fragment shaders were processed actively on the EUs. Unit: percent.The percentage of time in which fragment shaders were processed actively on the both FPUs. Unit: percent.The percentage of time in which fragment shaders were stalled on the EUs. Unit: percent.The percentage of time in which geometry pipeline output is ready Unit: percent.The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which geometry shaders were processed actively on the EUs. Unit: percent.The percentage of time in which geometry shaders were stalled on the EUs. Unit: percent.The percentage of time in which hardware threads occupied EUs. Unit: percent.The percentage of time in which hardware threads occupied XVEs. Unit: percent.The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which hull stall pipeline stage was stalled. Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice4 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 dualsubslice5 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice4 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice5 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice6 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice7 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice4 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice5 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice6 Xe core3 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core0 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core1 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core2 thread dispatcher Unit: percent.The percentage of time in which non-PS thread is ready for dispatch on slice7 Xe core3 thread dispatcher Unit: percent.The percentage of time in which pixel values 00 are ready Unit: percent.The percentage of time in which pixel values 01 are ready Unit: percent.The percentage of time in which pixel values 10 are ready Unit: percent.The percentage of time in which pixel values 11 are ready Unit: percent.The percentage of time in which pixel values 20 are ready Unit: percent.The percentage of time in which pixel values 21 are ready Unit: percent.The percentage of time in which pixel values 30 are ready Unit: percent.The percentage of time in which pixel values 31 are ready Unit: percent.The percentage of time in which quad0 L3 bank0 output is ready Unit: percent.The percentage of time in which quad0 L3 bank1 output is ready Unit: percent.The percentage of time in which quad0 L3 bank2 output is ready Unit: percent.The percentage of time in which quad0 L3 bank3 output is ready Unit: percent.The percentage of time in which quad0 L3 bank4 output is ready Unit: percent.The percentage of time in which quad0 L3 bank5 output is ready Unit: percent.The percentage of time in which quad0 L3 bank6 output is ready Unit: percent.The percentage of time in which quad0 L3 bank7 output is ready Unit: percent.The percentage of time in which quad1 L3 bank0 output is ready Unit: percent.The percentage of time in which quad1 L3 bank1 output is ready Unit: percent.The percentage of time in which quad1 L3 bank2 output is ready Unit: percent.The percentage of time in which quad1 L3 bank3 output is ready Unit: percent.The percentage of time in which quad1 L3 bank4 output is ready Unit: percent.The percentage of time in which quad1 L3 bank5 output is ready Unit: percent.The percentage of time in which quad1 L3 bank6 output is ready Unit: percent.The percentage of time in which quad1 L3 bank7 output is ready Unit: percent.The percentage of time in which quad2 L3 bank0 output is ready Unit: percent.The percentage of time in which quad2 L3 bank1 output is ready Unit: percent.The percentage of time in which quad2 L3 bank2 output is ready Unit: percent.The percentage of time in which quad2 L3 bank3 output is ready Unit: percent.The percentage of time in which quad2 L3 bank4 output is ready Unit: percent.The percentage of time in which quad2 L3 bank5 output is ready Unit: percent.The percentage of time in which quad2 L3 bank6 output is ready Unit: percent.The percentage of time in which quad2 L3 bank7 output is ready Unit: percent.The percentage of time in which quad3 L3 bank0 output is ready Unit: percent.The percentage of time in which quad3 L3 bank1 output is ready Unit: percent.The percentage of time in which quad3 L3 bank2 output is ready Unit: percent.The percentage of time in which quad3 L3 bank3 output is ready Unit: percent.The percentage of time in which quad3 L3 bank4 output is ready Unit: percent.The percentage of time in which quad3 L3 bank5 output is ready Unit: percent.The percentage of time in which quad3 L3 bank6 output is ready Unit: percent.The percentage of time in which quad3 L3 bank7 output is ready Unit: percent.The percentage of time in which sampler 0 was bottlenecks. Unit: percent.The percentage of time in which sampler 0 was busy. Unit: percent.The percentage of time in which sampler 1 was bottlenecks. Unit: percent.The percentage of time in which sampler 1 was busy. Unit: percent.The percentage of time in which samplers have been processing EU requests. Unit: percent.The percentage of time in which samplers have been slowing down the pipe when processing EU requests. Unit: percent.The percentage of time in which samplers have been slowing down the pipe when processing XVE requests. Unit: percent.The percentage of time in which samplers or L1 cache are not idle. Unit: percent.The percentage of time in which samplers were bottlenecks. Unit: percent.The percentage of time in which samplers were busy. Unit: percent.The percentage of time in which slice0 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice0 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice0 pipe2 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice0 L3 bank0 has input available Unit: percent.The percentage of time in which slice0 L3 bank0 is active Unit: percent.The percentage of time in which slice0 L3 bank0 is stalled Unit: percent.The percentage of time in which slice0 L3 bank0 output is ready Unit: percent.The percentage of time in which slice0 L3 bank1 has input available Unit: percent.The percentage of time in which slice0 L3 bank1 is active Unit: percent.The percentage of time in which slice0 L3 bank1 is stalled Unit: percent.The percentage of time in which slice0 L3 bank1 output is ready Unit: percent.The percentage of time in which slice0 L3 bank2 has input available Unit: percent.The percentage of time in which slice0 L3 bank2 is active Unit: percent.The percentage of time in which slice0 L3 bank2 is stalled Unit: percent.The percentage of time in which slice0 L3 bank2 output is ready Unit: percent.The percentage of time in which slice0 L3 bank3 has input available Unit: percent.The percentage of time in which slice0 L3 bank3 is active Unit: percent.The percentage of time in which slice0 L3 bank3 is stalled Unit: percent.The percentage of time in which slice0 L3 bank3 output is ready Unit: percent.The percentage of time in which slice0 L3 bank4 has input available Unit: percent.The percentage of time in which slice0 L3 bank4 is active Unit: percent.The percentage of time in which slice0 L3 bank4 is stalled Unit: percent.The percentage of time in which slice0 L3 bank4 output is ready Unit: percent.The percentage of time in which slice0 L3 bank5 has input available Unit: percent.The percentage of time in which slice0 L3 bank5 is active Unit: percent.The percentage of time in which slice0 L3 bank5 is stalled Unit: percent.The percentage of time in which slice0 L3 bank5 output is ready Unit: percent.The percentage of time in which slice0 L3 bank6 has input available Unit: percent.The percentage of time in which slice0 L3 bank6 is active Unit: percent.The percentage of time in which slice0 L3 bank6 output is ready Unit: percent.The percentage of time in which slice0 L3 bank7 has input available Unit: percent.The percentage of time in which slice0 L3 bank7 is active Unit: percent.The percentage of time in which slice0 L3 bank7 output is ready Unit: percent.The percentage of time in which slice0 PS output is available Unit: percent.The percentage of time in which slice0 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice0 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice0 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice0 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice0 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice0 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice0 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice0 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice0 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice0 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice1 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice1 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice2 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice2 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice3 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice3 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice4 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice4 sampler output is ready Unit: percent.The percentage of time in which slice0 dualsubslice5 sampler input is available Unit: percent.The percentage of time in which slice0 dualsubslice5 sampler output is ready Unit: percent.The percentage of time in which slice0 pipe0 PS output is available Unit: percent.The percentage of time in which slice0 pipe0 pixel values are ready Unit: percent.The percentage of time in which slice0 pipe1 PS output is available Unit: percent.The percentage of time in which slice0 pipe1 pixel values are ready Unit: percent.The percentage of time in which slice0 pipe2 PS output is available Unit: percent.The percentage of time in which slice0 pipe2 pixel values are ready Unit: percent.The percentage of time in which slice0 pixel values are ready Unit: percent.The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)) Unit: percent.The percentage of time in which slice0 rasterizer input is available Unit: percent.The percentage of time in which slice0 rasterizer output is ready Unit: percent.The percentage of time in which slice0 subslice0 sampler input is available Unit: percent.The percentage of time in which slice0 subslice0 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice1 sampler input is available Unit: percent.The percentage of time in which slice0 subslice1 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice2 sampler input is available Unit: percent.The percentage of time in which slice0 subslice2 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice3 sampler input is available Unit: percent.The percentage of time in which slice0 subslice3 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice4 sampler input is available Unit: percent.The percentage of time in which slice0 subslice4 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice5 sampler input is available Unit: percent.The percentage of time in which slice0 subslice5 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice6 sampler input is available Unit: percent.The percentage of time in which slice0 subslice6 sampler output is ready Unit: percent.The percentage of time in which slice0 subslice7 sampler input is available Unit: percent.The percentage of time in which slice0 subslice7 sampler output is ready Unit: percent.The percentage of time in which slice1 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice1 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice1 L3 bank0 is active Unit: percent.The percentage of time in which slice1 L3 bank0 is stalled Unit: percent.The percentage of time in which slice1 L3 bank1 is active Unit: percent.The percentage of time in which slice1 L3 bank1 is stalled Unit: percent.The percentage of time in which slice1 L3 bank2 is active Unit: percent.The percentage of time in which slice1 L3 bank2 is stalled Unit: percent.The percentage of time in which slice1 L3 bank3 is active Unit: percent.The percentage of time in which slice1 L3 bank3 is stalled Unit: percent.The percentage of time in which slice1 PS output is available Unit: percent.The percentage of time in which slice1 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice1 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice1 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice1 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice1 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice1 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice1 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice1 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice1 pixel values are ready Unit: percent.The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice1 rasterizer input is available Unit: percent.The percentage of time in which slice1 rasterizer output is ready Unit: percent.The percentage of time in which slice1 subslice0 sampler input is available Unit: percent.The percentage of time in which slice1 subslice0 sampler output is ready Unit: percent.The percentage of time in which slice1 subslice1 sampler input is available Unit: percent.The percentage of time in which slice1 subslice1 sampler output is ready Unit: percent.The percentage of time in which slice1 subslice2 sampler input is available Unit: percent.The percentage of time in which slice1 subslice2 sampler output is ready Unit: percent.The percentage of time in which slice2 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice2 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice2 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice2 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice2 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice2 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice2 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice2 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice2 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice2 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice2 rasterizer input is available Unit: percent.The percentage of time in which slice2 rasterizer output is ready Unit: percent.The percentage of time in which slice3 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice3 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice3 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice3 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice3 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice3 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice3 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice3 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice3 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice3 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice3 rasterizer input is available Unit: percent.The percentage of time in which slice3 rasterizer output is ready Unit: percent.The percentage of time in which slice4 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice4 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice4 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice4 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice4 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice4 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice4 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice4 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice4 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice4 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice4 rasterizer input is available Unit: percent.The percentage of time in which slice4 rasterizer output is ready Unit: percent.The percentage of time in which slice5 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice5 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice5 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice5 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice5 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice5 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice5 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice5 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice5 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice5 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice5 rasterizer input is available Unit: percent.The percentage of time in which slice5 rasterizer output is ready Unit: percent.The percentage of time in which slice6 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice6 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice6 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice6 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice6 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice6 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice6 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice6 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice6 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice6 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice6 rasterizer input is available Unit: percent.The percentage of time in which slice6 rasterizer output is ready Unit: percent.The percentage of time in which slice7 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice7 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied) Unit: percent.The percentage of time in which slice7 Xe core0 sampler input is available Unit: percent.The percentage of time in which slice7 Xe core0 sampler output is ready Unit: percent.The percentage of time in which slice7 Xe core1 sampler input is available Unit: percent.The percentage of time in which slice7 Xe core1 sampler output is ready Unit: percent.The percentage of time in which slice7 Xe core2 sampler input is available Unit: percent.The percentage of time in which slice7 Xe core2 sampler output is ready Unit: percent.The percentage of time in which slice7 Xe core3 sampler input is available Unit: percent.The percentage of time in which slice7 Xe core3 sampler output is ready Unit: percent.The percentage of time in which slice7 rasterizer input is available Unit: percent.The percentage of time in which slice7 rasterizer output is ready Unit: percent.The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which stream-output pipeline stage was stalled. Unit: percent.The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which strip-fans pipeline stage was stalled. Unit: percent.The percentage of time in which tessellation pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which the Execution Units were actively processing. Unit: percent.The percentage of time in which the Execution Units were idle. Unit: percent.The percentage of time in which the Execution Units were stalled. Unit: percent.The percentage of time in which the GPU has been processing GPU commands. Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice4 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice0 dualsubslice5 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice4 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice5 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice6 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core0 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core1 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core2 thread dispatcher port 3 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 0 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 1 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 2 Unit: percent.The percentage of time in which thread header is ready on slice7 Xe core3 thread dispatcher port 3 Unit: percent.The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline. Unit: percent.The percentage of time in which vertex shaders were processed actively on the EUs. Unit: percent.The percentage of time in which vertex shaders were stalled on the EUs. Unit: percent.The percentage of time when IDI0 SQ0 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ00 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ01 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ1 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ10 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ11 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ20 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ30 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ40 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ50 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ60 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI0 SQ70 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI1 SQ0 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when IDI1 SQ1 is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when SQ is filled above a threshold (usually 48 entries) Unit: percent.The percentage of time when Vdbox0 command streamer was busy. Unit: percent.The percentage of time when Vdbox1 command streamer was busy. Unit: percent.The percentage of time when any command streamer was busy. Unit: percent.The percentage of time when any compute engine is busy Unit: percent.The percentage of time when blitter command streamer was busy. Unit: percent.The percentage of time when compute command streamer 0 was busy. Unit: percent.The percentage of time when compute command streamer 1 was busy. Unit: percent.The percentage of time when compute command streamer 2 was busy. Unit: percent.The percentage of time when compute command streamer 3 was busy. Unit: percent.The percentage of time when posh command streamer was busy. Unit: percent.The percentage of time when render and any compute engines are simultaneously busy Unit: percent.The percentage of time when render and compute engines are simultaneously busy Unit: percent.The percentage of time when render command streamer was busy. Unit: percent.The percentage of time when sampler slice0 Xe core0 is busy Unit: percent.The percentage of time when sampler slice0 dualsubslice0 is bottleneck Unit: percent.The percentage of time when sampler slice2 Xe core0 is busy Unit: percent.The percentage of time when vdbox00 command streamer was busy. Unit: percent.The percentage of time when vdbox10 command streamer was busy. Unit: percent.The percentage of time when vebox command streamer was busy. Unit: percent.The percentage of time when vebox0 command streamer was busy. Unit: percent.The percentage of time when vebox1 command streamer was busy. Unit: percent.The ratio of EU typed atomics requests to L3 cache line writes. The ratio of EU typed read requests to L3 cache line reads. The ratio of EU typed write requests to L3 cache line writes. The ratio of EU untyped read requests to L3 cache line reads. The ratio of EU untyped write requests to L3 cache line writes. The subslice 0 Data Port data and constant reads from L3 cache. Unit: messages.The subslice 0 Data Port data writes to L3 cache. Unit: messages.The subslice 0 Data Port reads from L3 cache. Unit: messages.The subslice 0 Data Port writes to L3 cache. Unit: messages.The subslice 0 EU A64 Untyped Reads subslice 0. Unit: messages.The subslice 0 EU A64 Untyped Writes subslice 0. Unit: messages.The subslice 0 EU Typed Atomics subslice 0. Unit: messages.The subslice 0 EU Typed Reads subslice 0. Unit: messages.The subslice 0 EU Typed Writes subslice 0. Unit: messages.The subslice 0 EU URB Atomics subslice 0. Unit: messages.The subslice 0 EU Untyped Atomics subslice 0. Unit: messages.The subslice 0 EU Untyped Reads subslice 0. Unit: messages.The subslice 0 EU Untyped Writes subslice 0. Unit: messages.The subslice 0 EU data reads from Data Port with 128B per message. Unit: messages.The subslice 0 EU data reads from Data Port with 256B per message. Unit: messages.The subslice 0 EU data reads from Data Port with 32B per message. Unit: messages.The subslice 0 EU data reads from Data Port with 64B per message. Unit: messages.The subslice 0 EU data simd16 writes to Data Port with 128B per message. Unit: messages.The subslice 0 EU data simd16 writes to Data Port with 192B per message. Unit: messages.The subslice 0 EU data simd16 writes to Data Port with 256B per message. Unit: messages.The subslice 0 EU data writes to Data Port with 128B per message. Unit: messages.The subslice 0 EU data writes to Data Port with 32B per message. Unit: messages.The subslice 0 EU data writes to Data Port with 64B per message. Unit: messages.The subslice 0 typed atomics. Unit: messages.The subslice 0 typed reads. Unit: messages.The subslice 0 typed writes. Unit: messages.The subslice 0 untyped reads (including SLM reads). Unit: messages.The subslice 0 untyped writes (including SLM writes). Unit: messages.The total number of GPU core clocks elapsed during the measurement. Unit: cycles.The total number of GPU memory bytes read from GTI. Unit: bytes.The total number of GPU memory bytes read from shared local memory. Unit: bytes.The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI. Unit: bytes.The total number of GPU memory bytes transferred between GPU and LLC. Unit: bytes.The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups. Unit: bytes.The total number of GPU memory bytes transferred between GTI and Uncore ring. Unit: bytes.The total number of GPU memory bytes transferred between L3 caches and GTI. Unit: bytes.The total number of GPU memory bytes transferred between depth caches and GTI. Unit: bytes.The total number of GPU memory bytes transferred between render color caches and GTI. Unit: bytes.The total number of GPU memory bytes transferred between samplers and L3 caches. Unit: bytes.The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB. Unit: bytes.The total number of GPU memory bytes transferred via L3. Unit: bytes.The total number of GPU memory bytes written into shared local memory. Unit: bytes.The total number of GPU memory bytes written to GTI. Unit: bytes.The total number of GTI memory reads (64B each). Unit: messages.The total number of GTI memory reads from Command Streamer. Unit: messages.The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses). Unit: messages.The total number of GTI memory reads from Hierarchical Depth Cache. Unit: messages.The total number of GTI memory reads from L3 (L3 Cache misses). Unit: messages.The total number of GTI memory reads from L3 (L3 misses). Unit: messages.The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses). Unit: messages.The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses). Unit: messages.The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses). Unit: messages.The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses). Unit: messages.The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses). Unit: messages.The total number of GTI memory reads from Render Color Cache (Render Color Cache misses). Unit: messages.The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses). Unit: messages.The total number of GTI memory reads from Render Depth Cache. Unit: messages.The total number of GTI memory reads from Resource Streamer. Unit: messages.The total number of GTI memory reads from Stencil Cache (Stencil Cache misses). Unit: messages.The total number of GTI memory reads from Stencil Cache. Unit: messages.The total number of GTI memory reads from Vertex Fetch. Unit: messages.The total number of GTI memory reads. Unit: messages.The total number of GTI memory writes (64B each). Unit: messages.The total number of GTI memory writes from Command Streamer. Unit: messages.The total number of GTI memory writes from Hierarchical Depth Cache. Unit: messages.The total number of GTI memory writes from L3 (L3 invalidations). Unit: messages.The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations). Unit: messages.The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations). Unit: messages.The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations). Unit: messages.The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations). Unit: messages.The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations). Unit: messages.The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations). Unit: messages.The total number of GTI memory writes from Render Depth Cache. Unit: messages.The total number of GTI memory writes from Stencil Cache. Unit: messages.The total number of GTI memory writes from Stream Output. Unit: messages.The total number of GTI memory writes. Unit: messages.The total number of L3 accesses from all entities. Unit: messages.The total number of L3 cache lookup accesses w/o IC. Unit: messages.The total number of L3 misses. Unit: messages.The total number of LLC cache lookups done from the GPU (64b reads, 32B writes). Unit: messages.The total number of LLC cache lookups for reads done from the GPU. Unit: messages.The total number of LLC cache lookups for write done from the GPU (32B writes). Unit: messages.The total number of accesses to L3 Bank 00 from IC cache. Unit: messages.The total number of accesses to L3 Bank 00. Unit: messages.The total number of accesses to L3 Bank 01. Unit: messages.The total number of accesses to L3 Bank 02. Unit: messages.The total number of accesses to L3 Bank 03. Unit: messages.The total number of accesses to L3 Bank 10 from IC cache. Unit: messages.The total number of accesses to L3 Bank 10. Unit: messages.The total number of accesses to L3 Bank 11. Unit: messages.The total number of accesses to L3 Bank 12. Unit: messages.The total number of accesses to L3 Bank 13. Unit: messages.The total number of accesses to Slice0 L3 Bank0. Unit: messages.The total number of accesses to Slice0 L3 Bank1. Unit: messages.The total number of accesses to Slice0 L3 Bank2. Unit: messages.The total number of accesses to Slice0 L3 Bank3. Unit: messages.The total number of accesses to Slice0 L3 Bank4. Unit: messages.The total number of accesses to Slice0 L3 Bank5. Unit: messages.The total number of accesses to Slice0 L3 Bank6. Unit: messages.The total number of accesses to Slice0 L3 Bank7. Unit: messages.The total number of all GTI accesses to the ring. Unit: messages.The total number of all accesses from GTI to the ring. Unit: messages.The total number of blended samples or pixels written to all render targets. Unit: pixels.The total number of byten written into shared local memory. Unit: bytes.The total number of compute shader hardware threads dispatched. Unit: threads.The total number of control shader hardware threads dispatched. Unit: threads.The total number of domain shader hardware threads dispatched. Unit: threads.The total number of evaluation shader hardware threads dispatched. Unit: threads.The total number of fragment shader hardware threads dispatched. Unit: threads.The total number of geometry shader hardware threads dispatched. Unit: threads.The total number of hits in L3 Bank 00 from IC cache. Unit: messages.The total number of hits in L3 Bank 10 from IC cache. Unit: messages.The total number of hull shader hardware threads dispatched. Unit: threads.The total number of messages send to samplers. Unit: messages.The total number of pixels dropped on early depth test. Unit: events.The total number of pixels dropped on early depth test. Unit: pixels.The total number of pixels dropped on early hierarchical depth test. Unit: pixels.The total number of pixels dropped on post-FS alpha test. Unit: pixels.The total number of pixels dropped on post-FS alpha, stencil, or depth tests. Unit: pixels.The total number of pixels dropped on post-FS depth test. Unit: pixels.The total number of pixels dropped on post-FS stencil test. Unit: pixels.The total number of rasterized pixels. Unit: pixels.The total number of reads from shared local memory. Unit: messages.The total number of sampler cache misses in all LODs in all sampler units. Unit: messages.The total number of samples or pixels dropped in fragment shaders. Unit: pixels.The total number of samples or pixels written to all render targets. Unit: pixels.The total number of shader atomic memory accesses. Unit: messages.The total number of shader barrier messages. Unit: messages.The total number of shader memory accesses to L3. Unit: messages.The total number of successful LLC cache lookups done from the GPU. Unit: messages.The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache. Unit: texels.The total number of texels lookups in LOD0 in all sampler units. Unit: texels.The total number of texels lookups in LOD0 in sampler 0 unit. Unit: texels.The total number of texels lookups in LOD0 in sampler 1 unit. Unit: texels.The total number of texels seen on input (with 2x2 accuracy) in all sampler units. Unit: texels.The total number of typed atomic accesses via Data Port. Unit: events.The total number of typed atomics. Unit: messages.The total number of typed memory bytes read via Data Port. Unit: bytes.The total number of typed memory bytes written via Data Port. Unit: bytes.The total number of untyped memory bytes written via Data Port. Unit: bytes.The total number of vertex shader hardware threads dispatched. Unit: threads.The total number of writes into shared local memory. Unit: messages.Time elapsed on the GPU during the measurement. Unit: ns.Total Compute Shader GPU duration. Unit: us.Total Control Shader GPU duration. Unit: us.Total Evaluation Shader GPU duration. Unit: us.Total Fragment Shader GPU duration. Unit: us.Total Geometry Shader GPU duration. Unit: us.Total Vertex Shader GPU duration. Unit: us.AMFS 4X4 SHADING REQUEST SLICE0AMFS 4X4 SHADING REQUEST SLICE1AMFS 4X4 SHADING REQUEST SLICE2AMFS 4X4 SHADING REQUEST SLICE3AMFS 4X4 SHADING REQUEST SLICE4AMFS 4X4 SHADING REQUEST SLICE5AMFS 4X4 SHADING REQUEST SLICE6AMFS 4X4 SHADING REQUEST SLICE7AMFS CACHE HIT SLICE0AMFS CACHE HIT SLICE1AMFS CACHE HIT SLICE2AMFS CACHE HIT SLICE3AMFS CACHE HIT SLICE4AMFS CACHE HIT SLICE5AMFS CACHE HIT SLICE6AMFS CACHE HIT SLICE7AMFS CACHE MISS SLICE0AMFS CACHE MISS SLICE1AMFS CACHE MISS SLICE2AMFS CACHE MISS SLICE3AMFS CACHE MISS SLICE4AMFS CACHE MISS SLICE5AMFS CACHE MISS SLICE6AMFS CACHE MISS SLICE7AMFS L3 ACCESS SLICE0AMFS L3 ACCESS SLICE1AMFS L3 ACCESS SLICE2AMFS L3 ACCESS SLICE3AMFS L3 ACCESS SLICE4AMFS L3 ACCESS SLICE5AMFS L3 ACCESS SLICE6AMFS L3 ACCESS SLICE7AMFS L3 ATOMIC SLICE0AMFS L3 ATOMIC SLICE1AMFS L3 ATOMIC SLICE2AMFS L3 ATOMIC SLICE3AMFS L3 ATOMIC SLICE4AMFS L3 ATOMIC SLICE5AMFS L3 ATOMIC SLICE6AMFS L3 ATOMIC SLICE7AMFS L3 WRITE SLICE0AMFS L3 WRITE SLICE1AMFS L3 WRITE SLICE2AMFS L3 WRITE SLICE3AMFS L3 WRITE SLICE4AMFS L3 WRITE SLICE5AMFS L3 WRITE SLICE6AMFS L3 WRITE SLICE7AMFS STALL ALL INPUT SLICE0AMFS STALL ALL INPUT SLICE1AMFS STALL ALL INPUT SLICE2AMFS STALL ALL INPUT SLICE3AMFS STALL ALL INPUT SLICE4AMFS STALL ALL INPUT SLICE5AMFS STALL ALL INPUT SLICE6AMFS STALL ALL INPUT SLICE7AMFS STALL ANY INPUT SLICE0AMFS STALL ANY INPUT SLICE1AMFS STALL ANY INPUT SLICE2AMFS STALL ANY INPUT SLICE3AMFS STALL ANY INPUT SLICE4AMFS STALL ANY INPUT SLICE5AMFS STALL ANY INPUT SLICE6AMFS STALL ANY INPUT SLICE7ASYNC CS EM Pipe ActiveASYNC CS FPU Pipe ActiveASYNC GPGPU THREAD EXIT COUNT XECORE0ASYNC GPGPU THREAD EXIT COUNT XECORE1ASYNC GPGPU THREAD EXIT COUNT XECORE10ASYNC GPGPU THREAD EXIT COUNT XECORE11ASYNC GPGPU THREAD EXIT COUNT XECORE12ASYNC GPGPU THREAD EXIT COUNT XECORE13ASYNC GPGPU THREAD EXIT COUNT XECORE14ASYNC GPGPU THREAD EXIT COUNT XECORE15ASYNC GPGPU THREAD EXIT COUNT XECORE16ASYNC GPGPU THREAD EXIT COUNT XECORE17ASYNC GPGPU THREAD EXIT COUNT XECORE18ASYNC GPGPU THREAD EXIT COUNT XECORE19ASYNC GPGPU THREAD EXIT COUNT XECORE2ASYNC GPGPU THREAD EXIT COUNT XECORE20ASYNC GPGPU THREAD EXIT COUNT XECORE21ASYNC GPGPU THREAD EXIT COUNT XECORE22ASYNC GPGPU THREAD EXIT COUNT XECORE23ASYNC GPGPU THREAD EXIT COUNT XECORE24ASYNC GPGPU THREAD EXIT COUNT XECORE25ASYNC GPGPU THREAD EXIT COUNT XECORE26ASYNC GPGPU THREAD EXIT COUNT XECORE27ASYNC GPGPU THREAD EXIT COUNT XECORE28ASYNC GPGPU THREAD EXIT COUNT XECORE29ASYNC GPGPU THREAD EXIT COUNT XECORE3ASYNC GPGPU THREAD EXIT COUNT XECORE30ASYNC GPGPU THREAD EXIT COUNT XECORE31ASYNC GPGPU THREAD EXIT COUNT XECORE4ASYNC GPGPU THREAD EXIT COUNT XECORE5ASYNC GPGPU THREAD EXIT COUNT XECORE6ASYNC GPGPU THREAD EXIT COUNT XECORE7ASYNC GPGPU THREAD EXIT COUNT XECORE8ASYNC GPGPU THREAD EXIT COUNT XECORE9ASYNC GPGPU THREADGROUP COUNT XECORE0ASYNC GPGPU THREADGROUP COUNT XECORE1ASYNC GPGPU THREADGROUP COUNT XECORE10ASYNC GPGPU THREADGROUP COUNT XECORE11ASYNC GPGPU THREADGROUP COUNT XECORE12ASYNC GPGPU THREADGROUP COUNT XECORE13ASYNC GPGPU THREADGROUP COUNT XECORE14ASYNC GPGPU THREADGROUP COUNT XECORE15ASYNC GPGPU THREADGROUP COUNT XECORE16ASYNC GPGPU THREADGROUP COUNT XECORE17ASYNC GPGPU THREADGROUP COUNT XECORE18ASYNC GPGPU THREADGROUP COUNT XECORE19ASYNC GPGPU THREADGROUP COUNT XECORE2ASYNC GPGPU THREADGROUP COUNT XECORE20ASYNC GPGPU THREADGROUP COUNT XECORE21ASYNC GPGPU THREADGROUP COUNT XECORE22ASYNC GPGPU THREADGROUP COUNT XECORE23ASYNC GPGPU THREADGROUP COUNT XECORE24ASYNC GPGPU THREADGROUP COUNT XECORE25ASYNC GPGPU THREADGROUP COUNT XECORE26ASYNC GPGPU THREADGROUP COUNT XECORE27ASYNC GPGPU THREADGROUP COUNT XECORE28ASYNC GPGPU THREADGROUP COUNT XECORE29ASYNC GPGPU THREADGROUP COUNT XECORE3ASYNC GPGPU THREADGROUP COUNT XECORE30ASYNC GPGPU THREADGROUP COUNT XECORE31ASYNC GPGPU THREADGROUP COUNT XECORE4ASYNC GPGPU THREADGROUP COUNT XECORE5ASYNC GPGPU THREADGROUP COUNT XECORE6ASYNC GPGPU THREADGROUP COUNT XECORE7ASYNC GPGPU THREADGROUP COUNT XECORE8ASYNC GPGPU THREADGROUP COUNT XECORE9AVG GPU Core FrequencyAll Data Port 0 Reads from L3All Data Port 0 Writes to L3Alpha Test FailsAny Engine BusyAny compute engine busyAnyRingBusyBC BottleneckBC00 BottleneckBC10 BottleneckBC20 BottleneckBC30 BottleneckBC40 BottleneckBC50 BottleneckBC60 BottleneckBC70 BottleneckBlitter Ring BusyCL StallCL0 StallCL1 StallCL2 StallCL3 StallCL4 StallCL5 StallCL6 StallCL7 StallCLIPPER INPUT AVAILABLE SLICE0CLIPPER INPUT AVAILABLE SLICE1CLIPPER INPUT AVAILABLE SLICE2CLIPPER INPUT AVAILABLE SLICE3CLIPPER INPUT AVAILABLE SLICE4CLIPPER INPUT AVAILABLE SLICE5CLIPPER INPUT AVAILABLE SLICE6CLIPPER INPUT AVAILABLE SLICE7CLIPPER INPUT VERTEX SLICE0CLIPPER INPUT VERTEX SLICE1CLIPPER INPUT VERTEX SLICE2CLIPPER INPUT VERTEX SLICE3CLIPPER INPUT VERTEX SLICE4CLIPPER INPUT VERTEX SLICE5CLIPPER INPUT VERTEX SLICE6CLIPPER INPUT VERTEX SLICE7CLIPPER OUTPUT READY SLICE0CLIPPER OUTPUT READY SLICE1CLIPPER OUTPUT READY SLICE2CLIPPER OUTPUT READY SLICE3CLIPPER OUTPUT READY SLICE4CLIPPER OUTPUT READY SLICE5CLIPPER OUTPUT READY SLICE6CLIPPER OUTPUT READY SLICE7CLIPPER PRIMITIVE CULL SLICE0CLIPPER PRIMITIVE CULL SLICE1CLIPPER PRIMITIVE CULL SLICE2CLIPPER PRIMITIVE CULL SLICE3CLIPPER PRIMITIVE CULL SLICE4CLIPPER PRIMITIVE CULL SLICE5CLIPPER PRIMITIVE CULL SLICE6CLIPPER PRIMITIVE CULL SLICE7CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1CLIPPER PRIMITIVE FAR NEAR CLIP SLICE2CLIPPER PRIMITIVE FAR NEAR CLIP SLICE3CLIPPER PRIMITIVE FAR NEAR CLIP SLICE4CLIPPER PRIMITIVE FAR NEAR CLIP SLICE5CLIPPER PRIMITIVE FAR NEAR CLIP SLICE6CLIPPER PRIMITIVE FAR NEAR CLIP SLICE7CLIPPER PRIMITIVE OUTPUT SLICE0CLIPPER PRIMITIVE OUTPUT SLICE1CLIPPER PRIMITIVE OUTPUT SLICE2CLIPPER PRIMITIVE OUTPUT SLICE3CLIPPER PRIMITIVE OUTPUT SLICE4CLIPPER PRIMITIVE OUTPUT SLICE5CLIPPER PRIMITIVE OUTPUT SLICE6CLIPPER PRIMITIVE OUTPUT SLICE7CLIPPER TRANSACTION OUTPUT SLICE0CLIPPER TRANSACTION OUTPUT SLICE1CLIPPER TRANSACTION OUTPUT SLICE2CLIPPER TRANSACTION OUTPUT SLICE3CLIPPER TRANSACTION OUTPUT SLICE4CLIPPER TRANSACTION OUTPUT SLICE5CLIPPER TRANSACTION OUTPUT SLICE6CLIPPER TRANSACTION OUTPUT SLICE7COLOR L3 ACCESS L3BANK0COLOR L3 ACCESS L3BANK1COLOR L3 ACCESS L3BANK2COLOR L3 ACCESS L3BANK3COLOR L3 ACCESS L3BANK4COLOR L3 ACCESS L3BANK5COLOR L3 ACCESS L3BANK6COLOR L3 ACCESS L3BANK7COLOR L3 HIT L3BANK0COLOR L3 HIT L3BANK1COLOR L3 HIT L3BANK10COLOR L3 HIT L3BANK11COLOR L3 HIT L3BANK12COLOR L3 HIT L3BANK13COLOR L3 HIT L3BANK14COLOR L3 HIT L3BANK15COLOR L3 HIT L3BANK16COLOR L3 HIT L3BANK17COLOR L3 HIT L3BANK18COLOR L3 HIT L3BANK19COLOR L3 HIT L3BANK2COLOR L3 HIT L3BANK20COLOR L3 HIT L3BANK21COLOR L3 HIT L3BANK22COLOR L3 HIT L3BANK23COLOR L3 HIT L3BANK24COLOR L3 HIT L3BANK25COLOR L3 HIT L3BANK26COLOR L3 HIT L3BANK27COLOR L3 HIT L3BANK28COLOR L3 HIT L3BANK29COLOR L3 HIT L3BANK3COLOR L3 HIT L3BANK30COLOR L3 HIT L3BANK31COLOR L3 HIT L3BANK4COLOR L3 HIT L3BANK5COLOR L3 HIT L3BANK6COLOR L3 HIT L3BANK7COLOR L3 HIT L3BANK8COLOR L3 HIT L3BANK9COLOR PIPE CACHE LATENCY1 STALL CPIPE0COLOR PIPE CACHE LATENCY1 STALL CPIPE1COLOR PIPE CACHE LATENCY1 STALL CPIPE10COLOR PIPE CACHE LATENCY1 STALL CPIPE11COLOR PIPE CACHE LATENCY1 STALL CPIPE12COLOR PIPE CACHE LATENCY1 STALL CPIPE13COLOR PIPE CACHE LATENCY1 STALL CPIPE14COLOR PIPE CACHE LATENCY1 STALL CPIPE15COLOR PIPE CACHE LATENCY1 STALL CPIPE2COLOR PIPE CACHE LATENCY1 STALL CPIPE3COLOR PIPE CACHE LATENCY1 STALL CPIPE4COLOR PIPE CACHE LATENCY1 STALL CPIPE5COLOR PIPE CACHE LATENCY1 STALL CPIPE6COLOR PIPE CACHE LATENCY1 STALL CPIPE7COLOR PIPE CACHE LATENCY1 STALL CPIPE8COLOR PIPE CACHE LATENCY1 STALL CPIPE9COLOR PIPE CACHE LATENCY2 STALL L3NODE0COLOR PIPE CACHE LATENCY2 STALL L3NODE1COLOR PIPE CACHE LATENCY2 STALL L3NODE2COLOR PIPE CACHE LATENCY2 STALL L3NODE3COLOR PIPE CACHE LATENCY2 STALL L3NODE4COLOR PIPE CACHE LATENCY2 STALL L3NODE5COLOR PIPE CACHE LATENCY2 STALL L3NODE6COLOR PIPE CACHE LATENCY2 STALL L3NODE7COMMAND PARSER COMPUTE ENGINE BUSYCOMMAND PARSER COMPUTE ENGINE BUSY CCS0COMMAND PARSER COMPUTE ENGINE BUSY CCS1COMMAND PARSER COMPUTE ENGINE BUSY CCS2COMMAND PARSER COMPUTE ENGINE BUSY CCS3COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNTCOMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3COMMAND PARSER COPY ENGINE BUSYCOMMAND PARSER FLUSH COUNTCOMMAND PARSER RENDER ENGINE BUSYCOMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNTCOMMAND PARSER RENDER ENGINE DRAW COUNTCOMMAND PARSER VIDEO ENGINE BUSYCOMMAND PARSER VIDEO ENGINE BUSY VDBOX0COMMAND PARSER VIDEO ENGINE BUSY VDBOX1COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSYCOMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1CS AVG Active per ThreadCS AVG Stall per ThreadCS DurationCS EM Pipe ActiveCS EU ActiveCS EU StallCS FPU Pipe ActiveCS FPU0 Pipe ActiveCS FPU1 Pipe ActiveCS Send Pipe ActiveCS Send Pipeline ActiveCS Threads DispatchedClipper BottleneckClipper0 BottleneckClipper1 BottleneckClipper2 BottleneckClipper3 BottleneckClipper4 BottleneckClipper5 BottleneckClipper6 BottleneckClipper7 BottleneckCompute Ring BusyComputeEngine0 Ring BusyComputeEngine1 Ring BusyComputeEngine2 Ring BusyComputeEngine3 Ring BusyDATAPORT BYTE READDATAPORT BYTE READ XECORE0DATAPORT BYTE READ XECORE1DATAPORT BYTE READ XECORE10DATAPORT BYTE READ XECORE11DATAPORT BYTE READ XECORE12DATAPORT BYTE READ XECORE13DATAPORT BYTE READ XECORE14DATAPORT BYTE READ XECORE15DATAPORT BYTE READ XECORE16DATAPORT BYTE READ XECORE17DATAPORT BYTE READ XECORE18DATAPORT BYTE READ XECORE19DATAPORT BYTE READ XECORE2DATAPORT BYTE READ XECORE20DATAPORT BYTE READ XECORE21DATAPORT BYTE READ XECORE22DATAPORT BYTE READ XECORE23DATAPORT BYTE READ XECORE24DATAPORT BYTE READ XECORE25DATAPORT BYTE READ XECORE26DATAPORT BYTE READ XECORE27DATAPORT BYTE READ XECORE28DATAPORT BYTE READ XECORE29DATAPORT BYTE READ XECORE3DATAPORT BYTE READ XECORE30DATAPORT BYTE READ XECORE31DATAPORT BYTE READ XECORE4DATAPORT BYTE READ XECORE5DATAPORT BYTE READ XECORE6DATAPORT BYTE READ XECORE7DATAPORT BYTE READ XECORE8DATAPORT BYTE READ XECORE9DATAPORT BYTE WRITEDATAPORT BYTE WRITE XECORE0DATAPORT BYTE WRITE XECORE1DATAPORT BYTE WRITE XECORE10DATAPORT BYTE WRITE XECORE11DATAPORT BYTE WRITE XECORE12DATAPORT BYTE WRITE XECORE13DATAPORT BYTE WRITE XECORE14DATAPORT BYTE WRITE XECORE15DATAPORT BYTE WRITE XECORE16DATAPORT BYTE WRITE XECORE17DATAPORT BYTE WRITE XECORE18DATAPORT BYTE WRITE XECORE19DATAPORT BYTE WRITE XECORE2DATAPORT BYTE WRITE XECORE20DATAPORT BYTE WRITE XECORE21DATAPORT BYTE WRITE XECORE22DATAPORT BYTE WRITE XECORE23DATAPORT BYTE WRITE XECORE24DATAPORT BYTE WRITE XECORE25DATAPORT BYTE WRITE XECORE26DATAPORT BYTE WRITE XECORE27DATAPORT BYTE WRITE XECORE28DATAPORT BYTE WRITE XECORE29DATAPORT BYTE WRITE XECORE3DATAPORT BYTE WRITE XECORE30DATAPORT BYTE WRITE XECORE31DATAPORT BYTE WRITE XECORE4DATAPORT BYTE WRITE XECORE5DATAPORT BYTE WRITE XECORE6DATAPORT BYTE WRITE XECORE7DATAPORT BYTE WRITE XECORE8DATAPORT BYTE WRITE XECORE9DATAPORT INPUT AVAILABLE XECORE0DATAPORT INPUT AVAILABLE XECORE1DATAPORT INPUT AVAILABLE XECORE10DATAPORT INPUT AVAILABLE XECORE11DATAPORT INPUT AVAILABLE XECORE12DATAPORT INPUT AVAILABLE XECORE13DATAPORT INPUT AVAILABLE XECORE14DATAPORT INPUT AVAILABLE XECORE15DATAPORT INPUT AVAILABLE XECORE16DATAPORT INPUT AVAILABLE XECORE17DATAPORT INPUT AVAILABLE XECORE18DATAPORT INPUT AVAILABLE XECORE19DATAPORT INPUT AVAILABLE XECORE2DATAPORT INPUT AVAILABLE XECORE20DATAPORT INPUT AVAILABLE XECORE21DATAPORT INPUT AVAILABLE XECORE22DATAPORT INPUT AVAILABLE XECORE23DATAPORT INPUT AVAILABLE XECORE24DATAPORT INPUT AVAILABLE XECORE25DATAPORT INPUT AVAILABLE XECORE26DATAPORT INPUT AVAILABLE XECORE27DATAPORT INPUT AVAILABLE XECORE28DATAPORT INPUT AVAILABLE XECORE29DATAPORT INPUT AVAILABLE XECORE3DATAPORT INPUT AVAILABLE XECORE30DATAPORT INPUT AVAILABLE XECORE31DATAPORT INPUT AVAILABLE XECORE4DATAPORT INPUT AVAILABLE XECORE5DATAPORT INPUT AVAILABLE XECORE6DATAPORT INPUT AVAILABLE XECORE7DATAPORT INPUT AVAILABLE XECORE8DATAPORT INPUT AVAILABLE XECORE9DATAPORT L3 HIT L3BANK0DATAPORT L3 HIT L3BANK1DATAPORT L3 HIT L3BANK10DATAPORT L3 HIT L3BANK11DATAPORT L3 HIT L3BANK12DATAPORT L3 HIT L3BANK13DATAPORT L3 HIT L3BANK14DATAPORT L3 HIT L3BANK15DATAPORT L3 HIT L3BANK16DATAPORT L3 HIT L3BANK17DATAPORT L3 HIT L3BANK18DATAPORT L3 HIT L3BANK19DATAPORT L3 HIT L3BANK2DATAPORT L3 HIT L3BANK20DATAPORT L3 HIT L3BANK21DATAPORT L3 HIT L3BANK22DATAPORT L3 HIT L3BANK23DATAPORT L3 HIT L3BANK24DATAPORT L3 HIT L3BANK25DATAPORT L3 HIT L3BANK26DATAPORT L3 HIT L3BANK27DATAPORT L3 HIT L3BANK28DATAPORT L3 HIT L3BANK29DATAPORT L3 HIT L3BANK3DATAPORT L3 HIT L3BANK30DATAPORT L3 HIT L3BANK31DATAPORT L3 HIT L3BANK4DATAPORT L3 HIT L3BANK5DATAPORT L3 HIT L3BANK6DATAPORT L3 HIT L3BANK7DATAPORT L3 HIT L3BANK8DATAPORT L3 HIT L3BANK9DATAPORT L3 READ L3BANK0DATAPORT L3 READ L3BANK1DATAPORT L3 READ L3BANK10DATAPORT L3 READ L3BANK11DATAPORT L3 READ L3BANK12DATAPORT L3 READ L3BANK13DATAPORT L3 READ L3BANK14DATAPORT L3 READ L3BANK15DATAPORT L3 READ L3BANK16DATAPORT L3 READ L3BANK17DATAPORT L3 READ L3BANK18DATAPORT L3 READ L3BANK19DATAPORT L3 READ L3BANK2DATAPORT L3 READ L3BANK20DATAPORT L3 READ L3BANK21DATAPORT L3 READ L3BANK22DATAPORT L3 READ L3BANK23DATAPORT L3 READ L3BANK24DATAPORT L3 READ L3BANK25DATAPORT L3 READ L3BANK26DATAPORT L3 READ L3BANK27DATAPORT L3 READ L3BANK28DATAPORT L3 READ L3BANK29DATAPORT L3 READ L3BANK3DATAPORT L3 READ L3BANK30DATAPORT L3 READ L3BANK31DATAPORT L3 READ L3BANK4DATAPORT L3 READ L3BANK5DATAPORT L3 READ L3BANK6DATAPORT L3 READ L3BANK7DATAPORT L3 READ L3BANK8DATAPORT L3 READ L3BANK9DATAPORT L3 WRITE L3BANK0DATAPORT L3 WRITE L3BANK1DATAPORT L3 WRITE L3BANK10DATAPORT L3 WRITE L3BANK11DATAPORT L3 WRITE L3BANK12DATAPORT L3 WRITE L3BANK13DATAPORT L3 WRITE L3BANK14DATAPORT L3 WRITE L3BANK15DATAPORT L3 WRITE L3BANK16DATAPORT L3 WRITE L3BANK17DATAPORT L3 WRITE L3BANK18DATAPORT L3 WRITE L3BANK19DATAPORT L3 WRITE L3BANK2DATAPORT L3 WRITE L3BANK20DATAPORT L3 WRITE L3BANK21DATAPORT L3 WRITE L3BANK22DATAPORT L3 WRITE L3BANK23DATAPORT L3 WRITE L3BANK24DATAPORT L3 WRITE L3BANK25DATAPORT L3 WRITE L3BANK26DATAPORT L3 WRITE L3BANK27DATAPORT L3 WRITE L3BANK28DATAPORT L3 WRITE L3BANK29DATAPORT L3 WRITE L3BANK3DATAPORT L3 WRITE L3BANK30DATAPORT L3 WRITE L3BANK31DATAPORT L3 WRITE L3BANK4DATAPORT L3 WRITE L3BANK5DATAPORT L3 WRITE L3BANK6DATAPORT L3 WRITE L3BANK7DATAPORT L3 WRITE L3BANK8DATAPORT L3 WRITE L3BANK9DATAPORT OUTPUT READY XECORE0DATAPORT OUTPUT READY XECORE1DATAPORT OUTPUT READY XECORE10DATAPORT OUTPUT READY XECORE11DATAPORT OUTPUT READY XECORE12DATAPORT OUTPUT READY XECORE13DATAPORT OUTPUT READY XECORE14DATAPORT OUTPUT READY XECORE15DATAPORT OUTPUT READY XECORE16DATAPORT OUTPUT READY XECORE17DATAPORT OUTPUT READY XECORE18DATAPORT OUTPUT READY XECORE19DATAPORT OUTPUT READY XECORE2DATAPORT OUTPUT READY XECORE20DATAPORT OUTPUT READY XECORE21DATAPORT OUTPUT READY XECORE22DATAPORT OUTPUT READY XECORE23DATAPORT OUTPUT READY XECORE24DATAPORT OUTPUT READY XECORE25DATAPORT OUTPUT READY XECORE26DATAPORT OUTPUT READY XECORE27DATAPORT OUTPUT READY XECORE28DATAPORT OUTPUT READY XECORE29DATAPORT OUTPUT READY XECORE3DATAPORT OUTPUT READY XECORE30DATAPORT OUTPUT READY XECORE31DATAPORT OUTPUT READY XECORE4DATAPORT OUTPUT READY XECORE5DATAPORT OUTPUT READY XECORE6DATAPORT OUTPUT READY XECORE7DATAPORT OUTPUT READY XECORE8DATAPORT OUTPUT READY XECORE9DATAPORT TEXTURE CACHE ACCESS XECORE0DATAPORT TEXTURE CACHE ACCESS XECORE1DATAPORT TEXTURE CACHE ACCESS XECORE10DATAPORT TEXTURE CACHE ACCESS XECORE11DATAPORT TEXTURE CACHE ACCESS XECORE12DATAPORT TEXTURE CACHE ACCESS XECORE13DATAPORT TEXTURE CACHE ACCESS XECORE14DATAPORT TEXTURE CACHE ACCESS XECORE15DATAPORT TEXTURE CACHE ACCESS XECORE16DATAPORT TEXTURE CACHE ACCESS XECORE17DATAPORT TEXTURE CACHE ACCESS XECORE18DATAPORT TEXTURE CACHE ACCESS XECORE19DATAPORT TEXTURE CACHE ACCESS XECORE2DATAPORT TEXTURE CACHE ACCESS XECORE20DATAPORT TEXTURE CACHE ACCESS XECORE21DATAPORT TEXTURE CACHE ACCESS XECORE22DATAPORT TEXTURE CACHE ACCESS XECORE23DATAPORT TEXTURE CACHE ACCESS XECORE24DATAPORT TEXTURE CACHE ACCESS XECORE25DATAPORT TEXTURE CACHE ACCESS XECORE26DATAPORT TEXTURE CACHE ACCESS XECORE27DATAPORT TEXTURE CACHE ACCESS XECORE28DATAPORT TEXTURE CACHE ACCESS XECORE29DATAPORT TEXTURE CACHE ACCESS XECORE3DATAPORT TEXTURE CACHE ACCESS XECORE30DATAPORT TEXTURE CACHE ACCESS XECORE31DATAPORT TEXTURE CACHE ACCESS XECORE4DATAPORT TEXTURE CACHE ACCESS XECORE5DATAPORT TEXTURE CACHE ACCESS XECORE6DATAPORT TEXTURE CACHE ACCESS XECORE7DATAPORT TEXTURE CACHE ACCESS XECORE8DATAPORT TEXTURE CACHE ACCESS XECORE9DATAPORT TEXTURE CACHE HIT XECORE0DATAPORT TEXTURE CACHE HIT XECORE1DATAPORT TEXTURE CACHE HIT XECORE10DATAPORT TEXTURE CACHE HIT XECORE11DATAPORT TEXTURE CACHE HIT XECORE12DATAPORT TEXTURE CACHE HIT XECORE13DATAPORT TEXTURE CACHE HIT XECORE14DATAPORT TEXTURE CACHE HIT XECORE15DATAPORT TEXTURE CACHE HIT XECORE16DATAPORT TEXTURE CACHE HIT XECORE17DATAPORT TEXTURE CACHE HIT XECORE18DATAPORT TEXTURE CACHE HIT XECORE19DATAPORT TEXTURE CACHE HIT XECORE2DATAPORT TEXTURE CACHE HIT XECORE20DATAPORT TEXTURE CACHE HIT XECORE21DATAPORT TEXTURE CACHE HIT XECORE22DATAPORT TEXTURE CACHE HIT XECORE23DATAPORT TEXTURE CACHE HIT XECORE24DATAPORT TEXTURE CACHE HIT XECORE25DATAPORT TEXTURE CACHE HIT XECORE26DATAPORT TEXTURE CACHE HIT XECORE27DATAPORT TEXTURE CACHE HIT XECORE28DATAPORT TEXTURE CACHE HIT XECORE29DATAPORT TEXTURE CACHE HIT XECORE3DATAPORT TEXTURE CACHE HIT XECORE30DATAPORT TEXTURE CACHE HIT XECORE31DATAPORT TEXTURE CACHE HIT XECORE4DATAPORT TEXTURE CACHE HIT XECORE5DATAPORT TEXTURE CACHE HIT XECORE6DATAPORT TEXTURE CACHE HIT XECORE7DATAPORT TEXTURE CACHE HIT XECORE8DATAPORT TEXTURE CACHE HIT XECORE9DS BottleneckDS EM Pipe ActiveDS FPU Pipe ActiveDS Send Pipe ActiveDS StallDS Threads DispatchedDS0 BottleneckDS0 StallDS1 BottleneckDS1 StallDS2 BottleneckDS2 StallDS3 BottleneckDS3 StallDS4 BottleneckDS4 StallDS5 BottleneckDS5 StallDS6 BottleneckDS6 StallDS7 BottleneckDS7 StallData Port 0 to L3 Data ReadsData Port 0 to L3 Data WritesEARLY DEPTH STENCIL TEST FAIL NP ZPIPE0EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1EARLY DEPTH STENCIL TEST FAIL NP ZPIPE10EARLY DEPTH STENCIL TEST FAIL NP ZPIPE11EARLY DEPTH STENCIL TEST FAIL NP ZPIPE12EARLY DEPTH STENCIL TEST FAIL NP ZPIPE13EARLY DEPTH STENCIL TEST FAIL NP ZPIPE14EARLY DEPTH STENCIL TEST FAIL NP ZPIPE15EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3EARLY DEPTH STENCIL TEST FAIL NP ZPIPE4EARLY DEPTH STENCIL TEST FAIL NP ZPIPE5EARLY DEPTH STENCIL TEST FAIL NP ZPIPE6EARLY DEPTH STENCIL TEST FAIL NP ZPIPE7EARLY DEPTH STENCIL TEST FAIL NP ZPIPE8EARLY DEPTH STENCIL TEST FAIL NP ZPIPE9EARLY DEPTH STENCIL TEST FAIL P ZPIPE0EARLY DEPTH STENCIL TEST FAIL P ZPIPE1EARLY DEPTH STENCIL TEST FAIL P ZPIPE10EARLY DEPTH STENCIL TEST FAIL P ZPIPE11EARLY DEPTH STENCIL TEST FAIL P ZPIPE12EARLY DEPTH STENCIL TEST FAIL P ZPIPE13EARLY DEPTH STENCIL TEST FAIL P ZPIPE14EARLY DEPTH STENCIL TEST FAIL P ZPIPE15EARLY DEPTH STENCIL TEST FAIL P ZPIPE2EARLY DEPTH STENCIL TEST FAIL P ZPIPE3EARLY DEPTH STENCIL TEST FAIL P ZPIPE4EARLY DEPTH STENCIL TEST FAIL P ZPIPE5EARLY DEPTH STENCIL TEST FAIL P ZPIPE6EARLY DEPTH STENCIL TEST FAIL P ZPIPE7EARLY DEPTH STENCIL TEST FAIL P ZPIPE8EARLY DEPTH STENCIL TEST FAIL P ZPIPE9EM And FPU Pipes ActiveEM Pipe ActiveEU AVG IPC RateEU ActiveEU Both FPU Pipes ActiveEU FPU And EM Pipes ActiveEU FPU Pipe ActiveEU FPU0 Binary InstructionEU FPU0 Hybrid InstructionEU FPU0 Move InstructionEU FPU0 Pipe ActiveEU FPU0 Ternary InstructionEU FPU1 Binary InstructionEU FPU1 Hybrid InstructionEU FPU1 Move InstructionEU FPU1 Pipe ActiveEU FPU1 Pipe Active including Ext MathEU FPU1 Ternary InstructionEU IdleEU Send Pipe ActiveEU StallEU Thread OccupancyEU to Data Port 0 Reads 128EU to Data Port 0 Reads 256EU to Data Port 0 Reads 32EU to Data Port 0 Reads 64EU to Data Port 0 Writes 128EU to Data Port 0 Writes 256BEU to Data Port 0 Writes 32BEU to Data Port 0 Writes 64BEarly Depth BottleneckEarly Depth Test FailsEarly Hi-Depth Test FailsEu 64 Untyped Reads 00Eu A32 Untyped Reads 00Eu A32 Untyped Writes 00Eu A64 Untyped Writes 00Eu Typed Atomics 00Eu Typed Reads 00Eu Typed Writes 00EuA64UntypedReads0EuA64UntypedWrites0EuBytesReadPerCacheLineEuBytesWrittenPerCacheLineEuDataReadsPerCacheLineEuDataWritesPerCacheLineEuTypedAtomics0EuTypedReads0EuTypedWrites0EuUntypedAtomics0EuUntypedReads0EuUntypedWrites0EuUrbAtomics0FPU FLT16 InstructionFPU FLT32 InstructionFPU FLT64 InstructionFS AVG Active per ThreadFS AVG Stall per ThreadFS Both FPU ActiveFS DurationFS EM Pipe ActiveFS EU ActiveFS EU StallFS FPU Pipe ActiveFS Send Pipe ActiveFS Threads DispatchedGPGPU DISPATCH XECORE0GPGPU DISPATCH XECORE1GPGPU DISPATCH XECORE10GPGPU DISPATCH XECORE11GPGPU DISPATCH XECORE12GPGPU DISPATCH XECORE13GPGPU DISPATCH XECORE14GPGPU DISPATCH XECORE15GPGPU DISPATCH XECORE16GPGPU DISPATCH XECORE17GPGPU DISPATCH XECORE18GPGPU DISPATCH XECORE19GPGPU DISPATCH XECORE2GPGPU DISPATCH XECORE20GPGPU DISPATCH XECORE21GPGPU DISPATCH XECORE22GPGPU DISPATCH XECORE23GPGPU DISPATCH XECORE24GPGPU DISPATCH XECORE25GPGPU DISPATCH XECORE26GPGPU DISPATCH XECORE27GPGPU DISPATCH XECORE28GPGPU DISPATCH XECORE29GPGPU DISPATCH XECORE3GPGPU DISPATCH XECORE30GPGPU DISPATCH XECORE31GPGPU DISPATCH XECORE4GPGPU DISPATCH XECORE5GPGPU DISPATCH XECORE6GPGPU DISPATCH XECORE7GPGPU DISPATCH XECORE8GPGPU DISPATCH XECORE9GPGPU THREADGROUP COUNT XECORE0GPGPU THREADGROUP COUNT XECORE1GPGPU THREADGROUP COUNT XECORE10GPGPU THREADGROUP COUNT XECORE11GPGPU THREADGROUP COUNT XECORE12GPGPU THREADGROUP COUNT XECORE13GPGPU THREADGROUP COUNT XECORE14GPGPU THREADGROUP COUNT XECORE15GPGPU THREADGROUP COUNT XECORE16GPGPU THREADGROUP COUNT XECORE17GPGPU THREADGROUP COUNT XECORE18GPGPU THREADGROUP COUNT XECORE19GPGPU THREADGROUP COUNT XECORE2GPGPU THREADGROUP COUNT XECORE20GPGPU THREADGROUP COUNT XECORE21GPGPU THREADGROUP COUNT XECORE22GPGPU THREADGROUP COUNT XECORE23GPGPU THREADGROUP COUNT XECORE24GPGPU THREADGROUP COUNT XECORE25GPGPU THREADGROUP COUNT XECORE26GPGPU THREADGROUP COUNT XECORE27GPGPU THREADGROUP COUNT XECORE28GPGPU THREADGROUP COUNT XECORE29GPGPU THREADGROUP COUNT XECORE3GPGPU THREADGROUP COUNT XECORE30GPGPU THREADGROUP COUNT XECORE31GPGPU THREADGROUP COUNT XECORE4GPGPU THREADGROUP COUNT XECORE5GPGPU THREADGROUP COUNT XECORE6GPGPU THREADGROUP COUNT XECORE7GPGPU THREADGROUP COUNT XECORE8GPGPU THREADGROUP COUNT XECORE9GPU BusyGPU Core ClocksGPU MEMORY 32B TRANSACTION READGPU MEMORY 32B TRANSACTION READ SQIDI0GPU MEMORY 32B TRANSACTION READ SQIDI1GPU MEMORY 32B TRANSACTION READ SQIDI2GPU MEMORY 32B TRANSACTION READ SQIDI3GPU MEMORY 32B TRANSACTION READ SQIDI4GPU MEMORY 32B TRANSACTION READ SQIDI5GPU MEMORY 32B TRANSACTION READ SQIDI6GPU MEMORY 32B TRANSACTION READ SQIDI7GPU MEMORY 32B TRANSACTION WRITEGPU MEMORY 32B TRANSACTION WRITE SQIDI0GPU MEMORY 32B TRANSACTION WRITE SQIDI1GPU MEMORY 32B TRANSACTION WRITE SQIDI2GPU MEMORY 32B TRANSACTION WRITE SQIDI3GPU MEMORY 32B TRANSACTION WRITE SQIDI4GPU MEMORY 32B TRANSACTION WRITE SQIDI5GPU MEMORY 32B TRANSACTION WRITE SQIDI6GPU MEMORY 32B TRANSACTION WRITE SQIDI7GPU MEMORY 64B TRANSACTION READGPU MEMORY 64B TRANSACTION READ SQIDI0GPU MEMORY 64B TRANSACTION READ SQIDI1GPU MEMORY 64B TRANSACTION READ SQIDI2GPU MEMORY 64B TRANSACTION READ SQIDI3GPU MEMORY 64B TRANSACTION READ SQIDI4GPU MEMORY 64B TRANSACTION READ SQIDI5GPU MEMORY 64B TRANSACTION READ SQIDI6GPU MEMORY 64B TRANSACTION READ SQIDI7GPU MEMORY 64B TRANSACTION WRITEGPU MEMORY 64B TRANSACTION WRITE SQIDI0GPU MEMORY 64B TRANSACTION WRITE SQIDI1GPU MEMORY 64B TRANSACTION WRITE SQIDI2GPU MEMORY 64B TRANSACTION WRITE SQIDI3GPU MEMORY 64B TRANSACTION WRITE SQIDI4GPU MEMORY 64B TRANSACTION WRITE SQIDI5GPU MEMORY 64B TRANSACTION WRITE SQIDI6GPU MEMORY 64B TRANSACTION WRITE SQIDI7GPU MEMORY ACTIVEGPU MEMORY ACTIVE SQIDI0GPU MEMORY ACTIVE SQIDI1GPU MEMORY ACTIVE SQIDI2GPU MEMORY ACTIVE SQIDI3GPU MEMORY ACTIVE SQIDI4GPU MEMORY ACTIVE SQIDI5GPU MEMORY ACTIVE SQIDI6GPU MEMORY ACTIVE SQIDI7GPU MEMORY BYTE READGPU MEMORY BYTE READ BWGPU MEMORY BYTE READ BW SQIDI0GPU MEMORY BYTE READ BW SQIDI1GPU MEMORY BYTE READ BW SQIDI2GPU MEMORY BYTE READ BW SQIDI3GPU MEMORY BYTE READ BW SQIDI4GPU MEMORY BYTE READ BW SQIDI5GPU MEMORY BYTE READ BW SQIDI6GPU MEMORY BYTE READ BW SQIDI7GPU MEMORY BYTE READ SQIDI0GPU MEMORY BYTE READ SQIDI1GPU MEMORY BYTE READ SQIDI2GPU MEMORY BYTE READ SQIDI3GPU MEMORY BYTE READ SQIDI4GPU MEMORY BYTE READ SQIDI5GPU MEMORY BYTE READ SQIDI6GPU MEMORY BYTE READ SQIDI7GPU MEMORY BYTE WRITEGPU MEMORY BYTE WRITE BWGPU MEMORY BYTE WRITE BW SQIDI0GPU MEMORY BYTE WRITE BW SQIDI1GPU MEMORY BYTE WRITE BW SQIDI2GPU MEMORY BYTE WRITE BW SQIDI3GPU MEMORY BYTE WRITE BW SQIDI4GPU MEMORY BYTE WRITE BW SQIDI5GPU MEMORY BYTE WRITE BW SQIDI6GPU MEMORY BYTE WRITE BW SQIDI7GPU MEMORY BYTE WRITE SQIDI0GPU MEMORY BYTE WRITE SQIDI1GPU MEMORY BYTE WRITE SQIDI2GPU MEMORY BYTE WRITE SQIDI3GPU MEMORY BYTE WRITE SQIDI4GPU MEMORY BYTE WRITE SQIDI5GPU MEMORY BYTE WRITE SQIDI6GPU MEMORY BYTE WRITE SQIDI7GPU MEMORY L3 READ SQIDI0GPU MEMORY L3 READ SQIDI1GPU MEMORY L3 READ SQIDI2GPU MEMORY L3 READ SQIDI3GPU MEMORY L3 READ SQIDI4GPU MEMORY L3 READ SQIDI5GPU MEMORY L3 READ SQIDI6GPU MEMORY L3 READ SQIDI7GPU MEMORY L3 WRITE SQIDI0GPU MEMORY L3 WRITE SQIDI1GPU MEMORY L3 WRITE SQIDI2GPU MEMORY L3 WRITE SQIDI3GPU MEMORY L3 WRITE SQIDI4GPU MEMORY L3 WRITE SQIDI5GPU MEMORY L3 WRITE SQIDI6GPU MEMORY L3 WRITE SQIDI7GPU MEMORY READGPU MEMORY READ SQIDI0GPU MEMORY READ SQIDI1GPU MEMORY READ SQIDI2GPU MEMORY READ SQIDI3GPU MEMORY READ SQIDI4GPU MEMORY READ SQIDI5GPU MEMORY READ SQIDI6GPU MEMORY READ SQIDI7GPU MEMORY REQUEST QUEUE FULLGPU MEMORY REQUEST QUEUE FULL SQIDI0GPU MEMORY REQUEST QUEUE FULL SQIDI1GPU MEMORY REQUEST QUEUE FULL SQIDI2GPU MEMORY REQUEST QUEUE FULL SQIDI3GPU MEMORY REQUEST QUEUE FULL SQIDI4GPU MEMORY REQUEST QUEUE FULL SQIDI5GPU MEMORY REQUEST QUEUE FULL SQIDI6GPU MEMORY REQUEST QUEUE FULL SQIDI7GPU MEMORY WRITEGPU MEMORY WRITE SQIDI0GPU MEMORY WRITE SQIDI1GPU MEMORY WRITE SQIDI2GPU MEMORY WRITE SQIDI3GPU MEMORY WRITE SQIDI4GPU MEMORY WRITE SQIDI5GPU MEMORY WRITE SQIDI6GPU MEMORY WRITE SQIDI7GPU Time ElapsedGS AVG Active per ThreadGS AVG Stall per ThreadGS BottleneckGS DurationGS EM Pipe ActiveGS EU ActiveGS EU StallGS FPU Pipe ActiveGS Send Pipe ActiveGS Threads DispatchedGS0 BottleneckGS1 BottleneckGS2 BottleneckGS3 BottleneckGS4 BottleneckGS5 BottleneckGS6 BottleneckGS7 BottleneckGTI Depth ThroughputGTI Fixed Pipe ThroughputGTI HDC TLB Lookup ThroughputGTI L3 ThroughputGTI RCC ThroughputGTI Read ThroughputGTI Read-Only StallGTI Read-Write StallGTI Ring ThroughputGTI Write ThroughputGtiCmdStreamerMemoryReadsGtiCmdStreamerMemoryWritesGtiHiDepthMemoryReadsGtiHizMemoryReadsGtiHizMemoryWritesGtiL3Bank0ReadsGtiL3Bank0WritesGtiL3Bank1ReadsGtiL3Bank1WritesGtiL3Bank2ReadsGtiL3Bank2WritesGtiL3Bank3ReadsGtiL3Bank3WritesGtiL3ReadsGtiL3WritesGtiMemoryReadsGtiMemoryWritesGtiMscMemoryReadsGtiMscMemoryWritesGtiRccMemoryReadsGtiRccMemoryWritesGtiRczMemoryReadsGtiRczMemoryWritesGtiRingAccessesGtiRsMemoryReadsGtiSoMemoryWritesGtiStcMemoryReadsGtiStcMemoryWritesGtiVfMemoryReadsHDC stalled by L3 (s0.ss0)HDC stalled by L3 (s0.ss1)HDC stalled by L3 (s0.ss2)HIZ DEPTH TEST AMBIG NP ZPIPE0HIZ DEPTH TEST AMBIG NP ZPIPE1HIZ DEPTH TEST AMBIG NP ZPIPE10HIZ DEPTH TEST AMBIG NP ZPIPE11HIZ DEPTH TEST AMBIG NP ZPIPE12HIZ DEPTH TEST AMBIG NP ZPIPE13HIZ DEPTH TEST AMBIG NP ZPIPE14HIZ DEPTH TEST AMBIG NP ZPIPE15HIZ DEPTH TEST AMBIG NP ZPIPE2HIZ DEPTH TEST AMBIG NP ZPIPE3HIZ DEPTH TEST AMBIG NP ZPIPE4HIZ DEPTH TEST AMBIG NP ZPIPE5HIZ DEPTH TEST AMBIG NP ZPIPE6HIZ DEPTH TEST AMBIG NP ZPIPE7HIZ DEPTH TEST AMBIG NP ZPIPE8HIZ DEPTH TEST AMBIG NP ZPIPE9HIZ DEPTH TEST AMBIG P ZPIPE0HIZ DEPTH TEST AMBIG P ZPIPE1HIZ DEPTH TEST AMBIG P ZPIPE10HIZ DEPTH TEST AMBIG P ZPIPE11HIZ DEPTH TEST AMBIG P ZPIPE12HIZ DEPTH TEST AMBIG P ZPIPE13HIZ DEPTH TEST AMBIG P ZPIPE14HIZ DEPTH TEST AMBIG P ZPIPE15HIZ DEPTH TEST AMBIG P ZPIPE2HIZ DEPTH TEST AMBIG P ZPIPE3HIZ DEPTH TEST AMBIG P ZPIPE4HIZ DEPTH TEST AMBIG P ZPIPE5HIZ DEPTH TEST AMBIG P ZPIPE6HIZ DEPTH TEST AMBIG P ZPIPE7HIZ DEPTH TEST AMBIG P ZPIPE8HIZ DEPTH TEST AMBIG P ZPIPE9HIZ DEPTH TEST FAIL NP ZPIPE0HIZ DEPTH TEST FAIL NP ZPIPE1HIZ DEPTH TEST FAIL NP ZPIPE10HIZ DEPTH TEST FAIL NP ZPIPE11HIZ DEPTH TEST FAIL NP ZPIPE12HIZ DEPTH TEST FAIL NP ZPIPE13HIZ DEPTH TEST FAIL NP ZPIPE14HIZ DEPTH TEST FAIL NP ZPIPE15HIZ DEPTH TEST FAIL NP ZPIPE2HIZ DEPTH TEST FAIL NP ZPIPE3HIZ DEPTH TEST FAIL NP ZPIPE4HIZ DEPTH TEST FAIL NP ZPIPE5HIZ DEPTH TEST FAIL NP ZPIPE6HIZ DEPTH TEST FAIL NP ZPIPE7HIZ DEPTH TEST FAIL NP ZPIPE8HIZ DEPTH TEST FAIL NP ZPIPE9HIZ DEPTH TEST FAIL P ZPIPE0HIZ DEPTH TEST FAIL P ZPIPE1HIZ DEPTH TEST FAIL P ZPIPE10HIZ DEPTH TEST FAIL P ZPIPE11HIZ DEPTH TEST FAIL P ZPIPE12HIZ DEPTH TEST FAIL P ZPIPE13HIZ DEPTH TEST FAIL P ZPIPE14HIZ DEPTH TEST FAIL P ZPIPE15HIZ DEPTH TEST FAIL P ZPIPE2HIZ DEPTH TEST FAIL P ZPIPE3HIZ DEPTH TEST FAIL P ZPIPE4HIZ DEPTH TEST FAIL P ZPIPE5HIZ DEPTH TEST FAIL P ZPIPE6HIZ DEPTH TEST FAIL P ZPIPE7HIZ DEPTH TEST FAIL P ZPIPE8HIZ DEPTH TEST FAIL P ZPIPE9HIZ DEPTH TEST PASS P ZPIPE0HIZ DEPTH TEST PASS P ZPIPE1HIZ DEPTH TEST PASS P ZPIPE10HIZ DEPTH TEST PASS P ZPIPE11HIZ DEPTH TEST PASS P ZPIPE12HIZ DEPTH TEST PASS P ZPIPE13HIZ DEPTH TEST PASS P ZPIPE14HIZ DEPTH TEST PASS P ZPIPE15HIZ DEPTH TEST PASS P ZPIPE2HIZ DEPTH TEST PASS P ZPIPE3HIZ DEPTH TEST PASS P ZPIPE4HIZ DEPTH TEST PASS P ZPIPE5HIZ DEPTH TEST PASS P ZPIPE6HIZ DEPTH TEST PASS P ZPIPE7HIZ DEPTH TEST PASS P ZPIPE8HIZ DEPTH TEST PASS P ZPIPE9HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1HIZ SUBSPAN LATENCY FIFOFULL ZPIPE10HIZ SUBSPAN LATENCY FIFOFULL ZPIPE11HIZ SUBSPAN LATENCY FIFOFULL ZPIPE12HIZ SUBSPAN LATENCY FIFOFULL ZPIPE13HIZ SUBSPAN LATENCY FIFOFULL ZPIPE14HIZ SUBSPAN LATENCY FIFOFULL ZPIPE15HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3HIZ SUBSPAN LATENCY FIFOFULL ZPIPE4HIZ SUBSPAN LATENCY FIFOFULL ZPIPE5HIZ SUBSPAN LATENCY FIFOFULL ZPIPE6HIZ SUBSPAN LATENCY FIFOFULL ZPIPE7HIZ SUBSPAN LATENCY FIFOFULL ZPIPE8HIZ SUBSPAN LATENCY FIFOFULL ZPIPE9HOST TO GPUMEM BYTE READHOST TO GPUMEM BYTE WRITEHOST TO GPUMEM TRANSACTION READHOST TO GPUMEM TRANSACTION WRITEHS BottleneckHS EM Pipe ActiveHS FPU Pipe ActiveHS Send Pipe ActiveHS StallHS Threads DispatchedHS0 BottleneckHS0 StallHS1 BottleneckHS1 StallHS2 BottleneckHS2 StallHS3 BottleneckHS3 StallHS4 BottleneckHS4 StallHS5 BottleneckHS5 StallHS6 BottleneckHS6 StallHS7 BottleneckHS7 StallHi-Depth BottleneckHi-Depth00 BottleneckHi-Depth01 BottleneckHi-Depth10 BottleneckHi-Depth11 BottleneckHi-Depth20 BottleneckHi-Depth30 BottleneckHi-Depth40 BottleneckHi-Depth50 BottleneckHi-Depth60 BottleneckHi-Depth70 BottleneckICACHE HIT BANK0 XECORE0ICACHE HIT BANK0 XECORE1ICACHE HIT BANK0 XECORE10ICACHE HIT BANK0 XECORE11ICACHE HIT BANK0 XECORE12ICACHE HIT BANK0 XECORE13ICACHE HIT BANK0 XECORE14ICACHE HIT BANK0 XECORE15ICACHE HIT BANK0 XECORE16ICACHE HIT BANK0 XECORE17ICACHE HIT BANK0 XECORE18ICACHE HIT BANK0 XECORE19ICACHE HIT BANK0 XECORE2ICACHE HIT BANK0 XECORE20ICACHE HIT BANK0 XECORE21ICACHE HIT BANK0 XECORE22ICACHE HIT BANK0 XECORE23ICACHE HIT BANK0 XECORE24ICACHE HIT BANK0 XECORE25ICACHE HIT BANK0 XECORE26ICACHE HIT BANK0 XECORE27ICACHE HIT BANK0 XECORE28ICACHE HIT BANK0 XECORE29ICACHE HIT BANK0 XECORE3ICACHE HIT BANK0 XECORE30ICACHE HIT BANK0 XECORE31ICACHE HIT BANK0 XECORE4ICACHE HIT BANK0 XECORE5ICACHE HIT BANK0 XECORE6ICACHE HIT BANK0 XECORE7ICACHE HIT BANK0 XECORE8ICACHE HIT BANK0 XECORE9ICACHE HIT BANK1 XECORE0ICACHE HIT BANK1 XECORE1ICACHE HIT BANK1 XECORE10ICACHE HIT BANK1 XECORE11ICACHE HIT BANK1 XECORE12ICACHE HIT BANK1 XECORE13ICACHE HIT BANK1 XECORE14ICACHE HIT BANK1 XECORE15ICACHE HIT BANK1 XECORE16ICACHE HIT BANK1 XECORE17ICACHE HIT BANK1 XECORE18ICACHE HIT BANK1 XECORE19ICACHE HIT BANK1 XECORE2ICACHE HIT BANK1 XECORE20ICACHE HIT BANK1 XECORE21ICACHE HIT BANK1 XECORE22ICACHE HIT BANK1 XECORE23ICACHE HIT BANK1 XECORE24ICACHE HIT BANK1 XECORE25ICACHE HIT BANK1 XECORE26ICACHE HIT BANK1 XECORE27ICACHE HIT BANK1 XECORE28ICACHE HIT BANK1 XECORE29ICACHE HIT BANK1 XECORE3ICACHE HIT BANK1 XECORE30ICACHE HIT BANK1 XECORE31ICACHE HIT BANK1 XECORE4ICACHE HIT BANK1 XECORE5ICACHE HIT BANK1 XECORE6ICACHE HIT BANK1 XECORE7ICACHE HIT BANK1 XECORE8ICACHE HIT BANK1 XECORE9ICACHE HIT BANK2 XECORE0ICACHE HIT BANK2 XECORE1ICACHE HIT BANK2 XECORE10ICACHE HIT BANK2 XECORE11ICACHE HIT BANK2 XECORE12ICACHE HIT BANK2 XECORE13ICACHE HIT BANK2 XECORE14ICACHE HIT BANK2 XECORE15ICACHE HIT BANK2 XECORE16ICACHE HIT BANK2 XECORE17ICACHE HIT BANK2 XECORE18ICACHE HIT BANK2 XECORE19ICACHE HIT BANK2 XECORE2ICACHE HIT BANK2 XECORE20ICACHE HIT BANK2 XECORE21ICACHE HIT BANK2 XECORE22ICACHE HIT BANK2 XECORE23ICACHE HIT BANK2 XECORE24ICACHE HIT BANK2 XECORE25ICACHE HIT BANK2 XECORE26ICACHE HIT BANK2 XECORE27ICACHE HIT BANK2 XECORE28ICACHE HIT BANK2 XECORE29ICACHE HIT BANK2 XECORE3ICACHE HIT BANK2 XECORE30ICACHE HIT BANK2 XECORE31ICACHE HIT BANK2 XECORE4ICACHE HIT BANK2 XECORE5ICACHE HIT BANK2 XECORE6ICACHE HIT BANK2 XECORE7ICACHE HIT BANK2 XECORE8ICACHE HIT BANK2 XECORE9ICACHE HIT BANK3 XECORE0ICACHE HIT BANK3 XECORE1ICACHE HIT BANK3 XECORE10ICACHE HIT BANK3 XECORE11ICACHE HIT BANK3 XECORE12ICACHE HIT BANK3 XECORE13ICACHE HIT BANK3 XECORE14ICACHE HIT BANK3 XECORE15ICACHE HIT BANK3 XECORE16ICACHE HIT BANK3 XECORE17ICACHE HIT BANK3 XECORE18ICACHE HIT BANK3 XECORE19ICACHE HIT BANK3 XECORE2ICACHE HIT BANK3 XECORE20ICACHE HIT BANK3 XECORE21ICACHE HIT BANK3 XECORE22ICACHE HIT BANK3 XECORE23ICACHE HIT BANK3 XECORE24ICACHE HIT BANK3 XECORE25ICACHE HIT BANK3 XECORE26ICACHE HIT BANK3 XECORE27ICACHE HIT BANK3 XECORE28ICACHE HIT BANK3 XECORE29ICACHE HIT BANK3 XECORE3ICACHE HIT BANK3 XECORE30ICACHE HIT BANK3 XECORE31ICACHE HIT BANK3 XECORE4ICACHE HIT BANK3 XECORE5ICACHE HIT BANK3 XECORE6ICACHE HIT BANK3 XECORE7ICACHE HIT BANK3 XECORE8ICACHE HIT BANK3 XECORE9ICACHE L3 HIT L3BANK0ICACHE L3 HIT L3BANK1ICACHE L3 HIT L3BANK10ICACHE L3 HIT L3BANK11ICACHE L3 HIT L3BANK12ICACHE L3 HIT L3BANK13ICACHE L3 HIT L3BANK14ICACHE L3 HIT L3BANK15ICACHE L3 HIT L3BANK16ICACHE L3 HIT L3BANK17ICACHE L3 HIT L3BANK18ICACHE L3 HIT L3BANK19ICACHE L3 HIT L3BANK2ICACHE L3 HIT L3BANK20ICACHE L3 HIT L3BANK21ICACHE L3 HIT L3BANK22ICACHE L3 HIT L3BANK23ICACHE L3 HIT L3BANK24ICACHE L3 HIT L3BANK25ICACHE L3 HIT L3BANK26ICACHE L3 HIT L3BANK27ICACHE L3 HIT L3BANK28ICACHE L3 HIT L3BANK29ICACHE L3 HIT L3BANK3ICACHE L3 HIT L3BANK30ICACHE L3 HIT L3BANK31ICACHE L3 HIT L3BANK4ICACHE L3 HIT L3BANK5ICACHE L3 HIT L3BANK6ICACHE L3 HIT L3BANK7ICACHE L3 HIT L3BANK8ICACHE L3 HIT L3BANK9ICACHE L3 READ L3BANK0ICACHE L3 READ L3BANK1ICACHE L3 READ L3BANK10ICACHE L3 READ L3BANK11ICACHE L3 READ L3BANK12ICACHE L3 READ L3BANK13ICACHE L3 READ L3BANK14ICACHE L3 READ L3BANK15ICACHE L3 READ L3BANK16ICACHE L3 READ L3BANK17ICACHE L3 READ L3BANK18ICACHE L3 READ L3BANK19ICACHE L3 READ L3BANK2ICACHE L3 READ L3BANK20ICACHE L3 READ L3BANK21ICACHE L3 READ L3BANK22ICACHE L3 READ L3BANK23ICACHE L3 READ L3BANK24ICACHE L3 READ L3BANK25ICACHE L3 READ L3BANK26ICACHE L3 READ L3BANK27ICACHE L3 READ L3BANK28ICACHE L3 READ L3BANK29ICACHE L3 READ L3BANK3ICACHE L3 READ L3BANK30ICACHE L3 READ L3BANK31ICACHE L3 READ L3BANK4ICACHE L3 READ L3BANK5ICACHE L3 READ L3BANK6ICACHE L3 READ L3BANK7ICACHE L3 READ L3BANK8ICACHE L3 READ L3BANK9ICACHE MISS BANK0 XECORE0ICACHE MISS BANK0 XECORE1ICACHE MISS BANK0 XECORE10ICACHE MISS BANK0 XECORE11ICACHE MISS BANK0 XECORE12ICACHE MISS BANK0 XECORE13ICACHE MISS BANK0 XECORE14ICACHE MISS BANK0 XECORE15ICACHE MISS BANK0 XECORE16ICACHE MISS BANK0 XECORE17ICACHE MISS BANK0 XECORE18ICACHE MISS BANK0 XECORE19ICACHE MISS BANK0 XECORE2ICACHE MISS BANK0 XECORE20ICACHE MISS BANK0 XECORE21ICACHE MISS BANK0 XECORE22ICACHE MISS BANK0 XECORE23ICACHE MISS BANK0 XECORE24ICACHE MISS BANK0 XECORE25ICACHE MISS BANK0 XECORE26ICACHE MISS BANK0 XECORE27ICACHE MISS BANK0 XECORE28ICACHE MISS BANK0 XECORE29ICACHE MISS BANK0 XECORE3ICACHE MISS BANK0 XECORE30ICACHE MISS BANK0 XECORE31ICACHE MISS BANK0 XECORE4ICACHE MISS BANK0 XECORE5ICACHE MISS BANK0 XECORE6ICACHE MISS BANK0 XECORE7ICACHE MISS BANK0 XECORE8ICACHE MISS BANK0 XECORE9ICACHE MISS BANK1 XECORE0ICACHE MISS BANK1 XECORE1ICACHE MISS BANK1 XECORE10ICACHE MISS BANK1 XECORE11ICACHE MISS BANK1 XECORE12ICACHE MISS BANK1 XECORE13ICACHE MISS BANK1 XECORE14ICACHE MISS BANK1 XECORE15ICACHE MISS BANK1 XECORE16ICACHE MISS BANK1 XECORE17ICACHE MISS BANK1 XECORE18ICACHE MISS BANK1 XECORE19ICACHE MISS BANK1 XECORE2ICACHE MISS BANK1 XECORE20ICACHE MISS BANK1 XECORE21ICACHE MISS BANK1 XECORE22ICACHE MISS BANK1 XECORE23ICACHE MISS BANK1 XECORE24ICACHE MISS BANK1 XECORE25ICACHE MISS BANK1 XECORE26ICACHE MISS BANK1 XECORE27ICACHE MISS BANK1 XECORE28ICACHE MISS BANK1 XECORE29ICACHE MISS BANK1 XECORE3ICACHE MISS BANK1 XECORE30ICACHE MISS BANK1 XECORE31ICACHE MISS BANK1 XECORE4ICACHE MISS BANK1 XECORE5ICACHE MISS BANK1 XECORE6ICACHE MISS BANK1 XECORE7ICACHE MISS BANK1 XECORE8ICACHE MISS BANK1 XECORE9ICACHE MISS BANK2 XECORE0ICACHE MISS BANK2 XECORE1ICACHE MISS BANK2 XECORE10ICACHE MISS BANK2 XECORE11ICACHE MISS BANK2 XECORE12ICACHE MISS BANK2 XECORE13ICACHE MISS BANK2 XECORE14ICACHE MISS BANK2 XECORE15ICACHE MISS BANK2 XECORE16ICACHE MISS BANK2 XECORE17ICACHE MISS BANK2 XECORE18ICACHE MISS BANK2 XECORE19ICACHE MISS BANK2 XECORE2ICACHE MISS BANK2 XECORE20ICACHE MISS BANK2 XECORE21ICACHE MISS BANK2 XECORE22ICACHE MISS BANK2 XECORE23ICACHE MISS BANK2 XECORE24ICACHE MISS BANK2 XECORE25ICACHE MISS BANK2 XECORE26ICACHE MISS BANK2 XECORE27ICACHE MISS BANK2 XECORE28ICACHE MISS BANK2 XECORE29ICACHE MISS BANK2 XECORE3ICACHE MISS BANK2 XECORE30ICACHE MISS BANK2 XECORE31ICACHE MISS BANK2 XECORE4ICACHE MISS BANK2 XECORE5ICACHE MISS BANK2 XECORE6ICACHE MISS BANK2 XECORE7ICACHE MISS BANK2 XECORE8ICACHE MISS BANK2 XECORE9ICACHE MISS BANK3 XECORE0ICACHE MISS BANK3 XECORE1ICACHE MISS BANK3 XECORE10ICACHE MISS BANK3 XECORE11ICACHE MISS BANK3 XECORE12ICACHE MISS BANK3 XECORE13ICACHE MISS BANK3 XECORE14ICACHE MISS BANK3 XECORE15ICACHE MISS BANK3 XECORE16ICACHE MISS BANK3 XECORE17ICACHE MISS BANK3 XECORE18ICACHE MISS BANK3 XECORE19ICACHE MISS BANK3 XECORE2ICACHE MISS BANK3 XECORE20ICACHE MISS BANK3 XECORE21ICACHE MISS BANK3 XECORE22ICACHE MISS BANK3 XECORE23ICACHE MISS BANK3 XECORE24ICACHE MISS BANK3 XECORE25ICACHE MISS BANK3 XECORE26ICACHE MISS BANK3 XECORE27ICACHE MISS BANK3 XECORE28ICACHE MISS BANK3 XECORE29ICACHE MISS BANK3 XECORE3ICACHE MISS BANK3 XECORE30ICACHE MISS BANK3 XECORE31ICACHE MISS BANK3 XECORE4ICACHE MISS BANK3 XECORE5ICACHE MISS BANK3 XECORE6ICACHE MISS BANK3 XECORE7ICACHE MISS BANK3 XECORE8ICACHE MISS BANK3 XECORE9IZ OUTPUT READY ZPIPE0IZ OUTPUT READY ZPIPE1IZ OUTPUT READY ZPIPE10IZ OUTPUT READY ZPIPE11IZ OUTPUT READY ZPIPE12IZ OUTPUT READY ZPIPE13IZ OUTPUT READY ZPIPE14IZ OUTPUT READY ZPIPE15IZ OUTPUT READY ZPIPE2IZ OUTPUT READY ZPIPE3IZ OUTPUT READY ZPIPE4IZ OUTPUT READY ZPIPE5IZ OUTPUT READY ZPIPE6IZ OUTPUT READY ZPIPE7IZ OUTPUT READY ZPIPE8IZ OUTPUT READY ZPIPE9IZ SUBSPAN LATENCY FIFOFULL ZPIPE0IZ SUBSPAN LATENCY FIFOFULL ZPIPE1IZ SUBSPAN LATENCY FIFOFULL ZPIPE10IZ SUBSPAN LATENCY FIFOFULL ZPIPE11IZ SUBSPAN LATENCY FIFOFULL ZPIPE12IZ SUBSPAN LATENCY FIFOFULL ZPIPE13IZ SUBSPAN LATENCY FIFOFULL ZPIPE14IZ SUBSPAN LATENCY FIFOFULL ZPIPE15IZ SUBSPAN LATENCY FIFOFULL ZPIPE2IZ SUBSPAN LATENCY FIFOFULL ZPIPE3IZ SUBSPAN LATENCY FIFOFULL ZPIPE4IZ SUBSPAN LATENCY FIFOFULL ZPIPE5IZ SUBSPAN LATENCY FIFOFULL ZPIPE6IZ SUBSPAN LATENCY FIFOFULL ZPIPE7IZ SUBSPAN LATENCY FIFOFULL ZPIPE8IZ SUBSPAN LATENCY FIFOFULL ZPIPE9L3 ATOMIC ACCESS L3BANK0L3 ATOMIC ACCESS L3BANK1L3 ATOMIC ACCESS L3BANK10L3 ATOMIC ACCESS L3BANK11L3 ATOMIC ACCESS L3BANK12L3 ATOMIC ACCESS L3BANK13L3 ATOMIC ACCESS L3BANK14L3 ATOMIC ACCESS L3BANK15L3 ATOMIC ACCESS L3BANK16L3 ATOMIC ACCESS L3BANK17L3 ATOMIC ACCESS L3BANK18L3 ATOMIC ACCESS L3BANK19L3 ATOMIC ACCESS L3BANK2L3 ATOMIC ACCESS L3BANK20L3 ATOMIC ACCESS L3BANK21L3 ATOMIC ACCESS L3BANK22L3 ATOMIC ACCESS L3BANK23L3 ATOMIC ACCESS L3BANK24L3 ATOMIC ACCESS L3BANK25L3 ATOMIC ACCESS L3BANK26L3 ATOMIC ACCESS L3BANK27L3 ATOMIC ACCESS L3BANK28L3 ATOMIC ACCESS L3BANK29L3 ATOMIC ACCESS L3BANK3L3 ATOMIC ACCESS L3BANK30L3 ATOMIC ACCESS L3BANK31L3 ATOMIC ACCESS L3BANK4L3 ATOMIC ACCESS L3BANK5L3 ATOMIC ACCESS L3BANK6L3 ATOMIC ACCESS L3BANK7L3 ATOMIC ACCESS L3BANK8L3 ATOMIC ACCESS L3BANK9L3 AccessesL3 BANK ACTIVE L3BANK0L3 BANK ACTIVE L3BANK1L3 BANK ACTIVE L3BANK10L3 BANK ACTIVE L3BANK11L3 BANK ACTIVE L3BANK12L3 BANK ACTIVE L3BANK13L3 BANK ACTIVE L3BANK14L3 BANK ACTIVE L3BANK15L3 BANK ACTIVE L3BANK16L3 BANK ACTIVE L3BANK17L3 BANK ACTIVE L3BANK18L3 BANK ACTIVE L3BANK19L3 BANK ACTIVE L3BANK2L3 BANK ACTIVE L3BANK20L3 BANK ACTIVE L3BANK21L3 BANK ACTIVE L3BANK22L3 BANK ACTIVE L3BANK23L3 BANK ACTIVE L3BANK24L3 BANK ACTIVE L3BANK25L3 BANK ACTIVE L3BANK26L3 BANK ACTIVE L3BANK27L3 BANK ACTIVE L3BANK28L3 BANK ACTIVE L3BANK29L3 BANK ACTIVE L3BANK3L3 BANK ACTIVE L3BANK30L3 BANK ACTIVE L3BANK31L3 BANK ACTIVE L3BANK4L3 BANK ACTIVE L3BANK5L3 BANK ACTIVE L3BANK6L3 BANK ACTIVE L3BANK7L3 BANK ACTIVE L3BANK8L3 BANK ACTIVE L3BANK9L3 BANK INPUT AVAILABLE L3BANK0L3 BANK INPUT AVAILABLE L3BANK1L3 BANK INPUT AVAILABLE L3BANK10L3 BANK INPUT AVAILABLE L3BANK11L3 BANK INPUT AVAILABLE L3BANK12L3 BANK INPUT AVAILABLE L3BANK13L3 BANK INPUT AVAILABLE L3BANK14L3 BANK INPUT AVAILABLE L3BANK15L3 BANK INPUT AVAILABLE L3BANK16L3 BANK INPUT AVAILABLE L3BANK17L3 BANK INPUT AVAILABLE L3BANK18L3 BANK INPUT AVAILABLE L3BANK19L3 BANK INPUT AVAILABLE L3BANK2L3 BANK INPUT AVAILABLE L3BANK20L3 BANK INPUT AVAILABLE L3BANK21L3 BANK INPUT AVAILABLE L3BANK22L3 BANK INPUT AVAILABLE L3BANK23L3 BANK INPUT AVAILABLE L3BANK24L3 BANK INPUT AVAILABLE L3BANK25L3 BANK INPUT AVAILABLE L3BANK26L3 BANK INPUT AVAILABLE L3BANK27L3 BANK INPUT AVAILABLE L3BANK28L3 BANK INPUT AVAILABLE L3BANK29L3 BANK INPUT AVAILABLE L3BANK3L3 BANK INPUT AVAILABLE L3BANK30L3 BANK INPUT AVAILABLE L3BANK31L3 BANK INPUT AVAILABLE L3BANK4L3 BANK INPUT AVAILABLE L3BANK5L3 BANK INPUT AVAILABLE L3BANK6L3 BANK INPUT AVAILABLE L3BANK7L3 BANK INPUT AVAILABLE L3BANK8L3 BANK INPUT AVAILABLE L3BANK9L3 BANK STALL L3BANK0L3 BANK STALL L3BANK1L3 BANK STALL L3BANK10L3 BANK STALL L3BANK11L3 BANK STALL L3BANK12L3 BANK STALL L3BANK13L3 BANK STALL L3BANK14L3 BANK STALL L3BANK15L3 BANK STALL L3BANK16L3 BANK STALL L3BANK17L3 BANK STALL L3BANK18L3 BANK STALL L3BANK19L3 BANK STALL L3BANK2L3 BANK STALL L3BANK20L3 BANK STALL L3BANK21L3 BANK STALL L3BANK22L3 BANK STALL L3BANK23L3 BANK STALL L3BANK24L3 BANK STALL L3BANK25L3 BANK STALL L3BANK26L3 BANK STALL L3BANK27L3 BANK STALL L3BANK28L3 BANK STALL L3BANK29L3 BANK STALL L3BANK3L3 BANK STALL L3BANK30L3 BANK STALL L3BANK31L3 BANK STALL L3BANK4L3 BANK STALL L3BANK5L3 BANK STALL L3BANK6L3 BANK STALL L3BANK7L3 BANK STALL L3BANK8L3 BANK STALL L3BANK9L3 BUSY L3BANK0L3 BUSY L3BANK1L3 BUSY L3BANK2L3 BUSY L3BANK3L3 BUSY L3BANK4L3 BUSY L3BANK5L3 BUSY L3BANK6L3 BUSY L3BANK7L3 BYTE READL3 BYTE WRITEL3 Bank 00 AccessesL3 Bank 00 IC AccessesL3 Bank 00 IC HitsL3 Bank 01 AccessesL3 Bank 02 AccessesL3 Bank 03 AccessesL3 Bank 10 AccessesL3 Bank 10 IC AccessesL3 Bank 10 IC HitsL3 Bank 11 AccessesL3 Bank 12 AccessesL3 Bank 13 AccessesL3 HIT L3BANK0L3 HIT L3BANK1L3 HIT L3BANK10L3 HIT L3BANK11L3 HIT L3BANK12L3 HIT L3BANK13L3 HIT L3BANK14L3 HIT L3BANK15L3 HIT L3BANK16L3 HIT L3BANK17L3 HIT L3BANK18L3 HIT L3BANK19L3 HIT L3BANK2L3 HIT L3BANK20L3 HIT L3BANK21L3 HIT L3BANK22L3 HIT L3BANK23L3 HIT L3BANK24L3 HIT L3BANK25L3 HIT L3BANK26L3 HIT L3BANK27L3 HIT L3BANK28L3 HIT L3BANK29L3 HIT L3BANK3L3 HIT L3BANK30L3 HIT L3BANK31L3 HIT L3BANK4L3 HIT L3BANK5L3 HIT L3BANK6L3 HIT L3BANK7L3 HIT L3BANK8L3 HIT L3BANK9L3 INPUT AVAILABLE L3BANK0L3 INPUT AVAILABLE L3BANK1L3 INPUT AVAILABLE L3BANK2L3 INPUT AVAILABLE L3BANK3L3 INPUT AVAILABLE L3BANK4L3 INPUT AVAILABLE L3BANK5L3 INPUT AVAILABLE L3BANK6L3 INPUT AVAILABLE L3BANK7L3 Lookup Accesses w/o ICL3 MISS L3BANK0L3 MISS L3BANK1L3 MISS L3BANK10L3 MISS L3BANK11L3 MISS L3BANK12L3 MISS L3BANK13L3 MISS L3BANK14L3 MISS L3BANK15L3 MISS L3BANK16L3 MISS L3BANK17L3 MISS L3BANK18L3 MISS L3BANK19L3 MISS L3BANK2L3 MISS L3BANK20L3 MISS L3BANK21L3 MISS L3BANK22L3 MISS L3BANK23L3 MISS L3BANK24L3 MISS L3BANK25L3 MISS L3BANK26L3 MISS L3BANK27L3 MISS L3BANK28L3 MISS L3BANK29L3 MISS L3BANK3L3 MISS L3BANK30L3 MISS L3BANK31L3 MISS L3BANK4L3 MISS L3BANK5L3 MISS L3BANK6L3 MISS L3BANK7L3 MISS L3BANK8L3 MISS L3BANK9L3 MissesL3 OUTPUT READY L3BANK0L3 OUTPUT READY L3BANK1L3 OUTPUT READY L3BANK10L3 OUTPUT READY L3BANK11L3 OUTPUT READY L3BANK12L3 OUTPUT READY L3BANK13L3 OUTPUT READY L3BANK14L3 OUTPUT READY L3BANK15L3 OUTPUT READY L3BANK16L3 OUTPUT READY L3BANK17L3 OUTPUT READY L3BANK18L3 OUTPUT READY L3BANK19L3 OUTPUT READY L3BANK2L3 OUTPUT READY L3BANK20L3 OUTPUT READY L3BANK21L3 OUTPUT READY L3BANK22L3 OUTPUT READY L3BANK23L3 OUTPUT READY L3BANK24L3 OUTPUT READY L3BANK25L3 OUTPUT READY L3BANK26L3 OUTPUT READY L3BANK27L3 OUTPUT READY L3BANK28L3 OUTPUT READY L3BANK29L3 OUTPUT READY L3BANK3L3 OUTPUT READY L3BANK30L3 OUTPUT READY L3BANK31L3 OUTPUT READY L3BANK4L3 OUTPUT READY L3BANK5L3 OUTPUT READY L3BANK6L3 OUTPUT READY L3BANK7L3 OUTPUT READY L3BANK8L3 OUTPUT READY L3BANK9L3 READ L3BANK0L3 READ L3BANK1L3 READ L3BANK10L3 READ L3BANK11L3 READ L3BANK12L3 READ L3BANK13L3 READ L3BANK14L3 READ L3BANK15L3 READ L3BANK16L3 READ L3BANK17L3 READ L3BANK18L3 READ L3BANK19L3 READ L3BANK2L3 READ L3BANK20L3 READ L3BANK21L3 READ L3BANK22L3 READ L3BANK23L3 READ L3BANK24L3 READ L3BANK25L3 READ L3BANK26L3 READ L3BANK27L3 READ L3BANK28L3 READ L3BANK29L3 READ L3BANK3L3 READ L3BANK30L3 READ L3BANK31L3 READ L3BANK4L3 READ L3BANK5L3 READ L3BANK6L3 READ L3BANK7L3 READ L3BANK8L3 READ L3BANK9L3 STALL L3BANK0L3 STALL L3BANK1L3 STALL L3BANK2L3 STALL L3BANK3L3 STALL L3BANK4L3 STALL L3BANK5L3 STALL L3BANK6L3 STALL L3BANK7L3 SUPERQ FULL L3BANK0L3 SUPERQ FULL L3BANK1L3 SUPERQ FULL L3BANK10L3 SUPERQ FULL L3BANK11L3 SUPERQ FULL L3BANK12L3 SUPERQ FULL L3BANK13L3 SUPERQ FULL L3BANK14L3 SUPERQ FULL L3BANK15L3 SUPERQ FULL L3BANK16L3 SUPERQ FULL L3BANK17L3 SUPERQ FULL L3BANK18L3 SUPERQ FULL L3BANK19L3 SUPERQ FULL L3BANK2L3 SUPERQ FULL L3BANK20L3 SUPERQ FULL L3BANK21L3 SUPERQ FULL L3BANK22L3 SUPERQ FULL L3BANK23L3 SUPERQ FULL L3BANK24L3 SUPERQ FULL L3BANK25L3 SUPERQ FULL L3BANK26L3 SUPERQ FULL L3BANK27L3 SUPERQ FULL L3BANK28L3 SUPERQ FULL L3BANK29L3 SUPERQ FULL L3BANK3L3 SUPERQ FULL L3BANK30L3 SUPERQ FULL L3BANK31L3 SUPERQ FULL L3BANK4L3 SUPERQ FULL L3BANK5L3 SUPERQ FULL L3BANK6L3 SUPERQ FULL L3BANK7L3 SUPERQ FULL L3BANK8L3 SUPERQ FULL L3BANK9L3 Sampler ThroughputL3 Shader ThroughputL3 Total ThroughputL3 WRITE L3BANK0L3 WRITE L3BANK1L3 WRITE L3BANK10L3 WRITE L3BANK11L3 WRITE L3BANK12L3 WRITE L3BANK13L3 WRITE L3BANK14L3 WRITE L3BANK15L3 WRITE L3BANK16L3 WRITE L3BANK17L3 WRITE L3BANK18L3 WRITE L3BANK19L3 WRITE L3BANK2L3 WRITE L3BANK20L3 WRITE L3BANK21L3 WRITE L3BANK22L3 WRITE L3BANK23L3 WRITE L3BANK24L3 WRITE L3BANK25L3 WRITE L3BANK26L3 WRITE L3BANK27L3 WRITE L3BANK28L3 WRITE L3BANK29L3 WRITE L3BANK3L3 WRITE L3BANK30L3 WRITE L3BANK31L3 WRITE L3BANK4L3 WRITE L3BANK5L3 WRITE L3BANK6L3 WRITE L3BANK7L3 WRITE L3BANK8L3 WRITE L3BANK9LLC GPU AccessesLLC GPU HitsLLC GPU Read AccessesLLC GPU ThroughputLLC GPU Write AccessesLOAD STORE CACHE ACCESS XECORE0LOAD STORE CACHE ACCESS XECORE1LOAD STORE CACHE ACCESS XECORE10LOAD STORE CACHE ACCESS XECORE11LOAD STORE CACHE ACCESS XECORE12LOAD STORE CACHE ACCESS XECORE13LOAD STORE CACHE ACCESS XECORE14LOAD STORE CACHE ACCESS XECORE15LOAD STORE CACHE ACCESS XECORE16LOAD STORE CACHE ACCESS XECORE17LOAD STORE CACHE ACCESS XECORE18LOAD STORE CACHE ACCESS XECORE19LOAD STORE CACHE ACCESS XECORE2LOAD STORE CACHE ACCESS XECORE20LOAD STORE CACHE ACCESS XECORE21LOAD STORE CACHE ACCESS XECORE22LOAD STORE CACHE ACCESS XECORE23LOAD STORE CACHE ACCESS XECORE24LOAD STORE CACHE ACCESS XECORE25LOAD STORE CACHE ACCESS XECORE26LOAD STORE CACHE ACCESS XECORE27LOAD STORE CACHE ACCESS XECORE28LOAD STORE CACHE ACCESS XECORE29LOAD STORE CACHE ACCESS XECORE3LOAD STORE CACHE ACCESS XECORE30LOAD STORE CACHE ACCESS XECORE31LOAD STORE CACHE ACCESS XECORE4LOAD STORE CACHE ACCESS XECORE5LOAD STORE CACHE ACCESS XECORE6LOAD STORE CACHE ACCESS XECORE7LOAD STORE CACHE ACCESS XECORE8LOAD STORE CACHE ACCESS XECORE9LOAD STORE CACHE BYTE READLOAD STORE CACHE BYTE READ BANK0 XECORE0LOAD STORE CACHE BYTE READ BANK0 XECORE1LOAD STORE CACHE BYTE READ BANK0 XECORE2LOAD STORE CACHE BYTE READ BANK0 XECORE3LOAD STORE CACHE BYTE READ BANK0 XECORE4LOAD STORE CACHE BYTE READ BANK0 XECORE5LOAD STORE CACHE BYTE READ BANK0 XECORE6LOAD STORE CACHE BYTE READ BANK0 XECORE7LOAD STORE CACHE BYTE READ BANK1 XECORE0LOAD STORE CACHE BYTE READ BANK1 XECORE1LOAD STORE CACHE BYTE READ BANK1 XECORE2LOAD STORE CACHE BYTE READ BANK1 XECORE3LOAD STORE CACHE BYTE READ BANK1 XECORE4LOAD STORE CACHE BYTE READ BANK1 XECORE5LOAD STORE CACHE BYTE READ BANK1 XECORE6LOAD STORE CACHE BYTE READ BANK1 XECORE7LOAD STORE CACHE BYTE READ BANK2 XECORE0LOAD STORE CACHE BYTE READ BANK2 XECORE1LOAD STORE CACHE BYTE READ BANK2 XECORE2LOAD STORE CACHE BYTE READ BANK2 XECORE3LOAD STORE CACHE BYTE READ BANK2 XECORE4LOAD STORE CACHE BYTE READ BANK2 XECORE5LOAD STORE CACHE BYTE READ BANK2 XECORE6LOAD STORE CACHE BYTE READ BANK2 XECORE7LOAD STORE CACHE BYTE READ BANK3 XECORE0LOAD STORE CACHE BYTE READ BANK3 XECORE1LOAD STORE CACHE BYTE READ BANK3 XECORE2LOAD STORE CACHE BYTE READ BANK3 XECORE3LOAD STORE CACHE BYTE READ BANK3 XECORE4LOAD STORE CACHE BYTE READ BANK3 XECORE5LOAD STORE CACHE BYTE READ BANK3 XECORE6LOAD STORE CACHE BYTE READ BANK3 XECORE7LOAD STORE CACHE BYTE WRITELOAD STORE CACHE BYTE WRITE BANK0 XECORE0LOAD STORE CACHE BYTE WRITE BANK0 XECORE1LOAD STORE CACHE BYTE WRITE BANK0 XECORE2LOAD STORE CACHE BYTE WRITE BANK0 XECORE3LOAD STORE CACHE BYTE WRITE BANK0 XECORE4LOAD STORE CACHE BYTE WRITE BANK0 XECORE5LOAD STORE CACHE BYTE WRITE BANK0 XECORE6LOAD STORE CACHE BYTE WRITE BANK0 XECORE7LOAD STORE CACHE BYTE WRITE BANK1 XECORE0LOAD STORE CACHE BYTE WRITE BANK1 XECORE1LOAD STORE CACHE BYTE WRITE BANK1 XECORE2LOAD STORE CACHE BYTE WRITE BANK1 XECORE3LOAD STORE CACHE BYTE WRITE BANK1 XECORE4LOAD STORE CACHE BYTE WRITE BANK1 XECORE5LOAD STORE CACHE BYTE WRITE BANK1 XECORE6LOAD STORE CACHE BYTE WRITE BANK1 XECORE7LOAD STORE CACHE BYTE WRITE BANK2 XECORE0LOAD STORE CACHE BYTE WRITE BANK2 XECORE1LOAD STORE CACHE BYTE WRITE BANK2 XECORE2LOAD STORE CACHE BYTE WRITE BANK2 XECORE3LOAD STORE CACHE BYTE WRITE BANK2 XECORE4LOAD STORE CACHE BYTE WRITE BANK2 XECORE5LOAD STORE CACHE BYTE WRITE BANK2 XECORE6LOAD STORE CACHE BYTE WRITE BANK2 XECORE7LOAD STORE CACHE BYTE WRITE BANK3 XECORE0LOAD STORE CACHE BYTE WRITE BANK3 XECORE1LOAD STORE CACHE BYTE WRITE BANK3 XECORE2LOAD STORE CACHE BYTE WRITE BANK3 XECORE3LOAD STORE CACHE BYTE WRITE BANK3 XECORE4LOAD STORE CACHE BYTE WRITE BANK3 XECORE5LOAD STORE CACHE BYTE WRITE BANK3 XECORE6LOAD STORE CACHE BYTE WRITE BANK3 XECORE7LOAD STORE CACHE HIT XECORE0LOAD STORE CACHE HIT XECORE1LOAD STORE CACHE HIT XECORE10LOAD STORE CACHE HIT XECORE11LOAD STORE CACHE HIT XECORE12LOAD STORE CACHE HIT XECORE13LOAD STORE CACHE HIT XECORE14LOAD STORE CACHE HIT XECORE15LOAD STORE CACHE HIT XECORE16LOAD STORE CACHE HIT XECORE17LOAD STORE CACHE HIT XECORE18LOAD STORE CACHE HIT XECORE19LOAD STORE CACHE HIT XECORE2LOAD STORE CACHE HIT XECORE20LOAD STORE CACHE HIT XECORE21LOAD STORE CACHE HIT XECORE22LOAD STORE CACHE HIT XECORE23LOAD STORE CACHE HIT XECORE24LOAD STORE CACHE HIT XECORE25LOAD STORE CACHE HIT XECORE26LOAD STORE CACHE HIT XECORE27LOAD STORE CACHE HIT XECORE28LOAD STORE CACHE HIT XECORE29LOAD STORE CACHE HIT XECORE3LOAD STORE CACHE HIT XECORE30LOAD STORE CACHE HIT XECORE31LOAD STORE CACHE HIT XECORE4LOAD STORE CACHE HIT XECORE5LOAD STORE CACHE HIT XECORE6LOAD STORE CACHE HIT XECORE7LOAD STORE CACHE HIT XECORE8LOAD STORE CACHE HIT XECORE9LOAD STORE CACHE INPUT AVAILABLE XECORE0LOAD STORE CACHE INPUT AVAILABLE XECORE1LOAD STORE CACHE INPUT AVAILABLE XECORE10LOAD STORE CACHE INPUT AVAILABLE XECORE11LOAD STORE CACHE INPUT AVAILABLE XECORE12LOAD STORE CACHE INPUT AVAILABLE XECORE13LOAD STORE CACHE INPUT AVAILABLE XECORE14LOAD STORE CACHE INPUT AVAILABLE XECORE15LOAD STORE CACHE INPUT AVAILABLE XECORE16LOAD STORE CACHE INPUT AVAILABLE XECORE17LOAD STORE CACHE INPUT AVAILABLE XECORE18LOAD STORE CACHE INPUT AVAILABLE XECORE19LOAD STORE CACHE INPUT AVAILABLE XECORE2LOAD STORE CACHE INPUT AVAILABLE XECORE20LOAD STORE CACHE INPUT AVAILABLE XECORE21LOAD STORE CACHE INPUT AVAILABLE XECORE22LOAD STORE CACHE INPUT AVAILABLE XECORE23LOAD STORE CACHE INPUT AVAILABLE XECORE24LOAD STORE CACHE INPUT AVAILABLE XECORE25LOAD STORE CACHE INPUT AVAILABLE XECORE26LOAD STORE CACHE INPUT AVAILABLE XECORE27LOAD STORE CACHE INPUT AVAILABLE XECORE28LOAD STORE CACHE INPUT AVAILABLE XECORE29LOAD STORE CACHE INPUT AVAILABLE XECORE3LOAD STORE CACHE INPUT AVAILABLE XECORE30LOAD STORE CACHE INPUT AVAILABLE XECORE31LOAD STORE CACHE INPUT AVAILABLE XECORE4LOAD STORE CACHE INPUT AVAILABLE XECORE5LOAD STORE CACHE INPUT AVAILABLE XECORE6LOAD STORE CACHE INPUT AVAILABLE XECORE7LOAD STORE CACHE INPUT AVAILABLE XECORE8LOAD STORE CACHE INPUT AVAILABLE XECORE9LOAD STORE CACHE L3 READ XECORE0LOAD STORE CACHE L3 READ XECORE1LOAD STORE CACHE L3 READ XECORE10LOAD STORE CACHE L3 READ XECORE11LOAD STORE CACHE L3 READ XECORE12LOAD STORE CACHE L3 READ XECORE13LOAD STORE CACHE L3 READ XECORE14LOAD STORE CACHE L3 READ XECORE15LOAD STORE CACHE L3 READ XECORE16LOAD STORE CACHE L3 READ XECORE17LOAD STORE CACHE L3 READ XECORE18LOAD STORE CACHE L3 READ XECORE19LOAD STORE CACHE L3 READ XECORE2LOAD STORE CACHE L3 READ XECORE20LOAD STORE CACHE L3 READ XECORE21LOAD STORE CACHE L3 READ XECORE22LOAD STORE CACHE L3 READ XECORE23LOAD STORE CACHE L3 READ XECORE24LOAD STORE CACHE L3 READ XECORE25LOAD STORE CACHE L3 READ XECORE26LOAD STORE CACHE L3 READ XECORE27LOAD STORE CACHE L3 READ XECORE28LOAD STORE CACHE L3 READ XECORE29LOAD STORE CACHE L3 READ XECORE3LOAD STORE CACHE L3 READ XECORE30LOAD STORE CACHE L3 READ XECORE31LOAD STORE CACHE L3 READ XECORE4LOAD STORE CACHE L3 READ XECORE5LOAD STORE CACHE L3 READ XECORE6LOAD STORE CACHE L3 READ XECORE7LOAD STORE CACHE L3 READ XECORE8LOAD STORE CACHE L3 READ XECORE9LOAD STORE CACHE L3 WRITE XECORE0LOAD STORE CACHE L3 WRITE XECORE1LOAD STORE CACHE L3 WRITE XECORE10LOAD STORE CACHE L3 WRITE XECORE11LOAD STORE CACHE L3 WRITE XECORE12LOAD STORE CACHE L3 WRITE XECORE13LOAD STORE CACHE L3 WRITE XECORE14LOAD STORE CACHE L3 WRITE XECORE15LOAD STORE CACHE L3 WRITE XECORE16LOAD STORE CACHE L3 WRITE XECORE17LOAD STORE CACHE L3 WRITE XECORE18LOAD STORE CACHE L3 WRITE XECORE19LOAD STORE CACHE L3 WRITE XECORE2LOAD STORE CACHE L3 WRITE XECORE20LOAD STORE CACHE L3 WRITE XECORE21LOAD STORE CACHE L3 WRITE XECORE22LOAD STORE CACHE L3 WRITE XECORE23LOAD STORE CACHE L3 WRITE XECORE24LOAD STORE CACHE L3 WRITE XECORE25LOAD STORE CACHE L3 WRITE XECORE26LOAD STORE CACHE L3 WRITE XECORE27LOAD STORE CACHE L3 WRITE XECORE28LOAD STORE CACHE L3 WRITE XECORE29LOAD STORE CACHE L3 WRITE XECORE3LOAD STORE CACHE L3 WRITE XECORE30LOAD STORE CACHE L3 WRITE XECORE31LOAD STORE CACHE L3 WRITE XECORE4LOAD STORE CACHE L3 WRITE XECORE5LOAD STORE CACHE L3 WRITE XECORE6LOAD STORE CACHE L3 WRITE XECORE7LOAD STORE CACHE L3 WRITE XECORE8LOAD STORE CACHE L3 WRITE XECORE9LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE10LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE11LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE12LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE13LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE14LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE15LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE16LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE17LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE18LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE19LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE20LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE21LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE22LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE23LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE24LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE25LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE26LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE27LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE28LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE29LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE30LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE31LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE8LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE9LOAD STORE CACHE OUTPUT READY XECORE0LOAD STORE CACHE OUTPUT READY XECORE1LOAD STORE CACHE OUTPUT READY XECORE10LOAD STORE CACHE OUTPUT READY XECORE11LOAD STORE CACHE OUTPUT READY XECORE12LOAD STORE CACHE OUTPUT READY XECORE13LOAD STORE CACHE OUTPUT READY XECORE14LOAD STORE CACHE OUTPUT READY XECORE15LOAD STORE CACHE OUTPUT READY XECORE16LOAD STORE CACHE OUTPUT READY XECORE17LOAD STORE CACHE OUTPUT READY XECORE18LOAD STORE CACHE OUTPUT READY XECORE19LOAD STORE CACHE OUTPUT READY XECORE2LOAD STORE CACHE OUTPUT READY XECORE20LOAD STORE CACHE OUTPUT READY XECORE21LOAD STORE CACHE OUTPUT READY XECORE22LOAD STORE CACHE OUTPUT READY XECORE23LOAD STORE CACHE OUTPUT READY XECORE24LOAD STORE CACHE OUTPUT READY XECORE25LOAD STORE CACHE OUTPUT READY XECORE26LOAD STORE CACHE OUTPUT READY XECORE27LOAD STORE CACHE OUTPUT READY XECORE28LOAD STORE CACHE OUTPUT READY XECORE29LOAD STORE CACHE OUTPUT READY XECORE3LOAD STORE CACHE OUTPUT READY XECORE30LOAD STORE CACHE OUTPUT READY XECORE31LOAD STORE CACHE OUTPUT READY XECORE4LOAD STORE CACHE OUTPUT READY XECORE5LOAD STORE CACHE OUTPUT READY XECORE6LOAD STORE CACHE OUTPUT READY XECORE7LOAD STORE CACHE OUTPUT READY XECORE8LOAD STORE CACHE OUTPUT READY XECORE9LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1LOAD STORE CACHE PARTIAL WRITE COUNT XECORE10LOAD STORE CACHE PARTIAL WRITE COUNT XECORE11LOAD STORE CACHE PARTIAL WRITE COUNT XECORE12LOAD STORE CACHE PARTIAL WRITE COUNT XECORE13LOAD STORE CACHE PARTIAL WRITE COUNT XECORE14LOAD STORE CACHE PARTIAL WRITE COUNT XECORE15LOAD STORE CACHE PARTIAL WRITE COUNT XECORE16LOAD STORE CACHE PARTIAL WRITE COUNT XECORE17LOAD STORE CACHE PARTIAL WRITE COUNT XECORE18LOAD STORE CACHE PARTIAL WRITE COUNT XECORE19LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2LOAD STORE CACHE PARTIAL WRITE COUNT XECORE20LOAD STORE CACHE PARTIAL WRITE COUNT XECORE21LOAD STORE CACHE PARTIAL WRITE COUNT XECORE22LOAD STORE CACHE PARTIAL WRITE COUNT XECORE23LOAD STORE CACHE PARTIAL WRITE COUNT XECORE24LOAD STORE CACHE PARTIAL WRITE COUNT XECORE25LOAD STORE CACHE PARTIAL WRITE COUNT XECORE26LOAD STORE CACHE PARTIAL WRITE COUNT XECORE27LOAD STORE CACHE PARTIAL WRITE COUNT XECORE28LOAD STORE CACHE PARTIAL WRITE COUNT XECORE29LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3LOAD STORE CACHE PARTIAL WRITE COUNT XECORE30LOAD STORE CACHE PARTIAL WRITE COUNT XECORE31LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7LOAD STORE CACHE PARTIAL WRITE COUNT XECORE8LOAD STORE CACHE PARTIAL WRITE COUNT XECORE9Late Depth Test FailsLate Stencil Test FailsNon-PS Thread Ready For Dispatch on Slice0 DualSubslice0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 DualSubslice1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 DualSubslice2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 DualSubslice3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 DualSubslice4 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 DualSubslice5 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice4 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice4 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice4 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice4 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice5 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice5 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice5 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice5 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice6 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice6 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice6 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice6 Xe Core3 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice7 Xe Core0 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice7 Xe Core1 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice7 Xe Core2 Thread DispatcherNon-PS Thread Ready For Dispatch on Slice7 Xe Core3 Thread DispatcherNonPS Thread Ready For Dispatch on Slice0 Subslice0NonPS Thread Ready For Dispatch on Slice0 Subslice1NonPS Thread Ready For Dispatch on Slice0 Subslice2NonPS Thread Ready For Dispatch on Slice1 Subslice0NonPS Thread Ready For Dispatch on Slice1 Subslice1NonPS Thread Ready For Dispatch on Slice1 Subslice2PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE2PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE3PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE4PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE5PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE6PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE7PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE2PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE3PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE4PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE5PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE6PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE7PIXEL BACKEND INPUT AVAILABLE _L3NODE0PIXEL BACKEND INPUT AVAILABLE _L3NODE1PIXEL BACKEND OUTPUT READY _L3NODE0PIXEL BACKEND OUTPUT READY _L3NODE1PIXEL BLENDPIXEL POST PROCESS INPUT AVAILABLE CPIPE0PIXEL POST PROCESS INPUT AVAILABLE CPIPE1PIXEL POST PROCESS INPUT AVAILABLE CPIPE10PIXEL POST PROCESS INPUT AVAILABLE CPIPE11PIXEL POST PROCESS INPUT AVAILABLE CPIPE12PIXEL POST PROCESS INPUT AVAILABLE CPIPE13PIXEL POST PROCESS INPUT AVAILABLE CPIPE14PIXEL POST PROCESS INPUT AVAILABLE CPIPE15PIXEL POST PROCESS INPUT AVAILABLE CPIPE2PIXEL POST PROCESS INPUT AVAILABLE CPIPE3PIXEL POST PROCESS INPUT AVAILABLE CPIPE4PIXEL POST PROCESS INPUT AVAILABLE CPIPE5PIXEL POST PROCESS INPUT AVAILABLE CPIPE6PIXEL POST PROCESS INPUT AVAILABLE CPIPE7PIXEL POST PROCESS INPUT AVAILABLE CPIPE8PIXEL POST PROCESS INPUT AVAILABLE CPIPE9PIXEL POST PROCESS INPUT AVAILABLE XECORE0PIXEL POST PROCESS INPUT AVAILABLE XECORE1PIXEL POST PROCESS INPUT AVAILABLE XECORE2PIXEL POST PROCESS INPUT AVAILABLE XECORE3PIXEL POST PROCESS INPUT AVAILABLE XECORE4PIXEL POST PROCESS INPUT AVAILABLE XECORE5PIXEL POST PROCESS INPUT AVAILABLE XECORE6PIXEL POST PROCESS INPUT AVAILABLE XECORE7PIXEL POST PROCESS OUTPUT READY CPIPE0PIXEL POST PROCESS OUTPUT READY CPIPE1PIXEL POST PROCESS OUTPUT READY CPIPE10PIXEL POST PROCESS OUTPUT READY CPIPE11PIXEL POST PROCESS OUTPUT READY CPIPE12PIXEL POST PROCESS OUTPUT READY CPIPE13PIXEL POST PROCESS OUTPUT READY CPIPE14PIXEL POST PROCESS OUTPUT READY CPIPE15PIXEL POST PROCESS OUTPUT READY CPIPE2PIXEL POST PROCESS OUTPUT READY CPIPE3PIXEL POST PROCESS OUTPUT READY CPIPE4PIXEL POST PROCESS OUTPUT READY CPIPE5PIXEL POST PROCESS OUTPUT READY CPIPE6PIXEL POST PROCESS OUTPUT READY CPIPE7PIXEL POST PROCESS OUTPUT READY CPIPE8PIXEL POST PROCESS OUTPUT READY CPIPE9PIXEL WRITEPOSTPS DEPTH STENCIL ALPHA TEST FAILPS EM Pipe ActivePS FPU Pipe ActivePS FPU0 Pipe ActivePS FPU1 Pipe ActivePS OUTPUT AVAILABLE CPIPE0PS OUTPUT AVAILABLE CPIPE1PS OUTPUT AVAILABLE CPIPE10PS OUTPUT AVAILABLE CPIPE11PS OUTPUT AVAILABLE CPIPE12PS OUTPUT AVAILABLE CPIPE13PS OUTPUT AVAILABLE CPIPE14PS OUTPUT AVAILABLE CPIPE15PS OUTPUT AVAILABLE CPIPE2PS OUTPUT AVAILABLE CPIPE3PS OUTPUT AVAILABLE CPIPE4PS OUTPUT AVAILABLE CPIPE5PS OUTPUT AVAILABLE CPIPE6PS OUTPUT AVAILABLE CPIPE7PS OUTPUT AVAILABLE CPIPE8PS OUTPUT AVAILABLE CPIPE9PS Send Pipeline ActivePS Thread Ready For Dispatch on Slice0 Dualsubslice0 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Dualsubslice1 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Dualsubslice2 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Dualsubslice3 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Dualsubslice4 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Dualsubslice5 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice0PS Thread Ready For Dispatch on Slice0 Subslice0 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice1PS Thread Ready For Dispatch on Slice0 Subslice1 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice2PS Thread Ready For Dispatch on Slice0 Subslice2 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice3 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice4 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice5 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice6 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Subslice7 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice0 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice1 Subslice0PS Thread Ready For Dispatch on Slice1 Subslice1PS Thread Ready For Dispatch on Slice1 Subslice2PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice1 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice1 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice1 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice2 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice2 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice2 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice2 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice3 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice3 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice3 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice3 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice4 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice4 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice4 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice4 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice5 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice5 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice5 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice5 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice6 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice6 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice6 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice6 Xe Core3 Thread DispatcherPS Thread Ready For Dispatch on Slice7 Xe Core0 Thread DispatcherPS Thread Ready For Dispatch on Slice7 Xe Core1 Thread DispatcherPS Thread Ready For Dispatch on Slice7 Xe Core2 Thread DispatcherPS Thread Ready For Dispatch on Slice7 Xe Core3 Thread DispatcherPS Threads DispatchedPS00 Output AvailablePS01 Output AvailablePS10 Output AvailablePS11 Output AvailablePS20 Output AvailablePS21 Output AvailablePS30 Output AvailablePS31 Output AvailablePixel Values 00 ReadyPixel Values 01 ReadyPixel Values 10 ReadyPixel Values 11 ReadyPixel Values 20 ReadyPixel Values 21 ReadyPixel Values 30 ReadyPixel Values 31 ReadyPixels Failing TestsPolygon (Slice0) Data ReadyPolygon (Slice1) Data ReadyPolygon (Slice2) Data ReadyPolygon (Slice3) Data ReadyPolygon (Slice4) Data ReadyPolygon (Slice5) Data ReadyPolygon (Slice6) Data ReadyPolygon (Slice7) Data ReadyPolygon Data ReadyPosh Ring BusyQuad0 L3 Bank0 Input AvailableQuad0 L3 Bank0 Output ReadyQuad0 L3 Bank1 Input AvailableQuad0 L3 Bank1 Output ReadyQuad0 L3 Bank2 Input AvailableQuad0 L3 Bank2 Output ReadyQuad0 L3 Bank3 Input AvailableQuad0 L3 Bank3 Output ReadyQuad0 L3 Bank4 Input AvailableQuad0 L3 Bank4 Output ReadyQuad0 L3 Bank5 Input AvailableQuad0 L3 Bank5 Output ReadyQuad0 L3 Bank6 Input AvailableQuad0 L3 Bank6 Output ReadyQuad0 L3 Bank7 Input AvailableQuad0 L3 Bank7 Output ReadyQuad1 L3 Bank0 Input AvailableQuad1 L3 Bank0 Output ReadyQuad1 L3 Bank1 Input AvailableQuad1 L3 Bank1 Output ReadyQuad1 L3 Bank2 Input AvailableQuad1 L3 Bank2 Output ReadyQuad1 L3 Bank3 Input AvailableQuad1 L3 Bank3 Output ReadyQuad1 L3 Bank4 Input AvailableQuad1 L3 Bank4 Output ReadyQuad1 L3 Bank5 Input AvailableQuad1 L3 Bank5 Output ReadyQuad1 L3 Bank6 Input AvailableQuad1 L3 Bank6 Output ReadyQuad1 L3 Bank7 Input AvailableQuad1 L3 Bank7 Output ReadyQuad2 L3 Bank0 Input AvailableQuad2 L3 Bank0 Output ReadyQuad2 L3 Bank1 Input AvailableQuad2 L3 Bank1 Output ReadyQuad2 L3 Bank2 Input AvailableQuad2 L3 Bank2 Output ReadyQuad2 L3 Bank3 Input AvailableQuad2 L3 Bank3 Output ReadyQuad2 L3 Bank4 Input AvailableQuad2 L3 Bank4 Output ReadyQuad2 L3 Bank5 Input AvailableQuad2 L3 Bank5 Output ReadyQuad2 L3 Bank6 Input AvailableQuad2 L3 Bank6 Output ReadyQuad2 L3 Bank7 Input AvailableQuad2 L3 Bank7 Output ReadyQuad3 L3 Bank0 Input AvailableQuad3 L3 Bank0 Output ReadyQuad3 L3 Bank1 Input AvailableQuad3 L3 Bank1 Output ReadyQuad3 L3 Bank2 Input AvailableQuad3 L3 Bank2 Output ReadyQuad3 L3 Bank3 Input AvailableQuad3 L3 Bank3 Output ReadyQuad3 L3 Bank4 Input AvailableQuad3 L3 Bank4 Output ReadyQuad3 L3 Bank5 Input AvailableQuad3 L3 Bank5 Output ReadyQuad3 L3 Bank6 Input AvailableQuad3 L3 Bank6 Output ReadyQuad3 L3 Bank7 Input AvailableQuad3 L3 Bank7 Output ReadyRASTERIZER INPUT AVAILABLE SLICE0RASTERIZER INPUT AVAILABLE SLICE1RASTERIZER INPUT AVAILABLE SLICE2RASTERIZER INPUT AVAILABLE SLICE3RASTERIZER INPUT AVAILABLE SLICE4RASTERIZER INPUT AVAILABLE SLICE5RASTERIZER INPUT AVAILABLE SLICE6RASTERIZER INPUT AVAILABLE SLICE7RASTERIZER OUTPUT READY SLICE0RASTERIZER OUTPUT READY SLICE1RASTERIZER OUTPUT READY SLICE2RASTERIZER OUTPUT READY SLICE3RASTERIZER OUTPUT READY SLICE4RASTERIZER OUTPUT READY SLICE5RASTERIZER OUTPUT READY SLICE6RASTERIZER OUTPUT READY SLICE7RASTERIZER SAMPLE OUTPUTRASTERIZER TRANSACTION OUTPUT SLICE0RASTERIZER TRANSACTION OUTPUT SLICE1RASTERIZER TRANSACTION OUTPUT SLICE2RASTERIZER TRANSACTION OUTPUT SLICE3RASTERIZER TRANSACTION OUTPUT SLICE4RASTERIZER TRANSACTION OUTPUT SLICE5RASTERIZER TRANSACTION OUTPUT SLICE6RASTERIZER TRANSACTION OUTPUT SLICE7RENDER CACHE ALLOC L3NODE0RENDER CACHE ALLOC L3NODE1RENDER CACHE ALLOC L3NODE2RENDER CACHE ALLOC L3NODE3RENDER CACHE ALLOC L3NODE4RENDER CACHE ALLOC L3NODE5RENDER CACHE ALLOC L3NODE6RENDER CACHE ALLOC L3NODE7RENDER CACHE HIT L3NODE0RENDER CACHE HIT L3NODE1RENDER CACHE HIT L3NODE2RENDER CACHE HIT L3NODE3RENDER CACHE HIT L3NODE4RENDER CACHE HIT L3NODE5RENDER CACHE HIT L3NODE6RENDER CACHE HIT L3NODE7RENDER CACHE INPUT AVAILABLE _L3NODE0RENDER CACHE INPUT AVAILABLE _L3NODE1RENDER CACHE OUTPUT READY _L3NODE0RENDER CACHE OUTPUT READY _L3NODE1RENDER CACHE READ L3NODE0RENDER CACHE READ L3NODE1RENDER CACHE READ L3NODE2RENDER CACHE READ L3NODE3RENDER CACHE READ L3NODE4RENDER CACHE READ L3NODE5RENDER CACHE READ L3NODE6RENDER CACHE READ L3NODE7RENDER CACHE WRITE L3NODE0RENDER CACHE WRITE L3NODE1RENDER CACHE WRITE L3NODE2RENDER CACHE WRITE L3NODE3RENDER CACHE WRITE L3NODE4RENDER CACHE WRITE L3NODE5RENDER CACHE WRITE L3NODE6RENDER CACHE WRITE L3NODE7RENDER_CACHE_INPUT_AVAILABLE _L3NODE0RENDER_CACHE_INPUT_AVAILABLE _L3NODE1RENDER_CACHE_INPUT_AVAILABLE _L3NODE2RENDER_CACHE_INPUT_AVAILABLE _L3NODE3RENDER_CACHE_INPUT_AVAILABLE _L3NODE4RENDER_CACHE_INPUT_AVAILABLE _L3NODE5RENDER_CACHE_INPUT_AVAILABLE _L3NODE6RENDER_CACHE_INPUT_AVAILABLE _L3NODE7RENDER_CACHE_OUTPUT_READY _L3NODE0RENDER_CACHE_OUTPUT_READY _L3NODE1RENDER_CACHE_OUTPUT_READY _L3NODE2RENDER_CACHE_OUTPUT_READY _L3NODE3RENDER_CACHE_OUTPUT_READY _L3NODE4RENDER_CACHE_OUTPUT_READY _L3NODE5RENDER_CACHE_OUTPUT_READY _L3NODE6RENDER_CACHE_OUTPUT_READY _L3NODE7RT ANY HIT THREAD RAY DISPATCH XECORE0RT ANY HIT THREAD RAY DISPATCH XECORE1RT ANY HIT THREAD RAY DISPATCH XECORE10RT ANY HIT THREAD RAY DISPATCH XECORE11RT ANY HIT THREAD RAY DISPATCH XECORE12RT ANY HIT THREAD RAY DISPATCH XECORE13RT ANY HIT THREAD RAY DISPATCH XECORE14RT ANY HIT THREAD RAY DISPATCH XECORE15RT ANY HIT THREAD RAY DISPATCH XECORE16RT ANY HIT THREAD RAY DISPATCH XECORE17RT ANY HIT THREAD RAY DISPATCH XECORE18RT ANY HIT THREAD RAY DISPATCH XECORE19RT ANY HIT THREAD RAY DISPATCH XECORE2RT ANY HIT THREAD RAY DISPATCH XECORE20RT ANY HIT THREAD RAY DISPATCH XECORE21RT ANY HIT THREAD RAY DISPATCH XECORE22RT ANY HIT THREAD RAY DISPATCH XECORE23RT ANY HIT THREAD RAY DISPATCH XECORE24RT ANY HIT THREAD RAY DISPATCH XECORE25RT ANY HIT THREAD RAY DISPATCH XECORE26RT ANY HIT THREAD RAY DISPATCH XECORE27RT ANY HIT THREAD RAY DISPATCH XECORE28RT ANY HIT THREAD RAY DISPATCH XECORE29RT ANY HIT THREAD RAY DISPATCH XECORE3RT ANY HIT THREAD RAY DISPATCH XECORE30RT ANY HIT THREAD RAY DISPATCH XECORE31RT ANY HIT THREAD RAY DISPATCH XECORE4RT ANY HIT THREAD RAY DISPATCH XECORE5RT ANY HIT THREAD RAY DISPATCH XECORE6RT ANY HIT THREAD RAY DISPATCH XECORE7RT ANY HIT THREAD RAY DISPATCH XECORE8RT ANY HIT THREAD RAY DISPATCH XECORE9RT BVH CACHE MISS XECORE0RT BVH CACHE MISS XECORE1RT BVH CACHE MISS XECORE10RT BVH CACHE MISS XECORE11RT BVH CACHE MISS XECORE12RT BVH CACHE MISS XECORE13RT BVH CACHE MISS XECORE14RT BVH CACHE MISS XECORE15RT BVH CACHE MISS XECORE16RT BVH CACHE MISS XECORE17RT BVH CACHE MISS XECORE18RT BVH CACHE MISS XECORE19RT BVH CACHE MISS XECORE2RT BVH CACHE MISS XECORE20RT BVH CACHE MISS XECORE21RT BVH CACHE MISS XECORE22RT BVH CACHE MISS XECORE23RT BVH CACHE MISS XECORE24RT BVH CACHE MISS XECORE25RT BVH CACHE MISS XECORE26RT BVH CACHE MISS XECORE27RT BVH CACHE MISS XECORE28RT BVH CACHE MISS XECORE29RT BVH CACHE MISS XECORE3RT BVH CACHE MISS XECORE30RT BVH CACHE MISS XECORE31RT BVH CACHE MISS XECORE4RT BVH CACHE MISS XECORE5RT BVH CACHE MISS XECORE6RT BVH CACHE MISS XECORE7RT BVH CACHE MISS XECORE8RT BVH CACHE MISS XECORE9RT CALLABLE THREAD RAY DISPATCH XECORE0RT CALLABLE THREAD RAY DISPATCH XECORE1RT CALLABLE THREAD RAY DISPATCH XECORE10RT CALLABLE THREAD RAY DISPATCH XECORE11RT CALLABLE THREAD RAY DISPATCH XECORE12RT CALLABLE THREAD RAY DISPATCH XECORE13RT CALLABLE THREAD RAY DISPATCH XECORE14RT CALLABLE THREAD RAY DISPATCH XECORE15RT CALLABLE THREAD RAY DISPATCH XECORE16RT CALLABLE THREAD RAY DISPATCH XECORE17RT CALLABLE THREAD RAY DISPATCH XECORE18RT CALLABLE THREAD RAY DISPATCH XECORE19RT CALLABLE THREAD RAY DISPATCH XECORE2RT CALLABLE THREAD RAY DISPATCH XECORE20RT CALLABLE THREAD RAY DISPATCH XECORE21RT CALLABLE THREAD RAY DISPATCH XECORE22RT CALLABLE THREAD RAY DISPATCH XECORE23RT CALLABLE THREAD RAY DISPATCH XECORE24RT CALLABLE THREAD RAY DISPATCH XECORE25RT CALLABLE THREAD RAY DISPATCH XECORE26RT CALLABLE THREAD RAY DISPATCH XECORE27RT CALLABLE THREAD RAY DISPATCH XECORE28RT CALLABLE THREAD RAY DISPATCH XECORE29RT CALLABLE THREAD RAY DISPATCH XECORE3RT CALLABLE THREAD RAY DISPATCH XECORE30RT CALLABLE THREAD RAY DISPATCH XECORE31RT CALLABLE THREAD RAY DISPATCH XECORE4RT CALLABLE THREAD RAY DISPATCH XECORE5RT CALLABLE THREAD RAY DISPATCH XECORE6RT CALLABLE THREAD RAY DISPATCH XECORE7RT CALLABLE THREAD RAY DISPATCH XECORE8RT CALLABLE THREAD RAY DISPATCH XECORE9RT CLOSEST HIT THREAD RAY DISPATCH XECORE0RT CLOSEST HIT THREAD RAY DISPATCH XECORE1RT CLOSEST HIT THREAD RAY DISPATCH XECORE10RT CLOSEST HIT THREAD RAY DISPATCH XECORE11RT CLOSEST HIT THREAD RAY DISPATCH XECORE12RT CLOSEST HIT THREAD RAY DISPATCH XECORE13RT CLOSEST HIT THREAD RAY DISPATCH XECORE14RT CLOSEST HIT THREAD RAY DISPATCH XECORE15RT CLOSEST HIT THREAD RAY DISPATCH XECORE16RT CLOSEST HIT THREAD RAY DISPATCH XECORE17RT CLOSEST HIT THREAD RAY DISPATCH XECORE18RT CLOSEST HIT THREAD RAY DISPATCH XECORE19RT CLOSEST HIT THREAD RAY DISPATCH XECORE2RT CLOSEST HIT THREAD RAY DISPATCH XECORE20RT CLOSEST HIT THREAD RAY DISPATCH XECORE21RT CLOSEST HIT THREAD RAY DISPATCH XECORE22RT CLOSEST HIT THREAD RAY DISPATCH XECORE23RT CLOSEST HIT THREAD RAY DISPATCH XECORE24RT CLOSEST HIT THREAD RAY DISPATCH XECORE25RT CLOSEST HIT THREAD RAY DISPATCH XECORE26RT CLOSEST HIT THREAD RAY DISPATCH XECORE27RT CLOSEST HIT THREAD RAY DISPATCH XECORE28RT CLOSEST HIT THREAD RAY DISPATCH XECORE29RT CLOSEST HIT THREAD RAY DISPATCH XECORE3RT CLOSEST HIT THREAD RAY DISPATCH XECORE30RT CLOSEST HIT THREAD RAY DISPATCH XECORE31RT CLOSEST HIT THREAD RAY DISPATCH XECORE4RT CLOSEST HIT THREAD RAY DISPATCH XECORE5RT CLOSEST HIT THREAD RAY DISPATCH XECORE6RT CLOSEST HIT THREAD RAY DISPATCH XECORE7RT CLOSEST HIT THREAD RAY DISPATCH XECORE8RT CLOSEST HIT THREAD RAY DISPATCH XECORE9RT INPUT AVAILABLE XECORE0RT INPUT AVAILABLE XECORE1RT INPUT AVAILABLE XECORE10RT INPUT AVAILABLE XECORE11RT INPUT AVAILABLE XECORE12RT INPUT AVAILABLE XECORE13RT INPUT AVAILABLE XECORE14RT INPUT AVAILABLE XECORE15RT INPUT AVAILABLE XECORE16RT INPUT AVAILABLE XECORE17RT INPUT AVAILABLE XECORE18RT INPUT AVAILABLE XECORE19RT INPUT AVAILABLE XECORE2RT INPUT AVAILABLE XECORE20RT INPUT AVAILABLE XECORE21RT INPUT AVAILABLE XECORE22RT INPUT AVAILABLE XECORE23RT INPUT AVAILABLE XECORE24RT INPUT AVAILABLE XECORE25RT INPUT AVAILABLE XECORE26RT INPUT AVAILABLE XECORE27RT INPUT AVAILABLE XECORE28RT INPUT AVAILABLE XECORE29RT INPUT AVAILABLE XECORE3RT INPUT AVAILABLE XECORE30RT INPUT AVAILABLE XECORE31RT INPUT AVAILABLE XECORE4RT INPUT AVAILABLE XECORE5RT INPUT AVAILABLE XECORE6RT INPUT AVAILABLE XECORE7RT INPUT AVAILABLE XECORE8RT INPUT AVAILABLE XECORE9RT INPUT MESSAGE RAY COUNT XECORE0RT INPUT MESSAGE RAY COUNT XECORE1RT INPUT MESSAGE RAY COUNT XECORE10RT INPUT MESSAGE RAY COUNT XECORE11RT INPUT MESSAGE RAY COUNT XECORE12RT INPUT MESSAGE RAY COUNT XECORE13RT INPUT MESSAGE RAY COUNT XECORE14RT INPUT MESSAGE RAY COUNT XECORE15RT INPUT MESSAGE RAY COUNT XECORE16RT INPUT MESSAGE RAY COUNT XECORE17RT INPUT MESSAGE RAY COUNT XECORE18RT INPUT MESSAGE RAY COUNT XECORE19RT INPUT MESSAGE RAY COUNT XECORE2RT INPUT MESSAGE RAY COUNT XECORE20RT INPUT MESSAGE RAY COUNT XECORE21RT INPUT MESSAGE RAY COUNT XECORE22RT INPUT MESSAGE RAY COUNT XECORE23RT INPUT MESSAGE RAY COUNT XECORE24RT INPUT MESSAGE RAY COUNT XECORE25RT INPUT MESSAGE RAY COUNT XECORE26RT INPUT MESSAGE RAY COUNT XECORE27RT INPUT MESSAGE RAY COUNT XECORE28RT INPUT MESSAGE RAY COUNT XECORE29RT INPUT MESSAGE RAY COUNT XECORE3RT INPUT MESSAGE RAY COUNT XECORE30RT INPUT MESSAGE RAY COUNT XECORE31RT INPUT MESSAGE RAY COUNT XECORE4RT INPUT MESSAGE RAY COUNT XECORE5RT INPUT MESSAGE RAY COUNT XECORE6RT INPUT MESSAGE RAY COUNT XECORE7RT INPUT MESSAGE RAY COUNT XECORE8RT INPUT MESSAGE RAY COUNT XECORE9RT INSTANCE NODE RAY COUNT XECORE0RT INSTANCE NODE RAY COUNT XECORE1RT INSTANCE NODE RAY COUNT XECORE10RT INSTANCE NODE RAY COUNT XECORE11RT INSTANCE NODE RAY COUNT XECORE12RT INSTANCE NODE RAY COUNT XECORE13RT INSTANCE NODE RAY COUNT XECORE14RT INSTANCE NODE RAY COUNT XECORE15RT INSTANCE NODE RAY COUNT XECORE16RT INSTANCE NODE RAY COUNT XECORE17RT INSTANCE NODE RAY COUNT XECORE18RT INSTANCE NODE RAY COUNT XECORE19RT INSTANCE NODE RAY COUNT XECORE2RT INSTANCE NODE RAY COUNT XECORE20RT INSTANCE NODE RAY COUNT XECORE21RT INSTANCE NODE RAY COUNT XECORE22RT INSTANCE NODE RAY COUNT XECORE23RT INSTANCE NODE RAY COUNT XECORE24RT INSTANCE NODE RAY COUNT XECORE25RT INSTANCE NODE RAY COUNT XECORE26RT INSTANCE NODE RAY COUNT XECORE27RT INSTANCE NODE RAY COUNT XECORE28RT INSTANCE NODE RAY COUNT XECORE29RT INSTANCE NODE RAY COUNT XECORE3RT INSTANCE NODE RAY COUNT XECORE30RT INSTANCE NODE RAY COUNT XECORE31RT INSTANCE NODE RAY COUNT XECORE4RT INSTANCE NODE RAY COUNT XECORE5RT INSTANCE NODE RAY COUNT XECORE6RT INSTANCE NODE RAY COUNT XECORE7RT INSTANCE NODE RAY COUNT XECORE8RT INSTANCE NODE RAY COUNT XECORE9RT INTERNAL NODE RAY COUNT XECORE0RT INTERNAL NODE RAY COUNT XECORE1RT INTERNAL NODE RAY COUNT XECORE10RT INTERNAL NODE RAY COUNT XECORE11RT INTERNAL NODE RAY COUNT XECORE12RT INTERNAL NODE RAY COUNT XECORE13RT INTERNAL NODE RAY COUNT XECORE14RT INTERNAL NODE RAY COUNT XECORE15RT INTERNAL NODE RAY COUNT XECORE16RT INTERNAL NODE RAY COUNT XECORE17RT INTERNAL NODE RAY COUNT XECORE18RT INTERNAL NODE RAY COUNT XECORE19RT INTERNAL NODE RAY COUNT XECORE2RT INTERNAL NODE RAY COUNT XECORE20RT INTERNAL NODE RAY COUNT XECORE21RT INTERNAL NODE RAY COUNT XECORE22RT INTERNAL NODE RAY COUNT XECORE23RT INTERNAL NODE RAY COUNT XECORE24RT INTERNAL NODE RAY COUNT XECORE25RT INTERNAL NODE RAY COUNT XECORE26RT INTERNAL NODE RAY COUNT XECORE27RT INTERNAL NODE RAY COUNT XECORE28RT INTERNAL NODE RAY COUNT XECORE29RT INTERNAL NODE RAY COUNT XECORE3RT INTERNAL NODE RAY COUNT XECORE30RT INTERNAL NODE RAY COUNT XECORE31RT INTERNAL NODE RAY COUNT XECORE4RT INTERNAL NODE RAY COUNT XECORE5RT INTERNAL NODE RAY COUNT XECORE6RT INTERNAL NODE RAY COUNT XECORE7RT INTERNAL NODE RAY COUNT XECORE8RT INTERNAL NODE RAY COUNT XECORE9RT INTERSECTION THREAD RAY DISPATCH XECORE0RT INTERSECTION THREAD RAY DISPATCH XECORE1RT INTERSECTION THREAD RAY DISPATCH XECORE10RT INTERSECTION THREAD RAY DISPATCH XECORE11RT INTERSECTION THREAD RAY DISPATCH XECORE12RT INTERSECTION THREAD RAY DISPATCH XECORE13RT INTERSECTION THREAD RAY DISPATCH XECORE14RT INTERSECTION THREAD RAY DISPATCH XECORE15RT INTERSECTION THREAD RAY DISPATCH XECORE16RT INTERSECTION THREAD RAY DISPATCH XECORE17RT INTERSECTION THREAD RAY DISPATCH XECORE18RT INTERSECTION THREAD RAY DISPATCH XECORE19RT INTERSECTION THREAD RAY DISPATCH XECORE2RT INTERSECTION THREAD RAY DISPATCH XECORE20RT INTERSECTION THREAD RAY DISPATCH XECORE21RT INTERSECTION THREAD RAY DISPATCH XECORE22RT INTERSECTION THREAD RAY DISPATCH XECORE23RT INTERSECTION THREAD RAY DISPATCH XECORE24RT INTERSECTION THREAD RAY DISPATCH XECORE25RT INTERSECTION THREAD RAY DISPATCH XECORE26RT INTERSECTION THREAD RAY DISPATCH XECORE27RT INTERSECTION THREAD RAY DISPATCH XECORE28RT INTERSECTION THREAD RAY DISPATCH XECORE29RT INTERSECTION THREAD RAY DISPATCH XECORE3RT INTERSECTION THREAD RAY DISPATCH XECORE30RT INTERSECTION THREAD RAY DISPATCH XECORE31RT INTERSECTION THREAD RAY DISPATCH XECORE4RT INTERSECTION THREAD RAY DISPATCH XECORE5RT INTERSECTION THREAD RAY DISPATCH XECORE6RT INTERSECTION THREAD RAY DISPATCH XECORE7RT INTERSECTION THREAD RAY DISPATCH XECORE8RT INTERSECTION THREAD RAY DISPATCH XECORE9RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1RT LOAD STORE CACHE READ MESSAGE COUNT XECORE10RT LOAD STORE CACHE READ MESSAGE COUNT XECORE11RT LOAD STORE CACHE READ MESSAGE COUNT XECORE12RT LOAD STORE CACHE READ MESSAGE COUNT XECORE13RT LOAD STORE CACHE READ MESSAGE COUNT XECORE14RT LOAD STORE CACHE READ MESSAGE COUNT XECORE15RT LOAD STORE CACHE READ MESSAGE COUNT XECORE16RT LOAD STORE CACHE READ MESSAGE COUNT XECORE17RT LOAD STORE CACHE READ MESSAGE COUNT XECORE18RT LOAD STORE CACHE READ MESSAGE COUNT XECORE19RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2RT LOAD STORE CACHE READ MESSAGE COUNT XECORE20RT LOAD STORE CACHE READ MESSAGE COUNT XECORE21RT LOAD STORE CACHE READ MESSAGE COUNT XECORE22RT LOAD STORE CACHE READ MESSAGE COUNT XECORE23RT LOAD STORE CACHE READ MESSAGE COUNT XECORE24RT LOAD STORE CACHE READ MESSAGE COUNT XECORE25RT LOAD STORE CACHE READ MESSAGE COUNT XECORE26RT LOAD STORE CACHE READ MESSAGE COUNT XECORE27RT LOAD STORE CACHE READ MESSAGE COUNT XECORE28RT LOAD STORE CACHE READ MESSAGE COUNT XECORE29RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3RT LOAD STORE CACHE READ MESSAGE COUNT XECORE30RT LOAD STORE CACHE READ MESSAGE COUNT XECORE31RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7RT LOAD STORE CACHE READ MESSAGE COUNT XECORE8RT LOAD STORE CACHE READ MESSAGE COUNT XECORE9RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE10RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE11RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE12RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE13RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE14RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE15RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE16RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE17RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE18RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE19RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE20RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE21RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE22RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE23RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE24RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE25RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE26RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE27RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE28RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE29RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE30RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE31RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE8RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE9RT MESSAGE STALL COUNT XECORE0RT MESSAGE STALL COUNT XECORE1RT MESSAGE STALL COUNT XECORE10RT MESSAGE STALL COUNT XECORE11RT MESSAGE STALL COUNT XECORE12RT MESSAGE STALL COUNT XECORE13RT MESSAGE STALL COUNT XECORE14RT MESSAGE STALL COUNT XECORE15RT MESSAGE STALL COUNT XECORE16RT MESSAGE STALL COUNT XECORE17RT MESSAGE STALL COUNT XECORE18RT MESSAGE STALL COUNT XECORE19RT MESSAGE STALL COUNT XECORE2RT MESSAGE STALL COUNT XECORE20RT MESSAGE STALL COUNT XECORE21RT MESSAGE STALL COUNT XECORE22RT MESSAGE STALL COUNT XECORE23RT MESSAGE STALL COUNT XECORE24RT MESSAGE STALL COUNT XECORE25RT MESSAGE STALL COUNT XECORE26RT MESSAGE STALL COUNT XECORE27RT MESSAGE STALL COUNT XECORE28RT MESSAGE STALL COUNT XECORE29RT MESSAGE STALL COUNT XECORE3RT MESSAGE STALL COUNT XECORE30RT MESSAGE STALL COUNT XECORE31RT MESSAGE STALL COUNT XECORE4RT MESSAGE STALL COUNT XECORE5RT MESSAGE STALL COUNT XECORE6RT MESSAGE STALL COUNT XECORE7RT MESSAGE STALL COUNT XECORE8RT MESSAGE STALL COUNT XECORE9RT MISS THREAD RAY DISPATCH XECORE0RT MISS THREAD RAY DISPATCH XECORE1RT MISS THREAD RAY DISPATCH XECORE10RT MISS THREAD RAY DISPATCH XECORE11RT MISS THREAD RAY DISPATCH XECORE12RT MISS THREAD RAY DISPATCH XECORE13RT MISS THREAD RAY DISPATCH XECORE14RT MISS THREAD RAY DISPATCH XECORE15RT MISS THREAD RAY DISPATCH XECORE16RT MISS THREAD RAY DISPATCH XECORE17RT MISS THREAD RAY DISPATCH XECORE18RT MISS THREAD RAY DISPATCH XECORE19RT MISS THREAD RAY DISPATCH XECORE2RT MISS THREAD RAY DISPATCH XECORE20RT MISS THREAD RAY DISPATCH XECORE21RT MISS THREAD RAY DISPATCH XECORE22RT MISS THREAD RAY DISPATCH XECORE23RT MISS THREAD RAY DISPATCH XECORE24RT MISS THREAD RAY DISPATCH XECORE25RT MISS THREAD RAY DISPATCH XECORE26RT MISS THREAD RAY DISPATCH XECORE27RT MISS THREAD RAY DISPATCH XECORE28RT MISS THREAD RAY DISPATCH XECORE29RT MISS THREAD RAY DISPATCH XECORE3RT MISS THREAD RAY DISPATCH XECORE30RT MISS THREAD RAY DISPATCH XECORE31RT MISS THREAD RAY DISPATCH XECORE4RT MISS THREAD RAY DISPATCH XECORE5RT MISS THREAD RAY DISPATCH XECORE6RT MISS THREAD RAY DISPATCH XECORE7RT MISS THREAD RAY DISPATCH XECORE8RT MISS THREAD RAY DISPATCH XECORE9RT PROCEDURAL NODE RAY COUNT XECORE0RT PROCEDURAL NODE RAY COUNT XECORE1RT PROCEDURAL NODE RAY COUNT XECORE10RT PROCEDURAL NODE RAY COUNT XECORE11RT PROCEDURAL NODE RAY COUNT XECORE12RT PROCEDURAL NODE RAY COUNT XECORE13RT PROCEDURAL NODE RAY COUNT XECORE14RT PROCEDURAL NODE RAY COUNT XECORE15RT PROCEDURAL NODE RAY COUNT XECORE16RT PROCEDURAL NODE RAY COUNT XECORE17RT PROCEDURAL NODE RAY COUNT XECORE18RT PROCEDURAL NODE RAY COUNT XECORE19RT PROCEDURAL NODE RAY COUNT XECORE2RT PROCEDURAL NODE RAY COUNT XECORE20RT PROCEDURAL NODE RAY COUNT XECORE21RT PROCEDURAL NODE RAY COUNT XECORE22RT PROCEDURAL NODE RAY COUNT XECORE23RT PROCEDURAL NODE RAY COUNT XECORE24RT PROCEDURAL NODE RAY COUNT XECORE25RT PROCEDURAL NODE RAY COUNT XECORE26RT PROCEDURAL NODE RAY COUNT XECORE27RT PROCEDURAL NODE RAY COUNT XECORE28RT PROCEDURAL NODE RAY COUNT XECORE29RT PROCEDURAL NODE RAY COUNT XECORE3RT PROCEDURAL NODE RAY COUNT XECORE30RT PROCEDURAL NODE RAY COUNT XECORE31RT PROCEDURAL NODE RAY COUNT XECORE4RT PROCEDURAL NODE RAY COUNT XECORE5RT PROCEDURAL NODE RAY COUNT XECORE6RT PROCEDURAL NODE RAY COUNT XECORE7RT PROCEDURAL NODE RAY COUNT XECORE8RT PROCEDURAL NODE RAY COUNT XECORE9RT QUAD LEAF RAY COUNT XECORE0RT QUAD LEAF RAY COUNT XECORE1RT QUAD LEAF RAY COUNT XECORE10RT QUAD LEAF RAY COUNT XECORE11RT QUAD LEAF RAY COUNT XECORE12RT QUAD LEAF RAY COUNT XECORE13RT QUAD LEAF RAY COUNT XECORE14RT QUAD LEAF RAY COUNT XECORE15RT QUAD LEAF RAY COUNT XECORE16RT QUAD LEAF RAY COUNT XECORE17RT QUAD LEAF RAY COUNT XECORE18RT QUAD LEAF RAY COUNT XECORE19RT QUAD LEAF RAY COUNT XECORE2RT QUAD LEAF RAY COUNT XECORE20RT QUAD LEAF RAY COUNT XECORE21RT QUAD LEAF RAY COUNT XECORE22RT QUAD LEAF RAY COUNT XECORE23RT QUAD LEAF RAY COUNT XECORE24RT QUAD LEAF RAY COUNT XECORE25RT QUAD LEAF RAY COUNT XECORE26RT QUAD LEAF RAY COUNT XECORE27RT QUAD LEAF RAY COUNT XECORE28RT QUAD LEAF RAY COUNT XECORE29RT QUAD LEAF RAY COUNT XECORE3RT QUAD LEAF RAY COUNT XECORE30RT QUAD LEAF RAY COUNT XECORE31RT QUAD LEAF RAY COUNT XECORE4RT QUAD LEAF RAY COUNT XECORE5RT QUAD LEAF RAY COUNT XECORE6RT QUAD LEAF RAY COUNT XECORE7RT QUAD LEAF RAY COUNT XECORE8RT QUAD LEAF RAY COUNT XECORE9RT QUAD TEST RAY COUNT XECORE0RT QUAD TEST RAY COUNT XECORE1RT QUAD TEST RAY COUNT XECORE10RT QUAD TEST RAY COUNT XECORE11RT QUAD TEST RAY COUNT XECORE12RT QUAD TEST RAY COUNT XECORE13RT QUAD TEST RAY COUNT XECORE14RT QUAD TEST RAY COUNT XECORE15RT QUAD TEST RAY COUNT XECORE16RT QUAD TEST RAY COUNT XECORE17RT QUAD TEST RAY COUNT XECORE18RT QUAD TEST RAY COUNT XECORE19RT QUAD TEST RAY COUNT XECORE2RT QUAD TEST RAY COUNT XECORE20RT QUAD TEST RAY COUNT XECORE21RT QUAD TEST RAY COUNT XECORE22RT QUAD TEST RAY COUNT XECORE23RT QUAD TEST RAY COUNT XECORE24RT QUAD TEST RAY COUNT XECORE25RT QUAD TEST RAY COUNT XECORE26RT QUAD TEST RAY COUNT XECORE27RT QUAD TEST RAY COUNT XECORE28RT QUAD TEST RAY COUNT XECORE29RT QUAD TEST RAY COUNT XECORE3RT QUAD TEST RAY COUNT XECORE30RT QUAD TEST RAY COUNT XECORE31RT QUAD TEST RAY COUNT XECORE4RT QUAD TEST RAY COUNT XECORE5RT QUAD TEST RAY COUNT XECORE6RT QUAD TEST RAY COUNT XECORE7RT QUAD TEST RAY COUNT XECORE8RT QUAD TEST RAY COUNT XECORE9RT REQUEST COLLISION XECORE0RT REQUEST COLLISION XECORE1RT REQUEST COLLISION XECORE10RT REQUEST COLLISION XECORE11RT REQUEST COLLISION XECORE12RT REQUEST COLLISION XECORE13RT REQUEST COLLISION XECORE14RT REQUEST COLLISION XECORE15RT REQUEST COLLISION XECORE16RT REQUEST COLLISION XECORE17RT REQUEST COLLISION XECORE18RT REQUEST COLLISION XECORE19RT REQUEST COLLISION XECORE2RT REQUEST COLLISION XECORE20RT REQUEST COLLISION XECORE21RT REQUEST COLLISION XECORE22RT REQUEST COLLISION XECORE23RT REQUEST COLLISION XECORE24RT REQUEST COLLISION XECORE25RT REQUEST COLLISION XECORE26RT REQUEST COLLISION XECORE27RT REQUEST COLLISION XECORE28RT REQUEST COLLISION XECORE29RT REQUEST COLLISION XECORE3RT REQUEST COLLISION XECORE30RT REQUEST COLLISION XECORE31RT REQUEST COLLISION XECORE4RT REQUEST COLLISION XECORE5RT REQUEST COLLISION XECORE6RT REQUEST COLLISION XECORE7RT REQUEST COLLISION XECORE8RT REQUEST COLLISION XECORE9RT TRANSFORM RAY COUNT XECORE0RT TRANSFORM RAY COUNT XECORE1RT TRANSFORM RAY COUNT XECORE10RT TRANSFORM RAY COUNT XECORE11RT TRANSFORM RAY COUNT XECORE12RT TRANSFORM RAY COUNT XECORE13RT TRANSFORM RAY COUNT XECORE14RT TRANSFORM RAY COUNT XECORE15RT TRANSFORM RAY COUNT XECORE16RT TRANSFORM RAY COUNT XECORE17RT TRANSFORM RAY COUNT XECORE18RT TRANSFORM RAY COUNT XECORE19RT TRANSFORM RAY COUNT XECORE2RT TRANSFORM RAY COUNT XECORE20RT TRANSFORM RAY COUNT XECORE21RT TRANSFORM RAY COUNT XECORE22RT TRANSFORM RAY COUNT XECORE23RT TRANSFORM RAY COUNT XECORE24RT TRANSFORM RAY COUNT XECORE25RT TRANSFORM RAY COUNT XECORE26RT TRANSFORM RAY COUNT XECORE27RT TRANSFORM RAY COUNT XECORE28RT TRANSFORM RAY COUNT XECORE29RT TRANSFORM RAY COUNT XECORE3RT TRANSFORM RAY COUNT XECORE30RT TRANSFORM RAY COUNT XECORE31RT TRANSFORM RAY COUNT XECORE4RT TRANSFORM RAY COUNT XECORE5RT TRANSFORM RAY COUNT XECORE6RT TRANSFORM RAY COUNT XECORE7RT TRANSFORM RAY COUNT XECORE8RT TRANSFORM RAY COUNT XECORE9RT TRAVERSAL INPUT RAY COUNT XECORE0RT TRAVERSAL INPUT RAY COUNT XECORE1RT TRAVERSAL INPUT RAY COUNT XECORE10RT TRAVERSAL INPUT RAY COUNT XECORE11RT TRAVERSAL INPUT RAY COUNT XECORE12RT TRAVERSAL INPUT RAY COUNT XECORE13RT TRAVERSAL INPUT RAY COUNT XECORE14RT TRAVERSAL INPUT RAY COUNT XECORE15RT TRAVERSAL INPUT RAY COUNT XECORE16RT TRAVERSAL INPUT RAY COUNT XECORE17RT TRAVERSAL INPUT RAY COUNT XECORE18RT TRAVERSAL INPUT RAY COUNT XECORE19RT TRAVERSAL INPUT RAY COUNT XECORE2RT TRAVERSAL INPUT RAY COUNT XECORE20RT TRAVERSAL INPUT RAY COUNT XECORE21RT TRAVERSAL INPUT RAY COUNT XECORE22RT TRAVERSAL INPUT RAY COUNT XECORE23RT TRAVERSAL INPUT RAY COUNT XECORE24RT TRAVERSAL INPUT RAY COUNT XECORE25RT TRAVERSAL INPUT RAY COUNT XECORE26RT TRAVERSAL INPUT RAY COUNT XECORE27RT TRAVERSAL INPUT RAY COUNT XECORE28RT TRAVERSAL INPUT RAY COUNT XECORE29RT TRAVERSAL INPUT RAY COUNT XECORE3RT TRAVERSAL INPUT RAY COUNT XECORE30RT TRAVERSAL INPUT RAY COUNT XECORE31RT TRAVERSAL INPUT RAY COUNT XECORE4RT TRAVERSAL INPUT RAY COUNT XECORE5RT TRAVERSAL INPUT RAY COUNT XECORE6RT TRAVERSAL INPUT RAY COUNT XECORE7RT TRAVERSAL INPUT RAY COUNT XECORE8RT TRAVERSAL INPUT RAY COUNT XECORE9RT TRAVERSAL OUTPUT RAY COUNT XECORE0RT TRAVERSAL OUTPUT RAY COUNT XECORE1RT TRAVERSAL OUTPUT RAY COUNT XECORE10RT TRAVERSAL OUTPUT RAY COUNT XECORE11RT TRAVERSAL OUTPUT RAY COUNT XECORE12RT TRAVERSAL OUTPUT RAY COUNT XECORE13RT TRAVERSAL OUTPUT RAY COUNT XECORE14RT TRAVERSAL OUTPUT RAY COUNT XECORE15RT TRAVERSAL OUTPUT RAY COUNT XECORE16RT TRAVERSAL OUTPUT RAY COUNT XECORE17RT TRAVERSAL OUTPUT RAY COUNT XECORE18RT TRAVERSAL OUTPUT RAY COUNT XECORE19RT TRAVERSAL OUTPUT RAY COUNT XECORE2RT TRAVERSAL OUTPUT RAY COUNT XECORE20RT TRAVERSAL OUTPUT RAY COUNT XECORE21RT TRAVERSAL OUTPUT RAY COUNT XECORE22RT TRAVERSAL OUTPUT RAY COUNT XECORE23RT TRAVERSAL OUTPUT RAY COUNT XECORE24RT TRAVERSAL OUTPUT RAY COUNT XECORE25RT TRAVERSAL OUTPUT RAY COUNT XECORE26RT TRAVERSAL OUTPUT RAY COUNT XECORE27RT TRAVERSAL OUTPUT RAY COUNT XECORE28RT TRAVERSAL OUTPUT RAY COUNT XECORE29RT TRAVERSAL OUTPUT RAY COUNT XECORE3RT TRAVERSAL OUTPUT RAY COUNT XECORE30RT TRAVERSAL OUTPUT RAY COUNT XECORE31RT TRAVERSAL OUTPUT RAY COUNT XECORE4RT TRAVERSAL OUTPUT RAY COUNT XECORE5RT TRAVERSAL OUTPUT RAY COUNT XECORE6RT TRAVERSAL OUTPUT RAY COUNT XECORE7RT TRAVERSAL OUTPUT RAY COUNT XECORE8RT TRAVERSAL OUTPUT RAY COUNT XECORE9RT TRAVERSAL STEP RAY COUNT XECORE0RT TRAVERSAL STEP RAY COUNT XECORE1RT TRAVERSAL STEP RAY COUNT XECORE10RT TRAVERSAL STEP RAY COUNT XECORE11RT TRAVERSAL STEP RAY COUNT XECORE12RT TRAVERSAL STEP RAY COUNT XECORE13RT TRAVERSAL STEP RAY COUNT XECORE14RT TRAVERSAL STEP RAY COUNT XECORE15RT TRAVERSAL STEP RAY COUNT XECORE16RT TRAVERSAL STEP RAY COUNT XECORE17RT TRAVERSAL STEP RAY COUNT XECORE18RT TRAVERSAL STEP RAY COUNT XECORE19RT TRAVERSAL STEP RAY COUNT XECORE2RT TRAVERSAL STEP RAY COUNT XECORE20RT TRAVERSAL STEP RAY COUNT XECORE21RT TRAVERSAL STEP RAY COUNT XECORE22RT TRAVERSAL STEP RAY COUNT XECORE23RT TRAVERSAL STEP RAY COUNT XECORE24RT TRAVERSAL STEP RAY COUNT XECORE25RT TRAVERSAL STEP RAY COUNT XECORE26RT TRAVERSAL STEP RAY COUNT XECORE27RT TRAVERSAL STEP RAY COUNT XECORE28RT TRAVERSAL STEP RAY COUNT XECORE29RT TRAVERSAL STEP RAY COUNT XECORE3RT TRAVERSAL STEP RAY COUNT XECORE30RT TRAVERSAL STEP RAY COUNT XECORE31RT TRAVERSAL STEP RAY COUNT XECORE4RT TRAVERSAL STEP RAY COUNT XECORE5RT TRAVERSAL STEP RAY COUNT XECORE6RT TRAVERSAL STEP RAY COUNT XECORE7RT TRAVERSAL STEP RAY COUNT XECORE8RT TRAVERSAL STEP RAY COUNT XECORE9Rasterized PixelsRender Ring BusyRender and any compute engines are simultaneously busyRender and compute engines are simultaneously busySAMPLER 2X2 READSAMPLER BUSY XECORE0SAMPLER BUSY XECORE1SAMPLER BUSY XECORE10SAMPLER BUSY XECORE11SAMPLER BUSY XECORE12SAMPLER BUSY XECORE13SAMPLER BUSY XECORE14SAMPLER BUSY XECORE15SAMPLER BUSY XECORE16SAMPLER BUSY XECORE17SAMPLER BUSY XECORE18SAMPLER BUSY XECORE19SAMPLER BUSY XECORE2SAMPLER BUSY XECORE20SAMPLER BUSY XECORE21SAMPLER BUSY XECORE22SAMPLER BUSY XECORE23SAMPLER BUSY XECORE24SAMPLER BUSY XECORE25SAMPLER BUSY XECORE26SAMPLER BUSY XECORE27SAMPLER BUSY XECORE28SAMPLER BUSY XECORE29SAMPLER BUSY XECORE3SAMPLER BUSY XECORE30SAMPLER BUSY XECORE31SAMPLER BUSY XECORE4SAMPLER BUSY XECORE5SAMPLER BUSY XECORE6SAMPLER BUSY XECORE7SAMPLER BUSY XECORE8SAMPLER BUSY XECORE9SAMPLER INPUT AVAILABLE XECORE0SAMPLER INPUT AVAILABLE XECORE1SAMPLER INPUT AVAILABLE XECORE10SAMPLER INPUT AVAILABLE XECORE11SAMPLER INPUT AVAILABLE XECORE12SAMPLER INPUT AVAILABLE XECORE13SAMPLER INPUT AVAILABLE XECORE14SAMPLER INPUT AVAILABLE XECORE15SAMPLER INPUT AVAILABLE XECORE16SAMPLER INPUT AVAILABLE XECORE17SAMPLER INPUT AVAILABLE XECORE18SAMPLER INPUT AVAILABLE XECORE19SAMPLER INPUT AVAILABLE XECORE2SAMPLER INPUT AVAILABLE XECORE20SAMPLER INPUT AVAILABLE XECORE21SAMPLER INPUT AVAILABLE XECORE22SAMPLER INPUT AVAILABLE XECORE23SAMPLER INPUT AVAILABLE XECORE24SAMPLER INPUT AVAILABLE XECORE25SAMPLER INPUT AVAILABLE XECORE26SAMPLER INPUT AVAILABLE XECORE27SAMPLER INPUT AVAILABLE XECORE28SAMPLER INPUT AVAILABLE XECORE29SAMPLER INPUT AVAILABLE XECORE3SAMPLER INPUT AVAILABLE XECORE30SAMPLER INPUT AVAILABLE XECORE31SAMPLER INPUT AVAILABLE XECORE4SAMPLER INPUT AVAILABLE XECORE5SAMPLER INPUT AVAILABLE XECORE6SAMPLER INPUT AVAILABLE XECORE7SAMPLER INPUT AVAILABLE XECORE8SAMPLER INPUT AVAILABLE XECORE9SAMPLER L3 HIT L3BANK0SAMPLER L3 HIT L3BANK1SAMPLER L3 HIT L3BANK10SAMPLER L3 HIT L3BANK11SAMPLER L3 HIT L3BANK12SAMPLER L3 HIT L3BANK13SAMPLER L3 HIT L3BANK14SAMPLER L3 HIT L3BANK15SAMPLER L3 HIT L3BANK16SAMPLER L3 HIT L3BANK17SAMPLER L3 HIT L3BANK18SAMPLER L3 HIT L3BANK19SAMPLER L3 HIT L3BANK2SAMPLER L3 HIT L3BANK20SAMPLER L3 HIT L3BANK21SAMPLER L3 HIT L3BANK22SAMPLER L3 HIT L3BANK23SAMPLER L3 HIT L3BANK24SAMPLER L3 HIT L3BANK25SAMPLER L3 HIT L3BANK26SAMPLER L3 HIT L3BANK27SAMPLER L3 HIT L3BANK28SAMPLER L3 HIT L3BANK29SAMPLER L3 HIT L3BANK3SAMPLER L3 HIT L3BANK30SAMPLER L3 HIT L3BANK31SAMPLER L3 HIT L3BANK4SAMPLER L3 HIT L3BANK5SAMPLER L3 HIT L3BANK6SAMPLER L3 HIT L3BANK7SAMPLER L3 HIT L3BANK8SAMPLER L3 HIT L3BANK9SAMPLER L3 READSAMPLER L3 READ L3BANK0SAMPLER L3 READ L3BANK1SAMPLER L3 READ L3BANK10SAMPLER L3 READ L3BANK11SAMPLER L3 READ L3BANK12SAMPLER L3 READ L3BANK13SAMPLER L3 READ L3BANK14SAMPLER L3 READ L3BANK15SAMPLER L3 READ L3BANK16SAMPLER L3 READ L3BANK17SAMPLER L3 READ L3BANK18SAMPLER L3 READ L3BANK19SAMPLER L3 READ L3BANK2SAMPLER L3 READ L3BANK20SAMPLER L3 READ L3BANK21SAMPLER L3 READ L3BANK22SAMPLER L3 READ L3BANK23SAMPLER L3 READ L3BANK24SAMPLER L3 READ L3BANK25SAMPLER L3 READ L3BANK26SAMPLER L3 READ L3BANK27SAMPLER L3 READ L3BANK28SAMPLER L3 READ L3BANK29SAMPLER L3 READ L3BANK3SAMPLER L3 READ L3BANK30SAMPLER L3 READ L3BANK31SAMPLER L3 READ L3BANK4SAMPLER L3 READ L3BANK5SAMPLER L3 READ L3BANK6SAMPLER L3 READ L3BANK7SAMPLER L3 READ L3BANK8SAMPLER L3 READ L3BANK9SAMPLER MEMORY LATENCY STALL XECORE0SAMPLER MEMORY LATENCY STALL XECORE1SAMPLER MEMORY LATENCY STALL XECORE10SAMPLER MEMORY LATENCY STALL XECORE11SAMPLER MEMORY LATENCY STALL XECORE12SAMPLER MEMORY LATENCY STALL XECORE13SAMPLER MEMORY LATENCY STALL XECORE14SAMPLER MEMORY LATENCY STALL XECORE15SAMPLER MEMORY LATENCY STALL XECORE16SAMPLER MEMORY LATENCY STALL XECORE17SAMPLER MEMORY LATENCY STALL XECORE18SAMPLER MEMORY LATENCY STALL XECORE19SAMPLER MEMORY LATENCY STALL XECORE2SAMPLER MEMORY LATENCY STALL XECORE20SAMPLER MEMORY LATENCY STALL XECORE21SAMPLER MEMORY LATENCY STALL XECORE22SAMPLER MEMORY LATENCY STALL XECORE23SAMPLER MEMORY LATENCY STALL XECORE24SAMPLER MEMORY LATENCY STALL XECORE25SAMPLER MEMORY LATENCY STALL XECORE26SAMPLER MEMORY LATENCY STALL XECORE27SAMPLER MEMORY LATENCY STALL XECORE28SAMPLER MEMORY LATENCY STALL XECORE29SAMPLER MEMORY LATENCY STALL XECORE3SAMPLER MEMORY LATENCY STALL XECORE30SAMPLER MEMORY LATENCY STALL XECORE31SAMPLER MEMORY LATENCY STALL XECORE4SAMPLER MEMORY LATENCY STALL XECORE5SAMPLER MEMORY LATENCY STALL XECORE6SAMPLER MEMORY LATENCY STALL XECORE7SAMPLER MEMORY LATENCY STALL XECORE8SAMPLER MEMORY LATENCY STALL XECORE9SAMPLER OUTPUT READY XECORE0SAMPLER OUTPUT READY XECORE1SAMPLER OUTPUT READY XECORE10SAMPLER OUTPUT READY XECORE11SAMPLER OUTPUT READY XECORE12SAMPLER OUTPUT READY XECORE13SAMPLER OUTPUT READY XECORE14SAMPLER OUTPUT READY XECORE15SAMPLER OUTPUT READY XECORE16SAMPLER OUTPUT READY XECORE17SAMPLER OUTPUT READY XECORE18SAMPLER OUTPUT READY XECORE19SAMPLER OUTPUT READY XECORE2SAMPLER OUTPUT READY XECORE20SAMPLER OUTPUT READY XECORE21SAMPLER OUTPUT READY XECORE22SAMPLER OUTPUT READY XECORE23SAMPLER OUTPUT READY XECORE24SAMPLER OUTPUT READY XECORE25SAMPLER OUTPUT READY XECORE26SAMPLER OUTPUT READY XECORE27SAMPLER OUTPUT READY XECORE28SAMPLER OUTPUT READY XECORE29SAMPLER OUTPUT READY XECORE3SAMPLER OUTPUT READY XECORE30SAMPLER OUTPUT READY XECORE31SAMPLER OUTPUT READY XECORE4SAMPLER OUTPUT READY XECORE5SAMPLER OUTPUT READY XECORE6SAMPLER OUTPUT READY XECORE7SAMPLER OUTPUT READY XECORE8SAMPLER OUTPUT READY XECORE9SAMPLER TEXTURE CACHE ACCESS XECORE0SAMPLER TEXTURE CACHE ACCESS XECORE1SAMPLER TEXTURE CACHE ACCESS XECORE10SAMPLER TEXTURE CACHE ACCESS XECORE11SAMPLER TEXTURE CACHE ACCESS XECORE12SAMPLER TEXTURE CACHE ACCESS XECORE13SAMPLER TEXTURE CACHE ACCESS XECORE14SAMPLER TEXTURE CACHE ACCESS XECORE15SAMPLER TEXTURE CACHE ACCESS XECORE16SAMPLER TEXTURE CACHE ACCESS XECORE17SAMPLER TEXTURE CACHE ACCESS XECORE18SAMPLER TEXTURE CACHE ACCESS XECORE19SAMPLER TEXTURE CACHE ACCESS XECORE2SAMPLER TEXTURE CACHE ACCESS XECORE20SAMPLER TEXTURE CACHE ACCESS XECORE21SAMPLER TEXTURE CACHE ACCESS XECORE22SAMPLER TEXTURE CACHE ACCESS XECORE23SAMPLER TEXTURE CACHE ACCESS XECORE24SAMPLER TEXTURE CACHE ACCESS XECORE25SAMPLER TEXTURE CACHE ACCESS XECORE26SAMPLER TEXTURE CACHE ACCESS XECORE27SAMPLER TEXTURE CACHE ACCESS XECORE28SAMPLER TEXTURE CACHE ACCESS XECORE29SAMPLER TEXTURE CACHE ACCESS XECORE3SAMPLER TEXTURE CACHE ACCESS XECORE30SAMPLER TEXTURE CACHE ACCESS XECORE31SAMPLER TEXTURE CACHE ACCESS XECORE4SAMPLER TEXTURE CACHE ACCESS XECORE5SAMPLER TEXTURE CACHE ACCESS XECORE6SAMPLER TEXTURE CACHE ACCESS XECORE7SAMPLER TEXTURE CACHE ACCESS XECORE8SAMPLER TEXTURE CACHE ACCESS XECORE9SAMPLER TEXTURE CACHE MISS XECORE0SAMPLER TEXTURE CACHE MISS XECORE1SAMPLER TEXTURE CACHE MISS XECORE10SAMPLER TEXTURE CACHE MISS XECORE11SAMPLER TEXTURE CACHE MISS XECORE12SAMPLER TEXTURE CACHE MISS XECORE13SAMPLER TEXTURE CACHE MISS XECORE14SAMPLER TEXTURE CACHE MISS XECORE15SAMPLER TEXTURE CACHE MISS XECORE16SAMPLER TEXTURE CACHE MISS XECORE17SAMPLER TEXTURE CACHE MISS XECORE18SAMPLER TEXTURE CACHE MISS XECORE19SAMPLER TEXTURE CACHE MISS XECORE2SAMPLER TEXTURE CACHE MISS XECORE20SAMPLER TEXTURE CACHE MISS XECORE21SAMPLER TEXTURE CACHE MISS XECORE22SAMPLER TEXTURE CACHE MISS XECORE23SAMPLER TEXTURE CACHE MISS XECORE24SAMPLER TEXTURE CACHE MISS XECORE25SAMPLER TEXTURE CACHE MISS XECORE26SAMPLER TEXTURE CACHE MISS XECORE27SAMPLER TEXTURE CACHE MISS XECORE28SAMPLER TEXTURE CACHE MISS XECORE29SAMPLER TEXTURE CACHE MISS XECORE3SAMPLER TEXTURE CACHE MISS XECORE30SAMPLER TEXTURE CACHE MISS XECORE31SAMPLER TEXTURE CACHE MISS XECORE4SAMPLER TEXTURE CACHE MISS XECORE5SAMPLER TEXTURE CACHE MISS XECORE6SAMPLER TEXTURE CACHE MISS XECORE7SAMPLER TEXTURE CACHE MISS XECORE8SAMPLER TEXTURE CACHE MISS XECORE9SF StallSF0 BottleneckSF0 StallSF1 BottleneckSF1 StallSF2 BottleneckSF2 StallSF3 BottleneckSF3 StallSF4 BottleneckSF4 StallSF5 BottleneckSF5 StallSF6 BottleneckSF6 StallSF7 BottleneckSF7 StallSLM ACCESS COUNT BANK0 XECORE0SLM ACCESS COUNT BANK0 XECORE1SLM ACCESS COUNT BANK0 XECORE2SLM ACCESS COUNT BANK0 XECORE3SLM ACCESS COUNT BANK0 XECORE4SLM ACCESS COUNT BANK0 XECORE5SLM ACCESS COUNT BANK0 XECORE6SLM ACCESS COUNT BANK0 XECORE7SLM ACCESS COUNT BANK1 XECORE0SLM ACCESS COUNT BANK1 XECORE1SLM ACCESS COUNT BANK1 XECORE2SLM ACCESS COUNT BANK1 XECORE3SLM ACCESS COUNT BANK1 XECORE4SLM ACCESS COUNT BANK1 XECORE5SLM ACCESS COUNT BANK1 XECORE6SLM ACCESS COUNT BANK1 XECORE7SLM ACCESS COUNT XECORE0SLM ACCESS COUNT XECORE1SLM ACCESS COUNT XECORE10SLM ACCESS COUNT XECORE11SLM ACCESS COUNT XECORE12SLM ACCESS COUNT XECORE13SLM ACCESS COUNT XECORE14SLM ACCESS COUNT XECORE15SLM ACCESS COUNT XECORE16SLM ACCESS COUNT XECORE17SLM ACCESS COUNT XECORE18SLM ACCESS COUNT XECORE19SLM ACCESS COUNT XECORE2SLM ACCESS COUNT XECORE20SLM ACCESS COUNT XECORE21SLM ACCESS COUNT XECORE22SLM ACCESS COUNT XECORE23SLM ACCESS COUNT XECORE24SLM ACCESS COUNT XECORE25SLM ACCESS COUNT XECORE26SLM ACCESS COUNT XECORE27SLM ACCESS COUNT XECORE28SLM ACCESS COUNT XECORE29SLM ACCESS COUNT XECORE3SLM ACCESS COUNT XECORE30SLM ACCESS COUNT XECORE31SLM ACCESS COUNT XECORE4SLM ACCESS COUNT XECORE5SLM ACCESS COUNT XECORE6SLM ACCESS COUNT XECORE7SLM ACCESS COUNT XECORE8SLM ACCESS COUNT XECORE9SLM BANK CONFLICT COUNTSLM BANK CONFLICT COUNT XECORE0SLM BANK CONFLICT COUNT XECORE1SLM BANK CONFLICT COUNT XECORE10SLM BANK CONFLICT COUNT XECORE11SLM BANK CONFLICT COUNT XECORE12SLM BANK CONFLICT COUNT XECORE13SLM BANK CONFLICT COUNT XECORE14SLM BANK CONFLICT COUNT XECORE15SLM BANK CONFLICT COUNT XECORE16SLM BANK CONFLICT COUNT XECORE17SLM BANK CONFLICT COUNT XECORE18SLM BANK CONFLICT COUNT XECORE19SLM BANK CONFLICT COUNT XECORE2SLM BANK CONFLICT COUNT XECORE20SLM BANK CONFLICT COUNT XECORE21SLM BANK CONFLICT COUNT XECORE22SLM BANK CONFLICT COUNT XECORE23SLM BANK CONFLICT COUNT XECORE24SLM BANK CONFLICT COUNT XECORE25SLM BANK CONFLICT COUNT XECORE26SLM BANK CONFLICT COUNT XECORE27SLM BANK CONFLICT COUNT XECORE28SLM BANK CONFLICT COUNT XECORE29SLM BANK CONFLICT COUNT XECORE3SLM BANK CONFLICT COUNT XECORE30SLM BANK CONFLICT COUNT XECORE31SLM BANK CONFLICT COUNT XECORE4SLM BANK CONFLICT COUNT XECORE5SLM BANK CONFLICT COUNT XECORE6SLM BANK CONFLICT COUNT XECORE7SLM BANK CONFLICT COUNT XECORE8SLM BANK CONFLICT COUNT XECORE9SLM BYTE READSLM BYTE READ BANK0 XECORE0SLM BYTE READ BANK0 XECORE1SLM BYTE READ BANK0 XECORE2SLM BYTE READ BANK0 XECORE3SLM BYTE READ BANK0 XECORE4SLM BYTE READ BANK0 XECORE5SLM BYTE READ BANK0 XECORE6SLM BYTE READ BANK0 XECORE7SLM BYTE READ BANK1 XECORE0SLM BYTE READ BANK1 XECORE1SLM BYTE READ BANK1 XECORE2SLM BYTE READ BANK1 XECORE3SLM BYTE READ BANK1 XECORE4SLM BYTE READ BANK1 XECORE5SLM BYTE READ BANK1 XECORE6SLM BYTE READ BANK1 XECORE7SLM BYTE READ BANK2 XECORE0SLM BYTE READ BANK2 XECORE1SLM BYTE READ BANK2 XECORE2SLM BYTE READ BANK2 XECORE3SLM BYTE READ BANK2 XECORE4SLM BYTE READ BANK2 XECORE5SLM BYTE READ BANK2 XECORE6SLM BYTE READ BANK2 XECORE7SLM BYTE READ BANK3 XECORE0SLM BYTE READ BANK3 XECORE1SLM BYTE READ BANK3 XECORE2SLM BYTE READ BANK3 XECORE3SLM BYTE READ BANK3 XECORE4SLM BYTE READ BANK3 XECORE5SLM BYTE READ BANK3 XECORE6SLM BYTE READ BANK3 XECORE7SLM BYTE WRITESLM BYTE WRITE BANK0 XECORE0SLM BYTE WRITE BANK0 XECORE1SLM BYTE WRITE BANK0 XECORE2SLM BYTE WRITE BANK0 XECORE3SLM BYTE WRITE BANK0 XECORE4SLM BYTE WRITE BANK0 XECORE5SLM BYTE WRITE BANK0 XECORE6SLM BYTE WRITE BANK0 XECORE7SLM BYTE WRITE BANK1 XECORE0SLM BYTE WRITE BANK1 XECORE1SLM BYTE WRITE BANK1 XECORE2SLM BYTE WRITE BANK1 XECORE3SLM BYTE WRITE BANK1 XECORE4SLM BYTE WRITE BANK1 XECORE5SLM BYTE WRITE BANK1 XECORE6SLM BYTE WRITE BANK1 XECORE7SLM BYTE WRITE BANK2 XECORE0SLM BYTE WRITE BANK2 XECORE1SLM BYTE WRITE BANK2 XECORE2SLM BYTE WRITE BANK2 XECORE3SLM BYTE WRITE BANK2 XECORE4SLM BYTE WRITE BANK2 XECORE5SLM BYTE WRITE BANK2 XECORE6SLM BYTE WRITE BANK2 XECORE7SLM BYTE WRITE BANK3 XECORE0SLM BYTE WRITE BANK3 XECORE1SLM BYTE WRITE BANK3 XECORE2SLM BYTE WRITE BANK3 XECORE3SLM BYTE WRITE BANK3 XECORE4SLM BYTE WRITE BANK3 XECORE5SLM BYTE WRITE BANK3 XECORE6SLM BYTE WRITE BANK3 XECORE7SLM Bytes ReadSLM Bytes WrittenSLM WritesSO BottleneckSO StallSO0 BottleneckSO0 StallSO1 BottleneckSO1 StallSO2 BottleneckSO2 StallSO3 BottleneckSO3 StallSO4 BottleneckSO4 StallSO5 BottleneckSO5 StallSO6 BottleneckSO6 StallSO7 BottleneckSO7 StallSQ is fullSQ00 is fullSQ01 is fullSQ10 is fullSQ11 is fullSQ20 is fullSQ30 is fullSQ40 is fullSQ50 is fullSQ60 is fullSQ70 is fullSTC PMA stallSTREAMOUT OUTPUT VERTEX COUNT SLICE0STREAMOUT OUTPUT VERTEX COUNT SLICE1STREAMOUT OUTPUT VERTEX COUNT SLICE2STREAMOUT OUTPUT VERTEX COUNT SLICE3STREAMOUT OUTPUT VERTEX COUNT SLICE4STREAMOUT OUTPUT VERTEX COUNT SLICE5STREAMOUT OUTPUT VERTEX COUNT SLICE6STREAMOUT OUTPUT VERTEX COUNT SLICE7STRIPSFAN OBJECT COUNT SLICE0STRIPSFAN OBJECT COUNT SLICE1STRIPSFAN OBJECT COUNT SLICE2STRIPSFAN OBJECT COUNT SLICE3STRIPSFAN OBJECT COUNT SLICE4STRIPSFAN OBJECT COUNT SLICE5STRIPSFAN OBJECT COUNT SLICE6STRIPSFAN OBJECT COUNT SLICE7STRIPSFAN OBJECTS CULL SLICE0STRIPSFAN OBJECTS CULL SLICE1STRIPSFAN OBJECTS CULL SLICE2STRIPSFAN OBJECTS CULL SLICE3STRIPSFAN OBJECTS CULL SLICE4STRIPSFAN OBJECTS CULL SLICE5STRIPSFAN OBJECTS CULL SLICE6STRIPSFAN OBJECTS CULL SLICE7STRIPSFAN OUTPUT READY SLICE0STRIPSFAN OUTPUT READY SLICE1STRIPSFAN OUTPUT READY SLICE2STRIPSFAN OUTPUT READY SLICE3STRIPSFAN OUTPUT READY SLICE4STRIPSFAN OUTPUT READY SLICE5STRIPSFAN OUTPUT READY SLICE6STRIPSFAN OUTPUT READY SLICE7SYSMEM BYTE READSYSMEM BYTE WRITESYSMEM TRANSACTION READSYSMEM TRANSACTION WRITESampler 0 BottleneckSampler 0 BusySampler 0 Texels LOD0Sampler 1 BottleneckSampler 1 BusySampler 1 Texels LOD0Sampler AccessesSampler BottleneckSampler Cache MissesSampler L2 cache missesSampler L2 cache misses (ss0)Sampler L2 cache misses (ss1)Sampler L2 cache misses (ss2)Sampler L2 cache misses (ss3)Sampler Slice0 Dualsubslice0 is bottleneckSampler Slice0 Xe Core0 is busySampler Slice2 Xe Core0 is busySampler TexelsSampler Texels LOD0Sampler Texels MissesSampler00 BottleneckSampler00 BusySampler20 BottleneckSamplers BottleneckSamplers BusySamples BlendedSamples Killed in FSSamples WrittenSend Pipe ActiveShader Atomic Memory AccessesShader Barrier MessagesShader Memory AccessesSlice0 DualSubslice0 Input AvailableSlice0 DualSubslice0 Sampler Output ReadySlice0 DualSubslice1 Input AvailableSlice0 DualSubslice1 Sampler Output ReadySlice0 DualSubslice2 Input AvailableSlice0 DualSubslice2 Sampler Output ReadySlice0 DualSubslice3 Input AvailableSlice0 DualSubslice3 Sampler Output ReadySlice0 DualSubslice4 Input AvailableSlice0 DualSubslice4 Sampler Output ReadySlice0 DualSubslice5 Input AvailableSlice0 DualSubslice5 Sampler Output ReadySlice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3Slice0 Dualsubslice4 Non-sampler Shader Access Stalled On L3Slice0 Dualsubslice5 Non-sampler Shader Access Stalled On L3Slice0 L3 Bank0 AccessesSlice0 L3 Bank0 ActiveSlice0 L3 Bank0 Input AvailableSlice0 L3 Bank0 Output ReadySlice0 L3 Bank0 StalledSlice0 L3 Bank1 AccessesSlice0 L3 Bank1 ActiveSlice0 L3 Bank1 Input AvailableSlice0 L3 Bank1 Output ReadySlice0 L3 Bank1 StalledSlice0 L3 Bank2 AccessesSlice0 L3 Bank2 ActiveSlice0 L3 Bank2 Input AvailableSlice0 L3 Bank2 Output ReadySlice0 L3 Bank2 StalledSlice0 L3 Bank3 AccessesSlice0 L3 Bank3 ActiveSlice0 L3 Bank3 Input AvailableSlice0 L3 Bank3 Output ReadySlice0 L3 Bank3 StalledSlice0 L3 Bank4 AccessesSlice0 L3 Bank4 ActiveSlice0 L3 Bank4 Input AvailableSlice0 L3 Bank4 Output ReadySlice0 L3 Bank4 StalledSlice0 L3 Bank5 AccessesSlice0 L3 Bank5 ActiveSlice0 L3 Bank5 Input AvailableSlice0 L3 Bank5 Output ReadySlice0 L3 Bank5 StalledSlice0 L3 Bank6 AccessesSlice0 L3 Bank6 ActiveSlice0 L3 Bank6 Input AvailableSlice0 L3 Bank6 Output ReadySlice0 L3 Bank7 AccessesSlice0 L3 Bank7 ActiveSlice0 L3 Bank7 Input AvailableSlice0 L3 Bank7 Output ReadySlice0 PS Output AvailableSlice0 Pipe0 PS Output AvailableSlice0 Pipe0 Pixel Values ReadySlice0 Pipe0 Post-EarlyZ Pixel Data ReadySlice0 Pipe1 PS Output AvailableSlice0 Pipe1 Pixel Values ReadySlice0 Pipe1 Post-EarlyZ Pixel Data ReadySlice0 Pipe2 PS Output AvailableSlice0 Pipe2 Pixel Values ReadySlice0 Pipe2 Post-EarlyZ Pixel Data ReadySlice0 Pixel Values ReadySlice0 Post-EarlyZ Pixel Data ReadySlice0 Rasterizer Input AvailableSlice0 Rasterizer Output ReadySlice0 Subslice group 0 Non-sampler Shader Access Stalled On L3Slice0 Subslice group 1 Non-sampler Shader Access Stalled On L3Slice0 Subslice group 2 Non-sampler Shader Access Stalled On L3Slice0 Subslice group 3 Non-sampler Shader Access Stalled On L3Slice0 Subslice0 Input AvailableSlice0 Subslice0 Sampler Output ReadySlice0 Subslice1 Input AvailableSlice0 Subslice1 Sampler Output ReadySlice0 Subslice2 Input AvailableSlice0 Subslice2 Sampler Output ReadySlice0 Subslice3 Input AvailableSlice0 Subslice3 Sampler Output ReadySlice0 Subslice4 Input AvailableSlice0 Subslice4 Sampler Output ReadySlice0 Subslice5 Input AvailableSlice0 Subslice5 Sampler Output ReadySlice0 Subslice6 Input AvailableSlice0 Subslice6 Sampler Output ReadySlice0 Subslice7 Input AvailableSlice0 Subslice7 Sampler Output ReadySlice0 Xe Core0 Input AvailableSlice0 Xe Core0 Non-sampler Shader Access Stalled On L3Slice0 Xe Core0 Sampler Output ReadySlice0 Xe Core1 Input AvailableSlice0 Xe Core1 Non-sampler Shader Access Stalled On L3Slice0 Xe Core1 Sampler Output ReadySlice0 Xe Core2 Input AvailableSlice0 Xe Core2 Non-sampler Shader Access Stalled On L3Slice0 Xe Core2 Sampler Output ReadySlice0 Xe Core3 Input AvailableSlice0 Xe Core3 Non-sampler Shader Access Stalled On L3Slice0 Xe Core3 Sampler Output ReadySlice1 L3 Bank0 ActiveSlice1 L3 Bank0 StalledSlice1 L3 Bank1 ActiveSlice1 L3 Bank1 StalledSlice1 L3 Bank2 ActiveSlice1 L3 Bank2 StalledSlice1 L3 Bank3 ActiveSlice1 L3 Bank3 StalledSlice1 PS Output AvailableSlice1 Pipe0 Post-EarlyZ Pixel Data ReadySlice1 Pipe1 Post-EarlyZ Pixel Data ReadySlice1 Pixel Values ReadySlice1 Post-EarlyZ Pixel Data ReadySlice1 Rasterizer Input AvailableSlice1 Rasterizer Output ReadySlice1 Subslice0 Input AvailableSlice1 Subslice0 Sampler Output ReadySlice1 Subslice1 Input AvailableSlice1 Subslice1 Sampler Output ReadySlice1 Subslice2 Input AvailableSlice1 Subslice2 Sampler Output ReadySlice1 Xe Core0 Input AvailableSlice1 Xe Core0 Non-sampler Shader Access Stalled On L3Slice1 Xe Core0 Sampler Output ReadySlice1 Xe Core1 Input AvailableSlice1 Xe Core1 Non-sampler Shader Access Stalled On L3Slice1 Xe Core1 Sampler Output ReadySlice1 Xe Core2 Input AvailableSlice1 Xe Core2 Non-sampler Shader Access Stalled On L3Slice1 Xe Core2 Sampler Output ReadySlice1 Xe Core3 Input AvailableSlice1 Xe Core3 Non-sampler Shader Access Stalled On L3Slice1 Xe Core3 Sampler Output ReadySlice2 Pipe0 Post-EarlyZ Pixel Data ReadySlice2 Pipe1 Post-EarlyZ Pixel Data ReadySlice2 Rasterizer Input AvailableSlice2 Rasterizer Output ReadySlice2 Xe Core0 Input AvailableSlice2 Xe Core0 Non-sampler Shader Access Stalled On L3Slice2 Xe Core0 Sampler Output ReadySlice2 Xe Core1 Input AvailableSlice2 Xe Core1 Non-sampler Shader Access Stalled On L3Slice2 Xe Core1 Sampler Output ReadySlice2 Xe Core2 Input AvailableSlice2 Xe Core2 Non-sampler Shader Access Stalled On L3Slice2 Xe Core2 Sampler Output ReadySlice2 Xe Core3 Input AvailableSlice2 Xe Core3 Non-sampler Shader Access Stalled On L3Slice2 Xe Core3 Sampler Output ReadySlice3 Pipe0 Post-EarlyZ Pixel Data ReadySlice3 Pipe1 Post-EarlyZ Pixel Data ReadySlice3 Rasterizer Input AvailableSlice3 Rasterizer Output ReadySlice3 Xe Core0 Input AvailableSlice3 Xe Core0 Non-sampler Shader Access Stalled On L3Slice3 Xe Core0 Sampler Output ReadySlice3 Xe Core1 Input AvailableSlice3 Xe Core1 Non-sampler Shader Access Stalled On L3Slice3 Xe Core1 Sampler Output ReadySlice3 Xe Core2 Input AvailableSlice3 Xe Core2 Non-sampler Shader Access Stalled On L3Slice3 Xe Core2 Sampler Output ReadySlice3 Xe Core3 Input AvailableSlice3 Xe Core3 Non-sampler Shader Access Stalled On L3Slice3 Xe Core3 Sampler Output ReadySlice4 Pipe0 Post-EarlyZ Pixel Data ReadySlice4 Pipe1 Post-EarlyZ Pixel Data ReadySlice4 Rasterizer Input AvailableSlice4 Rasterizer Output ReadySlice4 Xe Core0 Input AvailableSlice4 Xe Core0 Non-sampler Shader Access Stalled On L3Slice4 Xe Core0 Sampler Output ReadySlice4 Xe Core1 Input AvailableSlice4 Xe Core1 Non-sampler Shader Access Stalled On L3Slice4 Xe Core1 Sampler Output ReadySlice4 Xe Core2 Input AvailableSlice4 Xe Core2 Non-sampler Shader Access Stalled On L3Slice4 Xe Core2 Sampler Output ReadySlice4 Xe Core3 Input AvailableSlice4 Xe Core3 Non-sampler Shader Access Stalled On L3Slice4 Xe Core3 Sampler Output ReadySlice5 Pipe0 Post-EarlyZ Pixel Data ReadySlice5 Pipe1 Post-EarlyZ Pixel Data ReadySlice5 Rasterizer Input AvailableSlice5 Rasterizer Output ReadySlice5 Xe Core0 Input AvailableSlice5 Xe Core0 Non-sampler Shader Access Stalled On L3Slice5 Xe Core0 Sampler Output ReadySlice5 Xe Core1 Input AvailableSlice5 Xe Core1 Non-sampler Shader Access Stalled On L3Slice5 Xe Core1 Sampler Output ReadySlice5 Xe Core2 Input AvailableSlice5 Xe Core2 Non-sampler Shader Access Stalled On L3Slice5 Xe Core2 Sampler Output ReadySlice5 Xe Core3 Input AvailableSlice5 Xe Core3 Non-sampler Shader Access Stalled On L3Slice5 Xe Core3 Sampler Output ReadySlice6 Pipe0 Post-EarlyZ Pixel Data ReadySlice6 Pipe1 Post-EarlyZ Pixel Data ReadySlice6 Rasterizer Input AvailableSlice6 Rasterizer Output ReadySlice6 Xe Core0 Input AvailableSlice6 Xe Core0 Non-sampler Shader Access Stalled On L3Slice6 Xe Core0 Sampler Output ReadySlice6 Xe Core1 Input AvailableSlice6 Xe Core1 Non-sampler Shader Access Stalled On L3Slice6 Xe Core1 Sampler Output ReadySlice6 Xe Core2 Input AvailableSlice6 Xe Core2 Non-sampler Shader Access Stalled On L3Slice6 Xe Core2 Sampler Output ReadySlice6 Xe Core3 Input AvailableSlice6 Xe Core3 Non-sampler Shader Access Stalled On L3Slice6 Xe Core3 Sampler Output ReadySlice7 Pipe0 Post-EarlyZ Pixel Data ReadySlice7 Pipe1 Post-EarlyZ Pixel Data ReadySlice7 Rasterizer Input AvailableSlice7 Rasterizer Output ReadySlice7 Xe Core0 Input AvailableSlice7 Xe Core0 Non-sampler Shader Access Stalled On L3Slice7 Xe Core0 Sampler Output ReadySlice7 Xe Core1 Input AvailableSlice7 Xe Core1 Non-sampler Shader Access Stalled On L3Slice7 Xe Core1 Sampler Output ReadySlice7 Xe Core2 Input AvailableSlice7 Xe Core2 Non-sampler Shader Access Stalled On L3Slice7 Xe Core2 Sampler Output ReadySlice7 Xe Core3 Input AvailableSlice7 Xe Core3 Non-sampler Shader Access Stalled On L3Slice7 Xe Core3 Sampler Output ReadyStrip-Fans BottleneckTASK THREAD EXIT COUNT XECORE0TASK THREAD EXIT COUNT XECORE1TASK THREAD EXIT COUNT XECORE10TASK THREAD EXIT COUNT XECORE11TASK THREAD EXIT COUNT XECORE12TASK THREAD EXIT COUNT XECORE13TASK THREAD EXIT COUNT XECORE14TASK THREAD EXIT COUNT XECORE15TASK THREAD EXIT COUNT XECORE16TASK THREAD EXIT COUNT XECORE17TASK THREAD EXIT COUNT XECORE18TASK THREAD EXIT COUNT XECORE19TASK THREAD EXIT COUNT XECORE2TASK THREAD EXIT COUNT XECORE20TASK THREAD EXIT COUNT XECORE21TASK THREAD EXIT COUNT XECORE22TASK THREAD EXIT COUNT XECORE23TASK THREAD EXIT COUNT XECORE24TASK THREAD EXIT COUNT XECORE25TASK THREAD EXIT COUNT XECORE26TASK THREAD EXIT COUNT XECORE27TASK THREAD EXIT COUNT XECORE28TASK THREAD EXIT COUNT XECORE29TASK THREAD EXIT COUNT XECORE3TASK THREAD EXIT COUNT XECORE30TASK THREAD EXIT COUNT XECORE31TASK THREAD EXIT COUNT XECORE4TASK THREAD EXIT COUNT XECORE5TASK THREAD EXIT COUNT XECORE6TASK THREAD EXIT COUNT XECORE7TASK THREAD EXIT COUNT XECORE8TASK THREAD EXIT COUNT XECORE9TASK THREADGROUP COUNT XECORE0TASK THREADGROUP COUNT XECORE1TASK THREADGROUP COUNT XECORE10TASK THREADGROUP COUNT XECORE11TASK THREADGROUP COUNT XECORE12TASK THREADGROUP COUNT XECORE13TASK THREADGROUP COUNT XECORE14TASK THREADGROUP COUNT XECORE15TASK THREADGROUP COUNT XECORE16TASK THREADGROUP COUNT XECORE17TASK THREADGROUP COUNT XECORE18TASK THREADGROUP COUNT XECORE19TASK THREADGROUP COUNT XECORE2TASK THREADGROUP COUNT XECORE20TASK THREADGROUP COUNT XECORE21TASK THREADGROUP COUNT XECORE22TASK THREADGROUP COUNT XECORE23TASK THREADGROUP COUNT XECORE24TASK THREADGROUP COUNT XECORE25TASK THREADGROUP COUNT XECORE26TASK THREADGROUP COUNT XECORE27TASK THREADGROUP COUNT XECORE28TASK THREADGROUP COUNT XECORE29TASK THREADGROUP COUNT XECORE3TASK THREADGROUP COUNT XECORE30TASK THREADGROUP COUNT XECORE31TASK THREADGROUP COUNT XECORE4TASK THREADGROUP COUNT XECORE5TASK THREADGROUP COUNT XECORE6TASK THREADGROUP COUNT XECORE7TASK THREADGROUP COUNT XECORE8TASK THREADGROUP COUNT XECORE9TCS AVG Active per ThreadTCS AVG Stall per ThreadTCS DurationTCS EU ActiveTCS EU StallTCS Threads DispatchedTE BottleneckTES AVG Active per ThreadTES AVG Stall per ThreadTES DurationTES EU ActiveTES EU StallTES Threads DispatchedTHREAD DISPATCH INPUT AVAILABLE XECORE0THREAD DISPATCH INPUT AVAILABLE XECORE1THREAD DISPATCH INPUT AVAILABLE XECORE10THREAD DISPATCH INPUT AVAILABLE XECORE11THREAD DISPATCH INPUT AVAILABLE XECORE12THREAD DISPATCH INPUT AVAILABLE XECORE13THREAD DISPATCH INPUT AVAILABLE XECORE14THREAD DISPATCH INPUT AVAILABLE XECORE15THREAD DISPATCH INPUT AVAILABLE XECORE16THREAD DISPATCH INPUT AVAILABLE XECORE17THREAD DISPATCH INPUT AVAILABLE XECORE18THREAD DISPATCH INPUT AVAILABLE XECORE19THREAD DISPATCH INPUT AVAILABLE XECORE2THREAD DISPATCH INPUT AVAILABLE XECORE20THREAD DISPATCH INPUT AVAILABLE XECORE21THREAD DISPATCH INPUT AVAILABLE XECORE22THREAD DISPATCH INPUT AVAILABLE XECORE23THREAD DISPATCH INPUT AVAILABLE XECORE24THREAD DISPATCH INPUT AVAILABLE XECORE25THREAD DISPATCH INPUT AVAILABLE XECORE26THREAD DISPATCH INPUT AVAILABLE XECORE27THREAD DISPATCH INPUT AVAILABLE XECORE28THREAD DISPATCH INPUT AVAILABLE XECORE29THREAD DISPATCH INPUT AVAILABLE XECORE3THREAD DISPATCH INPUT AVAILABLE XECORE30THREAD DISPATCH INPUT AVAILABLE XECORE31THREAD DISPATCH INPUT AVAILABLE XECORE4THREAD DISPATCH INPUT AVAILABLE XECORE5THREAD DISPATCH INPUT AVAILABLE XECORE6THREAD DISPATCH INPUT AVAILABLE XECORE7THREAD DISPATCH INPUT AVAILABLE XECORE8THREAD DISPATCH INPUT AVAILABLE XECORE9THREAD DISPATCH PS ACTIVE CYCLES XECORE0THREAD DISPATCH PS ACTIVE CYCLES XECORE1THREAD DISPATCH PS ACTIVE CYCLES XECORE2THREAD DISPATCH PS ACTIVE CYCLES XECORE3THREAD DISPATCH PS ACTIVE CYCLES XECORE4THREAD DISPATCH PS ACTIVE CYCLES XECORE5THREAD DISPATCH PS ACTIVE CYCLES XECORE6THREAD DISPATCH PS ACTIVE CYCLES XECORE7THREAD DISPATCH PS ACTIVE XECORE0THREAD DISPATCH PS ACTIVE XECORE1THREAD DISPATCH PS ACTIVE XECORE10THREAD DISPATCH PS ACTIVE XECORE11THREAD DISPATCH PS ACTIVE XECORE12THREAD DISPATCH PS ACTIVE XECORE13THREAD DISPATCH PS ACTIVE XECORE14THREAD DISPATCH PS ACTIVE XECORE15THREAD DISPATCH PS ACTIVE XECORE16THREAD DISPATCH PS ACTIVE XECORE17THREAD DISPATCH PS ACTIVE XECORE18THREAD DISPATCH PS ACTIVE XECORE19THREAD DISPATCH PS ACTIVE XECORE2THREAD DISPATCH PS ACTIVE XECORE20THREAD DISPATCH PS ACTIVE XECORE21THREAD DISPATCH PS ACTIVE XECORE22THREAD DISPATCH PS ACTIVE XECORE23THREAD DISPATCH PS ACTIVE XECORE24THREAD DISPATCH PS ACTIVE XECORE25THREAD DISPATCH PS ACTIVE XECORE26THREAD DISPATCH PS ACTIVE XECORE27THREAD DISPATCH PS ACTIVE XECORE28THREAD DISPATCH PS ACTIVE XECORE29THREAD DISPATCH PS ACTIVE XECORE3THREAD DISPATCH PS ACTIVE XECORE30THREAD DISPATCH PS ACTIVE XECORE31THREAD DISPATCH PS ACTIVE XECORE4THREAD DISPATCH PS ACTIVE XECORE5THREAD DISPATCH PS ACTIVE XECORE6THREAD DISPATCH PS ACTIVE XECORE7THREAD DISPATCH PS ACTIVE XECORE8THREAD DISPATCH PS ACTIVE XECORE9THREAD DISPATCH QUEUE0 ACTIVE XECORE0THREAD DISPATCH QUEUE0 ACTIVE XECORE1THREAD DISPATCH QUEUE0 ACTIVE XECORE10THREAD DISPATCH QUEUE0 ACTIVE XECORE11THREAD DISPATCH QUEUE0 ACTIVE XECORE12THREAD DISPATCH QUEUE0 ACTIVE XECORE13THREAD DISPATCH QUEUE0 ACTIVE XECORE14THREAD DISPATCH QUEUE0 ACTIVE XECORE15THREAD DISPATCH QUEUE0 ACTIVE XECORE16THREAD DISPATCH QUEUE0 ACTIVE XECORE17THREAD DISPATCH QUEUE0 ACTIVE XECORE18THREAD DISPATCH QUEUE0 ACTIVE XECORE19THREAD DISPATCH QUEUE0 ACTIVE XECORE2THREAD DISPATCH QUEUE0 ACTIVE XECORE20THREAD DISPATCH QUEUE0 ACTIVE XECORE21THREAD DISPATCH QUEUE0 ACTIVE XECORE22THREAD DISPATCH QUEUE0 ACTIVE XECORE23THREAD DISPATCH QUEUE0 ACTIVE XECORE24THREAD DISPATCH QUEUE0 ACTIVE XECORE25THREAD DISPATCH QUEUE0 ACTIVE XECORE26THREAD DISPATCH QUEUE0 ACTIVE XECORE27THREAD DISPATCH QUEUE0 ACTIVE XECORE28THREAD DISPATCH QUEUE0 ACTIVE XECORE29THREAD DISPATCH QUEUE0 ACTIVE XECORE3THREAD DISPATCH QUEUE0 ACTIVE XECORE30THREAD DISPATCH QUEUE0 ACTIVE XECORE31THREAD DISPATCH QUEUE0 ACTIVE XECORE4THREAD DISPATCH QUEUE0 ACTIVE XECORE5THREAD DISPATCH QUEUE0 ACTIVE XECORE6THREAD DISPATCH QUEUE0 ACTIVE XECORE7THREAD DISPATCH QUEUE0 ACTIVE XECORE8THREAD DISPATCH QUEUE0 ACTIVE XECORE9THREAD DISPATCH QUEUE1 ACTIVE XECORE0THREAD DISPATCH QUEUE1 ACTIVE XECORE1THREAD DISPATCH QUEUE1 ACTIVE XECORE10THREAD DISPATCH QUEUE1 ACTIVE XECORE11THREAD DISPATCH QUEUE1 ACTIVE XECORE12THREAD DISPATCH QUEUE1 ACTIVE XECORE13THREAD DISPATCH QUEUE1 ACTIVE XECORE14THREAD DISPATCH QUEUE1 ACTIVE XECORE15THREAD DISPATCH QUEUE1 ACTIVE XECORE16THREAD DISPATCH QUEUE1 ACTIVE XECORE17THREAD DISPATCH QUEUE1 ACTIVE XECORE18THREAD DISPATCH QUEUE1 ACTIVE XECORE19THREAD DISPATCH QUEUE1 ACTIVE XECORE2THREAD DISPATCH QUEUE1 ACTIVE XECORE20THREAD DISPATCH QUEUE1 ACTIVE XECORE21THREAD DISPATCH QUEUE1 ACTIVE XECORE22THREAD DISPATCH QUEUE1 ACTIVE XECORE23THREAD DISPATCH QUEUE1 ACTIVE XECORE24THREAD DISPATCH QUEUE1 ACTIVE XECORE25THREAD DISPATCH QUEUE1 ACTIVE XECORE26THREAD DISPATCH QUEUE1 ACTIVE XECORE27THREAD DISPATCH QUEUE1 ACTIVE XECORE28THREAD DISPATCH QUEUE1 ACTIVE XECORE29THREAD DISPATCH QUEUE1 ACTIVE XECORE3THREAD DISPATCH QUEUE1 ACTIVE XECORE30THREAD DISPATCH QUEUE1 ACTIVE XECORE31THREAD DISPATCH QUEUE1 ACTIVE XECORE4THREAD DISPATCH QUEUE1 ACTIVE XECORE5THREAD DISPATCH QUEUE1 ACTIVE XECORE6THREAD DISPATCH QUEUE1 ACTIVE XECORE7THREAD DISPATCH QUEUE1 ACTIVE XECORE8THREAD DISPATCH QUEUE1 ACTIVE XECORE9THREAD DISPATCH STALL XECORE0THREAD DISPATCH STALL XECORE1THREAD DISPATCH STALL XECORE10THREAD DISPATCH STALL XECORE11THREAD DISPATCH STALL XECORE12THREAD DISPATCH STALL XECORE13THREAD DISPATCH STALL XECORE14THREAD DISPATCH STALL XECORE15THREAD DISPATCH STALL XECORE16THREAD DISPATCH STALL XECORE17THREAD DISPATCH STALL XECORE18THREAD DISPATCH STALL XECORE19THREAD DISPATCH STALL XECORE2THREAD DISPATCH STALL XECORE20THREAD DISPATCH STALL XECORE21THREAD DISPATCH STALL XECORE22THREAD DISPATCH STALL XECORE23THREAD DISPATCH STALL XECORE24THREAD DISPATCH STALL XECORE25THREAD DISPATCH STALL XECORE26THREAD DISPATCH STALL XECORE27THREAD DISPATCH STALL XECORE28THREAD DISPATCH STALL XECORE29THREAD DISPATCH STALL XECORE3THREAD DISPATCH STALL XECORE30THREAD DISPATCH STALL XECORE31THREAD DISPATCH STALL XECORE4THREAD DISPATCH STALL XECORE5THREAD DISPATCH STALL XECORE6THREAD DISPATCH STALL XECORE7THREAD DISPATCH STALL XECORE8THREAD DISPATCH STALL XECORE9THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE0THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE1THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE2THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE3THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE4THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE5THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE6THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE7THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE10THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE11THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE12THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE13THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE14THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE15THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE16THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE17THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE18THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE19THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE20THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE21THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE22THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE23THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE24THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE25THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE26THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE27THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE28THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE29THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE30THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE31THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE8THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE9THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE0THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE1THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE2THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE3THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE4THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE5THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE6THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE7THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE10THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE11THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE12THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE13THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE14THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE15THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE16THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE17THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE18THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE19THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE20THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE21THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE22THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE23THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE24THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE25THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE26THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE27THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE28THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE29THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE30THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE31THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE8THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE9THREADGROUP DISPATCH RESOURCE STALL XECORE0THREADGROUP DISPATCH RESOURCE STALL XECORE1THREADGROUP DISPATCH RESOURCE STALL XECORE10THREADGROUP DISPATCH RESOURCE STALL XECORE11THREADGROUP DISPATCH RESOURCE STALL XECORE12THREADGROUP DISPATCH RESOURCE STALL XECORE13THREADGROUP DISPATCH RESOURCE STALL XECORE14THREADGROUP DISPATCH RESOURCE STALL XECORE15THREADGROUP DISPATCH RESOURCE STALL XECORE16THREADGROUP DISPATCH RESOURCE STALL XECORE17THREADGROUP DISPATCH RESOURCE STALL XECORE18THREADGROUP DISPATCH RESOURCE STALL XECORE19THREADGROUP DISPATCH RESOURCE STALL XECORE2THREADGROUP DISPATCH RESOURCE STALL XECORE20THREADGROUP DISPATCH RESOURCE STALL XECORE21THREADGROUP DISPATCH RESOURCE STALL XECORE22THREADGROUP DISPATCH RESOURCE STALL XECORE23THREADGROUP DISPATCH RESOURCE STALL XECORE24THREADGROUP DISPATCH RESOURCE STALL XECORE25THREADGROUP DISPATCH RESOURCE STALL XECORE26THREADGROUP DISPATCH RESOURCE STALL XECORE27THREADGROUP DISPATCH RESOURCE STALL XECORE28THREADGROUP DISPATCH RESOURCE STALL XECORE29THREADGROUP DISPATCH RESOURCE STALL XECORE3THREADGROUP DISPATCH RESOURCE STALL XECORE30THREADGROUP DISPATCH RESOURCE STALL XECORE31THREADGROUP DISPATCH RESOURCE STALL XECORE4THREADGROUP DISPATCH RESOURCE STALL XECORE5THREADGROUP DISPATCH RESOURCE STALL XECORE6THREADGROUP DISPATCH RESOURCE STALL XECORE7THREADGROUP DISPATCH RESOURCE STALL XECORE8THREADGROUP DISPATCH RESOURCE STALL XECORE9TestCounter0TestCounter1TestCounter2TestCounter3TestCounter4TestCounter5TestCounter6TestCounter7TestCounter8TestCounter9 - OAR enableThread Header Ready on Slice0 DualSubslice0 Thread DispatcherThread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice0 Thread Dispatcher Port 3Thread Header Ready on Slice0 DualSubslice1 Thread DispatcherThread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice1 Thread Dispatcher Port 3Thread Header Ready on Slice0 DualSubslice2 Thread DispatcherThread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice2 Thread Dispatcher Port 3Thread Header Ready on Slice0 DualSubslice3 Thread DispatcherThread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice3 Thread Dispatcher Port 3Thread Header Ready on Slice0 DualSubslice4 Thread DispatcherThread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice4 Thread Dispatcher Port 3Thread Header Ready on Slice0 DualSubslice5 Thread DispatcherThread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 0Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 1Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 2Thread Header Ready on Slice0 DualSubslice5 Thread Dispatcher Port 3Thread Header Ready on Slice0 Subslice0 Port 0Thread Header Ready on Slice0 Subslice0 Port 1Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice1 Port 0Thread Header Ready on Slice0 Subslice1 Port 1Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice2 Port 0Thread Header Ready on Slice0 Subslice2 Port 1Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 1Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 0Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 1Thread Header Ready on Slice0 Xe Core0 Thread DispatcherThread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice0 Xe Core1 Thread DispatcherThread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice0 Xe Core2 Thread DispatcherThread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice0 Xe Core3 Thread DispatcherThread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice1 Subslice0 Port 0Thread Header Ready on Slice1 Subslice0 Port 1Thread Header Ready on Slice1 Subslice1 Port 0Thread Header Ready on Slice1 Subslice1 Port 1Thread Header Ready on Slice1 Subslice2 Port 0Thread Header Ready on Slice1 Subslice2 Port 1Thread Header Ready on Slice1 Xe Core0 Thread DispatcherThread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice1 Xe Core1 Thread DispatcherThread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice1 Xe Core2 Thread DispatcherThread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice1 Xe Core3 Thread DispatcherThread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice2 Xe Core0 Thread DispatcherThread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice2 Xe Core1 Thread DispatcherThread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice2 Xe Core2 Thread DispatcherThread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice2 Xe Core3 Thread DispatcherThread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice3 Xe Core0 Thread DispatcherThread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice3 Xe Core1 Thread DispatcherThread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice3 Xe Core2 Thread DispatcherThread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice3 Xe Core3 Thread DispatcherThread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice4 Xe Core0 Thread DispatcherThread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice4 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice4 Xe Core1 Thread DispatcherThread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice4 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice4 Xe Core2 Thread DispatcherThread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice4 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice4 Xe Core3 Thread DispatcherThread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice4 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice5 Xe Core0 Thread DispatcherThread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice5 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice5 Xe Core1 Thread DispatcherThread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice5 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice5 Xe Core2 Thread DispatcherThread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice5 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice5 Xe Core3 Thread DispatcherThread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice5 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice6 Xe Core0 Thread DispatcherThread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice6 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice6 Xe Core1 Thread DispatcherThread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice6 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice6 Xe Core2 Thread DispatcherThread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice6 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice6 Xe Core3 Thread DispatcherThread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice6 Xe Core3 Thread Dispatcher Port 3Thread Header Ready on Slice7 Xe Core0 Thread DispatcherThread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 0Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 1Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 2Thread Header Ready on Slice7 Xe Core0 Thread Dispatcher Port 3Thread Header Ready on Slice7 Xe Core1 Thread DispatcherThread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 0Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 1Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 2Thread Header Ready on Slice7 Xe Core1 Thread Dispatcher Port 3Thread Header Ready on Slice7 Xe Core2 Thread DispatcherThread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 0Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 1Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 2Thread Header Ready on Slice7 Xe Core2 Thread Dispatcher Port 3Thread Header Ready on Slice7 Xe Core3 Thread DispatcherThread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 0Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 1Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 2Thread Header Ready on Slice7 Xe Core3 Thread Dispatcher Port 3Typed AtomicsTyped Atomics 0Typed Atomics 00Typed Atomics AccessesTyped Bytes ReadTyped Bytes WrittenTyped Reads 0Typed Reads 00Typed Writes 0Typed Writes 00TypedAtomicsPerCacheLineTypedReadsPerCacheLineTypedWritesPerCacheLineURB CROSS SLICE READ SLICE0URB CROSS SLICE READ SLICE1URB CROSS SLICE READ SLICE2URB CROSS SLICE READ SLICE3URB CROSS SLICE READ SLICE4URB CROSS SLICE READ SLICE5URB CROSS SLICE READ SLICE6URB CROSS SLICE READ SLICE7URB READ SLICE0URB READ SLICE1URB READ SLICE2URB READ SLICE3URB READ SLICE4URB READ SLICE5URB READ SLICE6URB READ SLICE7URB WRITE SLICE0URB WRITE SLICE1URB WRITE SLICE2URB WRITE SLICE3URB WRITE SLICE4URB WRITE SLICE5URB WRITE SLICE6URB WRITE SLICE7Untyped Bytes ReadUntyped Reads 0Untyped Reads 00Untyped WritesUntyped Writes 0Untyped Writes 00UntypedReadsPerCacheLineUntypedWritesPerCacheLineVERTEX FETCH INPUT AVAILABLE SLICE0VERTEX FETCH INPUT AVAILABLE SLICE1VERTEX FETCH INPUT AVAILABLE SLICE2VERTEX FETCH INPUT AVAILABLE SLICE3VERTEX FETCH INPUT AVAILABLE SLICE4VERTEX FETCH INPUT AVAILABLE SLICE5VERTEX FETCH INPUT AVAILABLE SLICE6VERTEX FETCH INPUT AVAILABLE SLICE7VERTEX FETCH OUTPUT READY SLICE0VERTEX FETCH OUTPUT READY SLICE1VERTEX FETCH OUTPUT READY SLICE2VERTEX FETCH OUTPUT READY SLICE3VERTEX FETCH OUTPUT READY SLICE4VERTEX FETCH OUTPUT READY SLICE5VERTEX FETCH OUTPUT READY SLICE6VERTEX FETCH OUTPUT READY SLICE7VF BottleneckVF0 BottleneckVF1 BottleneckVF2 BottleneckVF3 BottleneckVF4 BottleneckVF5 BottleneckVF6 BottleneckVF7 BottleneckVME BusyVS AVG Active per ThreadVS AVG Stall per ThreadVS BottleneckVS DurationVS EM Pipe ActiveVS EU ActiveVS EU StallVS FPU Pipe ActiveVS FPU0 Pipe ActiveVS FPU1 Pipe ActiveVS OUTPUT READY SLICE0VS OUTPUT READY SLICE1VS OUTPUT READY SLICE2VS OUTPUT READY SLICE3VS OUTPUT READY SLICE4VS OUTPUT READY SLICE5VS OUTPUT READY SLICE6VS OUTPUT READY SLICE7VS Send Pipe ActiveVS Threads DispatchedVS is sending vertices to CLVS0 BottleneckVS1 BottleneckVS2 BottleneckVS3 BottleneckVS4 BottleneckVS5 BottleneckVS6 BottleneckVS7 BottleneckVdbox0 Ring BusyVdbox00 Ring BusyVdbox1 Ring BusyVdbox10 Ring BusyVebox Ring BusyVebox0 Ring BusyVebox1 Ring BusyXMX And FPU Pipes ActiveXMX Pipe ActiveXVE ACTIVEXVE ACTIVE ASYNC CSXVE ACTIVE CSXVE ACTIVE CYCLESXVE ACTIVE CYCLES ASYNC CSXVE ACTIVE CYCLES CSXVE ACTIVE CYCLES DSXVE ACTIVE CYCLES FSXVE ACTIVE CYCLES GSXVE ACTIVE CYCLES HSXVE ACTIVE CYCLES MSXVE ACTIVE CYCLES RTXVE ACTIVE CYCLES TSXVE ACTIVE CYCLES VSXVE ACTIVE DSXVE ACTIVE FSXVE ACTIVE GSXVE ACTIVE HSXVE ACTIVE MSXVE ACTIVE RTXVE ACTIVE TSXVE ACTIVE VSXVE ATOMIC ACCESS COUNTXVE AVG IPC RateXVE ActiveXVE BARRIER MESSAGE COUNTXVE BUSYXVE COMPUTE THREAD COUNTXVE DATAPORT ATOMIC MESSAGE COUNT XECORE0XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1XVE DATAPORT ATOMIC MESSAGE COUNT XECORE10XVE DATAPORT ATOMIC MESSAGE COUNT XECORE11XVE DATAPORT ATOMIC MESSAGE COUNT XECORE12XVE DATAPORT ATOMIC MESSAGE COUNT XECORE13XVE DATAPORT ATOMIC MESSAGE COUNT XECORE14XVE DATAPORT ATOMIC MESSAGE COUNT XECORE15XVE DATAPORT ATOMIC MESSAGE COUNT XECORE16XVE DATAPORT ATOMIC MESSAGE COUNT XECORE17XVE DATAPORT ATOMIC MESSAGE COUNT XECORE18XVE DATAPORT ATOMIC MESSAGE COUNT XECORE19XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2XVE DATAPORT ATOMIC MESSAGE COUNT XECORE20XVE DATAPORT ATOMIC MESSAGE COUNT XECORE21XVE DATAPORT ATOMIC MESSAGE COUNT XECORE22XVE DATAPORT ATOMIC MESSAGE COUNT XECORE23XVE DATAPORT ATOMIC MESSAGE COUNT XECORE24XVE DATAPORT ATOMIC MESSAGE COUNT XECORE25XVE DATAPORT ATOMIC MESSAGE COUNT XECORE26XVE DATAPORT ATOMIC MESSAGE COUNT XECORE27XVE DATAPORT ATOMIC MESSAGE COUNT XECORE28XVE DATAPORT ATOMIC MESSAGE COUNT XECORE29XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3XVE DATAPORT ATOMIC MESSAGE COUNT XECORE30XVE DATAPORT ATOMIC MESSAGE COUNT XECORE31XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7XVE DATAPORT ATOMIC MESSAGE COUNT XECORE8XVE DATAPORT ATOMIC MESSAGE COUNT XECORE9XVE DATAPORT FENCE MESSAGE COUNT XECORE0XVE DATAPORT FENCE MESSAGE COUNT XECORE1XVE DATAPORT FENCE MESSAGE COUNT XECORE10XVE DATAPORT FENCE MESSAGE COUNT XECORE11XVE DATAPORT FENCE MESSAGE COUNT XECORE12XVE DATAPORT FENCE MESSAGE COUNT XECORE13XVE DATAPORT FENCE MESSAGE COUNT XECORE14XVE DATAPORT FENCE MESSAGE COUNT XECORE15XVE DATAPORT FENCE MESSAGE COUNT XECORE16XVE DATAPORT FENCE MESSAGE COUNT XECORE17XVE DATAPORT FENCE MESSAGE COUNT XECORE18XVE DATAPORT FENCE MESSAGE COUNT XECORE19XVE DATAPORT FENCE MESSAGE COUNT XECORE2XVE DATAPORT FENCE MESSAGE COUNT XECORE20XVE DATAPORT FENCE MESSAGE COUNT XECORE21XVE DATAPORT FENCE MESSAGE COUNT XECORE22XVE DATAPORT FENCE MESSAGE COUNT XECORE23XVE DATAPORT FENCE MESSAGE COUNT XECORE24XVE DATAPORT FENCE MESSAGE COUNT XECORE25XVE DATAPORT FENCE MESSAGE COUNT XECORE26XVE DATAPORT FENCE MESSAGE COUNT XECORE27XVE DATAPORT FENCE MESSAGE COUNT XECORE28XVE DATAPORT FENCE MESSAGE COUNT XECORE29XVE DATAPORT FENCE MESSAGE COUNT XECORE3XVE DATAPORT FENCE MESSAGE COUNT XECORE30XVE DATAPORT FENCE MESSAGE COUNT XECORE31XVE DATAPORT FENCE MESSAGE COUNT XECORE4XVE DATAPORT FENCE MESSAGE COUNT XECORE5XVE DATAPORT FENCE MESSAGE COUNT XECORE6XVE DATAPORT FENCE MESSAGE COUNT XECORE7XVE DATAPORT FENCE MESSAGE COUNT XECORE8XVE DATAPORT FENCE MESSAGE COUNT XECORE9XVE DATAPORT READ MESSAGE COUNT XECORE0XVE DATAPORT READ MESSAGE COUNT XECORE1XVE DATAPORT READ MESSAGE COUNT XECORE10XVE DATAPORT READ MESSAGE COUNT XECORE11XVE DATAPORT READ MESSAGE COUNT XECORE12XVE DATAPORT READ MESSAGE COUNT XECORE13XVE DATAPORT READ MESSAGE COUNT XECORE14XVE DATAPORT READ MESSAGE COUNT XECORE15XVE DATAPORT READ MESSAGE COUNT XECORE16XVE DATAPORT READ MESSAGE COUNT XECORE17XVE DATAPORT READ MESSAGE COUNT XECORE18XVE DATAPORT READ MESSAGE COUNT XECORE19XVE DATAPORT READ MESSAGE COUNT XECORE2XVE DATAPORT READ MESSAGE COUNT XECORE20XVE DATAPORT READ MESSAGE COUNT XECORE21XVE DATAPORT READ MESSAGE COUNT XECORE22XVE DATAPORT READ MESSAGE COUNT XECORE23XVE DATAPORT READ MESSAGE COUNT XECORE24XVE DATAPORT READ MESSAGE COUNT XECORE25XVE DATAPORT READ MESSAGE COUNT XECORE26XVE DATAPORT READ MESSAGE COUNT XECORE27XVE DATAPORT READ MESSAGE COUNT XECORE28XVE DATAPORT READ MESSAGE COUNT XECORE29XVE DATAPORT READ MESSAGE COUNT XECORE3XVE DATAPORT READ MESSAGE COUNT XECORE30XVE DATAPORT READ MESSAGE COUNT XECORE31XVE DATAPORT READ MESSAGE COUNT XECORE4XVE DATAPORT READ MESSAGE COUNT XECORE5XVE DATAPORT READ MESSAGE COUNT XECORE6XVE DATAPORT READ MESSAGE COUNT XECORE7XVE DATAPORT READ MESSAGE COUNT XECORE8XVE DATAPORT READ MESSAGE COUNT XECORE9XVE DATAPORT REGISTER REQUEST COUNT XECORE0XVE DATAPORT REGISTER REQUEST COUNT XECORE1XVE DATAPORT REGISTER REQUEST COUNT XECORE10XVE DATAPORT REGISTER REQUEST COUNT XECORE11XVE DATAPORT REGISTER REQUEST COUNT XECORE12XVE DATAPORT REGISTER REQUEST COUNT XECORE13XVE DATAPORT REGISTER REQUEST COUNT XECORE14XVE DATAPORT REGISTER REQUEST COUNT XECORE15XVE DATAPORT REGISTER REQUEST COUNT XECORE16XVE DATAPORT REGISTER REQUEST COUNT XECORE17XVE DATAPORT REGISTER REQUEST COUNT XECORE18XVE DATAPORT REGISTER REQUEST COUNT XECORE19XVE DATAPORT REGISTER REQUEST COUNT XECORE2XVE DATAPORT REGISTER REQUEST COUNT XECORE20XVE DATAPORT REGISTER REQUEST COUNT XECORE21XVE DATAPORT REGISTER REQUEST COUNT XECORE22XVE DATAPORT REGISTER REQUEST COUNT XECORE23XVE DATAPORT REGISTER REQUEST COUNT XECORE24XVE DATAPORT REGISTER REQUEST COUNT XECORE25XVE DATAPORT REGISTER REQUEST COUNT XECORE26XVE DATAPORT REGISTER REQUEST COUNT XECORE27XVE DATAPORT REGISTER REQUEST COUNT XECORE28XVE DATAPORT REGISTER REQUEST COUNT XECORE29XVE DATAPORT REGISTER REQUEST COUNT XECORE3XVE DATAPORT REGISTER REQUEST COUNT XECORE30XVE DATAPORT REGISTER REQUEST COUNT XECORE31XVE DATAPORT REGISTER REQUEST COUNT XECORE4XVE DATAPORT REGISTER REQUEST COUNT XECORE5XVE DATAPORT REGISTER REQUEST COUNT XECORE6XVE DATAPORT REGISTER REQUEST COUNT XECORE7XVE DATAPORT REGISTER REQUEST COUNT XECORE8XVE DATAPORT REGISTER REQUEST COUNT XECORE9XVE DATAPORT REGISTER RESPONSE COUNT XECORE0XVE DATAPORT REGISTER RESPONSE COUNT XECORE1XVE DATAPORT REGISTER RESPONSE COUNT XECORE10XVE DATAPORT REGISTER RESPONSE COUNT XECORE11XVE DATAPORT REGISTER RESPONSE COUNT XECORE12XVE DATAPORT REGISTER RESPONSE COUNT XECORE13XVE DATAPORT REGISTER RESPONSE COUNT XECORE14XVE DATAPORT REGISTER RESPONSE COUNT XECORE15XVE DATAPORT REGISTER RESPONSE COUNT XECORE16XVE DATAPORT REGISTER RESPONSE COUNT XECORE17XVE DATAPORT REGISTER RESPONSE COUNT XECORE18XVE DATAPORT REGISTER RESPONSE COUNT XECORE19XVE DATAPORT REGISTER RESPONSE COUNT XECORE2XVE DATAPORT REGISTER RESPONSE COUNT XECORE20XVE DATAPORT REGISTER RESPONSE COUNT XECORE21XVE DATAPORT REGISTER RESPONSE COUNT XECORE22XVE DATAPORT REGISTER RESPONSE COUNT XECORE23XVE DATAPORT REGISTER RESPONSE COUNT XECORE24XVE DATAPORT REGISTER RESPONSE COUNT XECORE25XVE DATAPORT REGISTER RESPONSE COUNT XECORE26XVE DATAPORT REGISTER RESPONSE COUNT XECORE27XVE DATAPORT REGISTER RESPONSE COUNT XECORE28XVE DATAPORT REGISTER RESPONSE COUNT XECORE29XVE DATAPORT REGISTER RESPONSE COUNT XECORE3XVE DATAPORT REGISTER RESPONSE COUNT XECORE30XVE DATAPORT REGISTER RESPONSE COUNT XECORE31XVE DATAPORT REGISTER RESPONSE COUNT XECORE4XVE DATAPORT REGISTER RESPONSE COUNT XECORE5XVE DATAPORT REGISTER RESPONSE COUNT XECORE6XVE DATAPORT REGISTER RESPONSE COUNT XECORE7XVE DATAPORT REGISTER RESPONSE COUNT XECORE8XVE DATAPORT REGISTER RESPONSE COUNT XECORE9XVE DATAPORT WRITE MESSAGE COUNT XECORE0XVE DATAPORT WRITE MESSAGE COUNT XECORE1XVE DATAPORT WRITE MESSAGE COUNT XECORE10XVE DATAPORT WRITE MESSAGE COUNT XECORE11XVE DATAPORT WRITE MESSAGE COUNT XECORE12XVE DATAPORT WRITE MESSAGE COUNT XECORE13XVE DATAPORT WRITE MESSAGE COUNT XECORE14XVE DATAPORT WRITE MESSAGE COUNT XECORE15XVE DATAPORT WRITE MESSAGE COUNT XECORE16XVE DATAPORT WRITE MESSAGE COUNT XECORE17XVE DATAPORT WRITE MESSAGE COUNT XECORE18XVE DATAPORT WRITE MESSAGE COUNT XECORE19XVE DATAPORT WRITE MESSAGE COUNT XECORE2XVE DATAPORT WRITE MESSAGE COUNT XECORE20XVE DATAPORT WRITE MESSAGE COUNT XECORE21XVE DATAPORT WRITE MESSAGE COUNT XECORE22XVE DATAPORT WRITE MESSAGE COUNT XECORE23XVE DATAPORT WRITE MESSAGE COUNT XECORE24XVE DATAPORT WRITE MESSAGE COUNT XECORE25XVE DATAPORT WRITE MESSAGE COUNT XECORE26XVE DATAPORT WRITE MESSAGE COUNT XECORE27XVE DATAPORT WRITE MESSAGE COUNT XECORE28XVE DATAPORT WRITE MESSAGE COUNT XECORE29XVE DATAPORT WRITE MESSAGE COUNT XECORE3XVE DATAPORT WRITE MESSAGE COUNT XECORE30XVE DATAPORT WRITE MESSAGE COUNT XECORE31XVE DATAPORT WRITE MESSAGE COUNT XECORE4XVE DATAPORT WRITE MESSAGE COUNT XECORE5XVE DATAPORT WRITE MESSAGE COUNT XECORE6XVE DATAPORT WRITE MESSAGE COUNT XECORE7XVE DATAPORT WRITE MESSAGE COUNT XECORE8XVE DATAPORT WRITE MESSAGE COUNT XECORE9XVE FPU Pipe ActiveXVE INST EXECUTED ALU0 ALLXVE INST EXECUTED ALU0 ALL UTILIZATIONXVE INST EXECUTED ALU0 ASYNC CSXVE INST EXECUTED ALU0 ASYNC CS UTILIZATIONXVE INST EXECUTED ALU0 CSXVE INST EXECUTED ALU0 CS UTILIZATIONXVE INST EXECUTED ALU0 DSXVE INST EXECUTED ALU0 DS UTILIZATIONXVE INST EXECUTED ALU0 FSXVE INST EXECUTED ALU0 FS UTILIZATIONXVE INST EXECUTED ALU0 GSXVE INST EXECUTED ALU0 GS UTILIZATIONXVE INST EXECUTED ALU0 HSXVE INST EXECUTED ALU0 HS UTILIZATIONXVE INST EXECUTED ALU0 MSXVE INST EXECUTED ALU0 MS UTILIZATIONXVE INST EXECUTED ALU0 RT AHSXVE INST EXECUTED ALU0 RT AHS UTILIZATIONXVE INST EXECUTED ALU0 RT CHSXVE INST EXECUTED ALU0 RT CHS UTILIZATIONXVE INST EXECUTED ALU0 RT MSXVE INST EXECUTED ALU0 RT MS UTILIZATIONXVE INST EXECUTED ALU0 TSXVE INST EXECUTED ALU0 TS UTILIZATIONXVE INST EXECUTED ALU0 VSXVE INST EXECUTED ALU0 VS UTILIZATIONXVE INST EXECUTED ALU1 ALLXVE INST EXECUTED ALU1 ALL UTILIZATIONXVE INST EXECUTED ALU1 ASYNC CSXVE INST EXECUTED ALU1 ASYNC CS UTILIZATIONXVE INST EXECUTED ALU1 CSXVE INST EXECUTED ALU1 CS UTILIZATIONXVE INST EXECUTED ALU1 DSXVE INST EXECUTED ALU1 DS UTILIZATIONXVE INST EXECUTED ALU1 FSXVE INST EXECUTED ALU1 FS UTILIZATIONXVE INST EXECUTED ALU1 GSXVE INST EXECUTED ALU1 GS UTILIZATIONXVE INST EXECUTED ALU1 HSXVE INST EXECUTED ALU1 HS UTILIZATIONXVE INST EXECUTED ALU1 MSXVE INST EXECUTED ALU1 MS UTILIZATIONXVE INST EXECUTED ALU1 RT AHSXVE INST EXECUTED ALU1 RT AHS UTILIZATIONXVE INST EXECUTED ALU1 RT CHSXVE INST EXECUTED ALU1 RT CHS UTILIZATIONXVE INST EXECUTED ALU1 RT MSXVE INST EXECUTED ALU1 RT MS UTILIZATIONXVE INST EXECUTED ALU1 TSXVE INST EXECUTED ALU1 TS UTILIZATIONXVE INST EXECUTED ALU1 VSXVE INST EXECUTED ALU1 VS UTILIZATIONXVE INST EXECUTED CONTROL ALLXVE INST EXECUTED CONTROL ALL UTILIZATIONXVE INST EXECUTED FP16XVE INST EXECUTED FP16 UTILIZATIONXVE INST EXECUTED FP32XVE INST EXECUTED FP32 UTILIZATIONXVE INST EXECUTED FP64XVE INST EXECUTED FP64 UTILIZATIONXVE INST EXECUTED INT16XVE INST EXECUTED INT16 UTILIZATIONXVE INST EXECUTED INT32XVE INST EXECUTED INT32 UTILIZATIONXVE INST EXECUTED MATHXVE INST EXECUTED MATH UTILIZATIONXVE INST EXECUTED SEND ALLXVE INST EXECUTED SEND ALL UTILIZATIONXVE INST EXECUTED SEND ASYNC CSXVE INST EXECUTED SEND ASYNC CS UTILIZATIONXVE INST EXECUTED SEND CSXVE INST EXECUTED SEND CS UTILIZATIONXVE INST EXECUTED SEND DSXVE INST EXECUTED SEND DS UTILIZATIONXVE INST EXECUTED SEND FSXVE INST EXECUTED SEND FS UTILIZATIONXVE INST EXECUTED SEND GSXVE INST EXECUTED SEND GS UTILIZATIONXVE INST EXECUTED SEND HSXVE INST EXECUTED SEND HS UTILIZATIONXVE INST EXECUTED SEND MSXVE INST EXECUTED SEND MS UTILIZATIONXVE INST EXECUTED SEND RT AHSXVE INST EXECUTED SEND RT AHS UTILIZATIONXVE INST EXECUTED SEND RT CHSXVE INST EXECUTED SEND RT CHS UTILIZATIONXVE INST EXECUTED SEND RT MSXVE INST EXECUTED SEND RT MS UTILIZATIONXVE INST EXECUTED SEND TSXVE INST EXECUTED SEND TS UTILIZATIONXVE INST EXECUTED SEND VSXVE INST EXECUTED SEND VS UTILIZATIONXVE INST EXECUTED XMX ALLXVE INST EXECUTED XMX ALL UTILIZATIONXVE INST EXECUTED XMX BF16XVE INST EXECUTED XMX BF16 UTILIZATIONXVE INST EXECUTED XMX FP16XVE INST EXECUTED XMX FP16 UTILIZATIONXVE INST EXECUTED XMX INT8XVE INST EXECUTED XMX INT8 UTILIZATIONXVE INST ISSUED ALL XECORE0 XVE0XVE INST ISSUED ALL XECORE1 XVE0XVE INST ISSUED ALL XECORE10 XVE0XVE INST ISSUED ALL XECORE11 XVE0XVE INST ISSUED ALL XECORE12 XVE0XVE INST ISSUED ALL XECORE13 XVE0XVE INST ISSUED ALL XECORE14 XVE0XVE INST ISSUED ALL XECORE15 XVE0XVE INST ISSUED ALL XECORE16 XVE0XVE INST ISSUED ALL XECORE17 XVE0XVE INST ISSUED ALL XECORE18 XVE0XVE INST ISSUED ALL XECORE19 XVE0XVE INST ISSUED ALL XECORE2 XVE0XVE INST ISSUED ALL XECORE20 XVE0XVE INST ISSUED ALL XECORE21 XVE0XVE INST ISSUED ALL XECORE22 XVE0XVE INST ISSUED ALL XECORE23 XVE0XVE INST ISSUED ALL XECORE24 XVE0XVE INST ISSUED ALL XECORE25 XVE0XVE INST ISSUED ALL XECORE26 XVE0XVE INST ISSUED ALL XECORE27 XVE0XVE INST ISSUED ALL XECORE28 XVE0XVE INST ISSUED ALL XECORE29 XVE0XVE INST ISSUED ALL XECORE3 XVE0XVE INST ISSUED ALL XECORE30 XVE0XVE INST ISSUED ALL XECORE31 XVE0XVE INST ISSUED ALL XECORE4 XVE0XVE INST ISSUED ALL XECORE5 XVE0XVE INST ISSUED ALL XECORE6 XVE0XVE INST ISSUED ALL XECORE7 XVE0XVE INST ISSUED ALL XECORE8 XVE0XVE INST ISSUED ALL XECORE9 XVE0XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE10XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE11XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE12XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE13XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE14XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE15XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE16XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE17XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE18XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE19XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE20XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE21XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE22XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE23XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE24XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE25XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE26XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE27XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE28XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE29XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE30XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE31XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE8XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE9XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE10XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE11XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE12XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE13XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE14XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE15XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE16XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE17XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE18XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE19XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE20XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE21XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE22XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE23XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE24XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE25XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE26XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE27XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE28XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE29XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE30XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE31XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE8XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE9XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE10XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE11XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE12XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE13XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE14XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE15XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE16XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE17XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE18XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE19XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE20XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE21XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE22XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE23XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE24XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE25XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE26XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE27XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE28XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE29XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE30XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE31XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE8XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE9XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE10XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE11XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE12XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE13XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE14XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE15XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE16XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE17XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE18XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE19XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE20XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE21XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE22XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE23XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE24XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE25XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE26XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE27XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE28XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE29XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE30XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE31XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE8XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE9XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE10XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE11XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE12XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE13XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE14XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE15XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE16XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE17XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE18XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE19XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE20XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE21XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE22XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE23XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE24XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE25XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE26XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE27XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE28XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE29XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE30XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE31XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE8XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE9XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE10XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE11XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE12XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE13XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE14XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE15XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE16XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE17XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE18XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE19XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE20XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE21XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE22XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE23XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE24XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE25XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE26XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE27XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE28XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE29XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE30XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE31XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE8XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE9XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0XVE MULTIPLE PIPE ACTIVE XECORE10 XVE0XVE MULTIPLE PIPE ACTIVE XECORE11 XVE0XVE MULTIPLE PIPE ACTIVE XECORE12 XVE0XVE MULTIPLE PIPE ACTIVE XECORE13 XVE0XVE MULTIPLE PIPE ACTIVE XECORE14 XVE0XVE MULTIPLE PIPE ACTIVE XECORE15 XVE0XVE MULTIPLE PIPE ACTIVE XECORE16 XVE0XVE MULTIPLE PIPE ACTIVE XECORE17 XVE0XVE MULTIPLE PIPE ACTIVE XECORE18 XVE0XVE MULTIPLE PIPE ACTIVE XECORE19 XVE0XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0XVE MULTIPLE PIPE ACTIVE XECORE20 XVE0XVE MULTIPLE PIPE ACTIVE XECORE21 XVE0XVE MULTIPLE PIPE ACTIVE XECORE22 XVE0XVE MULTIPLE PIPE ACTIVE XECORE23 XVE0XVE MULTIPLE PIPE ACTIVE XECORE24 XVE0XVE MULTIPLE PIPE ACTIVE XECORE25 XVE0XVE MULTIPLE PIPE ACTIVE XECORE26 XVE0XVE MULTIPLE PIPE ACTIVE XECORE27 XVE0XVE MULTIPLE PIPE ACTIVE XECORE28 XVE0XVE MULTIPLE PIPE ACTIVE XECORE29 XVE0XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0XVE MULTIPLE PIPE ACTIVE XECORE30 XVE0XVE MULTIPLE PIPE ACTIVE XECORE31 XVE0XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0XVE MULTIPLE PIPE ACTIVE XECORE8 XVE0XVE MULTIPLE PIPE ACTIVE XECORE9 XVE0XVE PIPE ALU0 AND ALU1 ACTIVEXVE PIPE ALU0 AND ALU1 ACTIVE CYCLESXVE PIPE ALU0 AND XMX ACTIVEXVE PIPE ALU0 AND XMX ACTIVE CYCLESXVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE10 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE11 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE12 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE13 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE14 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE15 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE16 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE17 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE18 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE19 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE20 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE21 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE22 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE23 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE24 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE25 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE26 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE27 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE28 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE29 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE30 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE31 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE8 XVE0 THREAD0XVE SHARED FUNCTION ACCESS HOLD XECORE9 XVE0 THREAD0XVE SLM ATOMIC MESSAGE COUNT XECORE0XVE SLM ATOMIC MESSAGE COUNT XECORE1XVE SLM ATOMIC MESSAGE COUNT XECORE10XVE SLM ATOMIC MESSAGE COUNT XECORE11XVE SLM ATOMIC MESSAGE COUNT XECORE12XVE SLM ATOMIC MESSAGE COUNT XECORE13XVE SLM ATOMIC MESSAGE COUNT XECORE14XVE SLM ATOMIC MESSAGE COUNT XECORE15XVE SLM ATOMIC MESSAGE COUNT XECORE16XVE SLM ATOMIC MESSAGE COUNT XECORE17XVE SLM ATOMIC MESSAGE COUNT XECORE18XVE SLM ATOMIC MESSAGE COUNT XECORE19XVE SLM ATOMIC MESSAGE COUNT XECORE2XVE SLM ATOMIC MESSAGE COUNT XECORE20XVE SLM ATOMIC MESSAGE COUNT XECORE21XVE SLM ATOMIC MESSAGE COUNT XECORE22XVE SLM ATOMIC MESSAGE COUNT XECORE23XVE SLM ATOMIC MESSAGE COUNT XECORE24XVE SLM ATOMIC MESSAGE COUNT XECORE25XVE SLM ATOMIC MESSAGE COUNT XECORE26XVE SLM ATOMIC MESSAGE COUNT XECORE27XVE SLM ATOMIC MESSAGE COUNT XECORE28XVE SLM ATOMIC MESSAGE COUNT XECORE29XVE SLM ATOMIC MESSAGE COUNT XECORE3XVE SLM ATOMIC MESSAGE COUNT XECORE30XVE SLM ATOMIC MESSAGE COUNT XECORE31XVE SLM ATOMIC MESSAGE COUNT XECORE4XVE SLM ATOMIC MESSAGE COUNT XECORE5XVE SLM ATOMIC MESSAGE COUNT XECORE6XVE SLM ATOMIC MESSAGE COUNT XECORE7XVE SLM ATOMIC MESSAGE COUNT XECORE8XVE SLM ATOMIC MESSAGE COUNT XECORE9XVE SLM FENCE MESSAGE COUNT XECORE0XVE SLM FENCE MESSAGE COUNT XECORE1XVE SLM FENCE MESSAGE COUNT XECORE10XVE SLM FENCE MESSAGE COUNT XECORE11XVE SLM FENCE MESSAGE COUNT XECORE12XVE SLM FENCE MESSAGE COUNT XECORE13XVE SLM FENCE MESSAGE COUNT XECORE14XVE SLM FENCE MESSAGE COUNT XECORE15XVE SLM FENCE MESSAGE COUNT XECORE16XVE SLM FENCE MESSAGE COUNT XECORE17XVE SLM FENCE MESSAGE COUNT XECORE18XVE SLM FENCE MESSAGE COUNT XECORE19XVE SLM FENCE MESSAGE COUNT XECORE2XVE SLM FENCE MESSAGE COUNT XECORE20XVE SLM FENCE MESSAGE COUNT XECORE21XVE SLM FENCE MESSAGE COUNT XECORE22XVE SLM FENCE MESSAGE COUNT XECORE23XVE SLM FENCE MESSAGE COUNT XECORE24XVE SLM FENCE MESSAGE COUNT XECORE25XVE SLM FENCE MESSAGE COUNT XECORE26XVE SLM FENCE MESSAGE COUNT XECORE27XVE SLM FENCE MESSAGE COUNT XECORE28XVE SLM FENCE MESSAGE COUNT XECORE29XVE SLM FENCE MESSAGE COUNT XECORE3XVE SLM FENCE MESSAGE COUNT XECORE30XVE SLM FENCE MESSAGE COUNT XECORE31XVE SLM FENCE MESSAGE COUNT XECORE4XVE SLM FENCE MESSAGE COUNT XECORE5XVE SLM FENCE MESSAGE COUNT XECORE6XVE SLM FENCE MESSAGE COUNT XECORE7XVE SLM FENCE MESSAGE COUNT XECORE8XVE SLM FENCE MESSAGE COUNT XECORE9XVE SLM READ MESSAGE COUNT XECORE0XVE SLM READ MESSAGE COUNT XECORE1XVE SLM READ MESSAGE COUNT XECORE10XVE SLM READ MESSAGE COUNT XECORE11XVE SLM READ MESSAGE COUNT XECORE12XVE SLM READ MESSAGE COUNT XECORE13XVE SLM READ MESSAGE COUNT XECORE14XVE SLM READ MESSAGE COUNT XECORE15XVE SLM READ MESSAGE COUNT XECORE16XVE SLM READ MESSAGE COUNT XECORE17XVE SLM READ MESSAGE COUNT XECORE18XVE SLM READ MESSAGE COUNT XECORE19XVE SLM READ MESSAGE COUNT XECORE2XVE SLM READ MESSAGE COUNT XECORE20XVE SLM READ MESSAGE COUNT XECORE21XVE SLM READ MESSAGE COUNT XECORE22XVE SLM READ MESSAGE COUNT XECORE23XVE SLM READ MESSAGE COUNT XECORE24XVE SLM READ MESSAGE COUNT XECORE25XVE SLM READ MESSAGE COUNT XECORE26XVE SLM READ MESSAGE COUNT XECORE27XVE SLM READ MESSAGE COUNT XECORE28XVE SLM READ MESSAGE COUNT XECORE29XVE SLM READ MESSAGE COUNT XECORE3XVE SLM READ MESSAGE COUNT XECORE30XVE SLM READ MESSAGE COUNT XECORE31XVE SLM READ MESSAGE COUNT XECORE4XVE SLM READ MESSAGE COUNT XECORE5XVE SLM READ MESSAGE COUNT XECORE6XVE SLM READ MESSAGE COUNT XECORE7XVE SLM READ MESSAGE COUNT XECORE8XVE SLM READ MESSAGE COUNT XECORE9XVE SLM WRITE MESSAGE COUNT XECORE0XVE SLM WRITE MESSAGE COUNT XECORE1XVE SLM WRITE MESSAGE COUNT XECORE10XVE SLM WRITE MESSAGE COUNT XECORE11XVE SLM WRITE MESSAGE COUNT XECORE12XVE SLM WRITE MESSAGE COUNT XECORE13XVE SLM WRITE MESSAGE COUNT XECORE14XVE SLM WRITE MESSAGE COUNT XECORE15XVE SLM WRITE MESSAGE COUNT XECORE16XVE SLM WRITE MESSAGE COUNT XECORE17XVE SLM WRITE MESSAGE COUNT XECORE18XVE SLM WRITE MESSAGE COUNT XECORE19XVE SLM WRITE MESSAGE COUNT XECORE2XVE SLM WRITE MESSAGE COUNT XECORE20XVE SLM WRITE MESSAGE COUNT XECORE21XVE SLM WRITE MESSAGE COUNT XECORE22XVE SLM WRITE MESSAGE COUNT XECORE23XVE SLM WRITE MESSAGE COUNT XECORE24XVE SLM WRITE MESSAGE COUNT XECORE25XVE SLM WRITE MESSAGE COUNT XECORE26XVE SLM WRITE MESSAGE COUNT XECORE27XVE SLM WRITE MESSAGE COUNT XECORE28XVE SLM WRITE MESSAGE COUNT XECORE29XVE SLM WRITE MESSAGE COUNT XECORE3XVE SLM WRITE MESSAGE COUNT XECORE30XVE SLM WRITE MESSAGE COUNT XECORE31XVE SLM WRITE MESSAGE COUNT XECORE4XVE SLM WRITE MESSAGE COUNT XECORE5XVE SLM WRITE MESSAGE COUNT XECORE6XVE SLM WRITE MESSAGE COUNT XECORE7XVE SLM WRITE MESSAGE COUNT XECORE8XVE SLM WRITE MESSAGE COUNT XECORE9XVE STALLXVE STALL ALUWR XECORE0 XVE0 THREAD0XVE STALL ALUWR XECORE1 XVE0 THREAD0XVE STALL ALUWR XECORE10 XVE0 THREAD0XVE STALL ALUWR XECORE11 XVE0 THREAD0XVE STALL ALUWR XECORE12 XVE0 THREAD0XVE STALL ALUWR XECORE13 XVE0 THREAD0XVE STALL ALUWR XECORE14 XVE0 THREAD0XVE STALL ALUWR XECORE15 XVE0 THREAD0XVE STALL ALUWR XECORE16 XVE0 THREAD0XVE STALL ALUWR XECORE17 XVE0 THREAD0XVE STALL ALUWR XECORE18 XVE0 THREAD0XVE STALL ALUWR XECORE19 XVE0 THREAD0XVE STALL ALUWR XECORE2 XVE0 THREAD0XVE STALL ALUWR XECORE20 XVE0 THREAD0XVE STALL ALUWR XECORE21 XVE0 THREAD0XVE STALL ALUWR XECORE22 XVE0 THREAD0XVE STALL ALUWR XECORE23 XVE0 THREAD0XVE STALL ALUWR XECORE24 XVE0 THREAD0XVE STALL ALUWR XECORE25 XVE0 THREAD0XVE STALL ALUWR XECORE26 XVE0 THREAD0XVE STALL ALUWR XECORE27 XVE0 THREAD0XVE STALL ALUWR XECORE28 XVE0 THREAD0XVE STALL ALUWR XECORE29 XVE0 THREAD0XVE STALL ALUWR XECORE3 XVE0 THREAD0XVE STALL ALUWR XECORE30 XVE0 THREAD0XVE STALL ALUWR XECORE31 XVE0 THREAD0XVE STALL ALUWR XECORE4 XVE0 THREAD0XVE STALL ALUWR XECORE5 XVE0 THREAD0XVE STALL ALUWR XECORE6 XVE0 THREAD0XVE STALL ALUWR XECORE7 XVE0 THREAD0XVE STALL ALUWR XECORE8 XVE0 THREAD0XVE STALL ALUWR XECORE9 XVE0 THREAD0XVE STALL ASYNC CSXVE STALL BARRIER XECORE0 XVE0 THREAD0XVE STALL BARRIER XECORE1 XVE0 THREAD0XVE STALL BARRIER XECORE10 XVE0 THREAD0XVE STALL BARRIER XECORE11 XVE0 THREAD0XVE STALL BARRIER XECORE12 XVE0 THREAD0XVE STALL BARRIER XECORE13 XVE0 THREAD0XVE STALL BARRIER XECORE14 XVE0 THREAD0XVE STALL BARRIER XECORE15 XVE0 THREAD0XVE STALL BARRIER XECORE16 XVE0 THREAD0XVE STALL BARRIER XECORE17 XVE0 THREAD0XVE STALL BARRIER XECORE18 XVE0 THREAD0XVE STALL BARRIER XECORE19 XVE0 THREAD0XVE STALL BARRIER XECORE2 XVE0 THREAD0XVE STALL BARRIER XECORE20 XVE0 THREAD0XVE STALL BARRIER XECORE21 XVE0 THREAD0XVE STALL BARRIER XECORE22 XVE0 THREAD0XVE STALL BARRIER XECORE23 XVE0 THREAD0XVE STALL BARRIER XECORE24 XVE0 THREAD0XVE STALL BARRIER XECORE25 XVE0 THREAD0XVE STALL BARRIER XECORE26 XVE0 THREAD0XVE STALL BARRIER XECORE27 XVE0 THREAD0XVE STALL BARRIER XECORE28 XVE0 THREAD0XVE STALL BARRIER XECORE29 XVE0 THREAD0XVE STALL BARRIER XECORE3 XVE0 THREAD0XVE STALL BARRIER XECORE30 XVE0 THREAD0XVE STALL BARRIER XECORE31 XVE0 THREAD0XVE STALL BARRIER XECORE4 XVE0 THREAD0XVE STALL BARRIER XECORE5 XVE0 THREAD0XVE STALL BARRIER XECORE6 XVE0 THREAD0XVE STALL BARRIER XECORE7 XVE0 THREAD0XVE STALL BARRIER XECORE8 XVE0 THREAD0XVE STALL BARRIER XECORE9 XVE0 THREAD0XVE STALL CONTROL XECORE0 XVE0 THREAD0XVE STALL CONTROL XECORE1 XVE0 THREAD0XVE STALL CONTROL XECORE2 XVE0 THREAD0XVE STALL CONTROL XECORE3 XVE0 THREAD0XVE STALL CONTROL XECORE4 XVE0 THREAD0XVE STALL CONTROL XECORE5 XVE0 THREAD0XVE STALL CONTROL XECORE6 XVE0 THREAD0XVE STALL CONTROL XECORE7 XVE0 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Basicbb080384-a01f-442f-8be2-3eae2c7394cd9f39ce80-0463-484e-b797-3135b7e0ab0a11e091e1-bbd3-4bd6-9ce8-8982d2d3a3b20f2e1818-c190-494a-a828-2ed4422d71f3ebd91ba3-4d01-4bdf-8752-384cd0a4e1395102fa66-b5f3-45f2-a16d-0a13a4cbb6c98706c725-7753-427d-ae2d-ba25c1168f2a3eab195e-e4d8-482e-9981-811935722b21100ae8ce-31c6-457f-97a2-dfd44812bce67e926c0a-471b-40b3-a641-75f3d73339ecaca9005f-fafe-4d02-a9de-b2584ff76f04ad96806d-7c0d-49f0-b844-c5010ade30af1669e79f-976e-47ba-a553-0a716ebd3c71d100e474-1e6c-4100-812b-71ec9cfe3523b22d38f6-a056-496a-8d7d-dede47051806c68abf37-fe6e-45f6-9dcb-549b3fbef69974dbc739-d871-41b5-be7b-fb547ac5bec91caf6b6d-a1ef-40d3-9033-311e482b826ee347a2bd-079d-4a77-b546-c3c114c55bae3b27f553-aebc-45ec-aa2f-926d81a91fd91fa73aed-3861-4c19-8105-e55986c8a4e52bb016ee-a9b7-477e-8d5d-f7fd179a8f16cdccda4b-c7c9-41a9-965f-fc2adf8cff0b3c44fb1b-f9b3-4d52-a507-e2b2a80ec8b7ec911098-71bf-4432-9153-6143e3cfbe0617d351db-7916-4eea-9817-29ca522daacdf2de5846-f330-4d26-ad41-824deb6b53f68f4ccb12-ee11-4741-93d4-d431b8ca58efd336f948-7e5c-41a9-be57-e3b01b8c829ac2929b2d-4ce9-4161-a1ac-fff0a75436b9a98b240c-71b7-4e72-b167-8538a581e26d5e7aa748-e1a6-4282-b3ae-48dbfb06dcf8e12f8fc0-2eb9-4bf6-bf44-a13ceb42c9f781be185c-7ac7-4a17-85fc-4144ccba4a465354b8d9-12fd-44eb-8f7d-0a4dffae44093225b6c6-805a-4e93-aaa5-5f09d87b31f9c423d483-13da-4bae-9b61-c13ec19ee450c7388ce3-9e3f-4804-a215-771791c4ea3c7ebc4a0a-5dc3-4de3-a8f8-2a6d1a95427f811a34c7-87f3-4d4d-b366-d4b5f5dc5be16ec13866-51c1-46c3-818b-c63cf38efcd54bc9e67a-0ebd-4d65-86cd-2eb961ccac5923f51139-6973-4b45-a211-778834ce2c9a4b886bf3-61ff-4381-9994-ac9b91202fc7eb6a0ef8-4e8f-41fa-85ba-686835711f6bee81cfab-667d-46c5-a2b7-17283b28c38d73acd312-486b-4aa8-bcd1-232bfb29481bef158e77-1bca-402c-b2d6-1654908fd977b997e963-d322-4d97-b631-f875b2135fc957c490ef-4993-465e-b1e0-774fbc104fdf50d02e16-414e-4b4c-adbd-71c584f857b5XGXIXWXY\\ @ @ (.@@ ( 6`4  P[ @@ @ @ IKM1eBXGXIXWXY\\ @ @'0,808$%&-. / .,@@@@@ $%&',-./`668``4       @AUU[U]@*@@@@@@@@@@@@@@ @ @ GMOQSU1WIKeBXGXIXWXY\\ @ @ ('(, $%&',-./.,@   U*$%&-. / 66`84       @AUU[U]@*@@@@@@@@@@@@@@ @ @ GMOQSU1WIKeBXGXIXWXY\\ 0@@8D8HL  @PPPs * , '$ *,`6628@`*, '$" '$&D E V O  @ @   2 (13(5153@A_[U]@* @@@@@@@@@@@@ @5 5 56@6GMOQSU1WIKeBXGXIXWXY\\ p@@DHL PTX\`d $hl(,pt04 @$$1t$Q$q$$ $$tt11123QQ RStqqq r stt @.* 468@ 8$$   @AP[U]@@@@@@@@GMOQS1eBXGXIXWXY\\ @ @> <     (|,| 1    3  " 0          @    @@ UUT@@@@@@@@@@@@ @ @@@,U.@@@@@ @  U*,@@@@@ 66&8```4&  @           UU[U]*@@@@@@@@@@@@@ @ @ MOQSU1WGIKeBXGXIXWXY\\\ @ @7G 55 [6 @@@75G565 5666GIKM1eBXGXIXWXY\\\ 0@@DH`L`  @ @@@@PpQq@6*$G6 55 @AP[,]@@@@@7@@75G5655@666GMOQ1UWIKeBXGXIXWXY\\ 0@?@DH`L` PTX\??`d $h`l(`, @V24RTrt @ 22 34445RR @RSTT Urr @r0sttt u @  @@@@@@U46@@@   U*,@@$&P"@@$&  $  @  @  @ @ @ @   @AP[U]?@K _*aGMOQSU1WIeBXGXIXWXY\\ 0@?@DH`L` PTX\??`d $h`l(`, @> >>2 >4>R >T>r >t> >> >3 @ 322 @2344453RR @RSTTT U3rr @r0sttt u3 @ 3 @@@@@@U46@@@   U*,@@$&P"@@$&  $  @  @  @ @ @ @   @AP[U]?@K _*aGMOQSU1WIeBXGXIXWXY\\ @@DHL PTX\`d $hl(,pxt0x4x|8< @&1&Q&q&&&  1111 1 1112222 2 3333QQQRSqqrs@@@@@A46@@@@@ @ @   *,@@@@@ A$&P" @@$    @ @ @ @  @AUU[]3@K_*(aGM OQS1UWIKeBXGXIXWXY\\ p@@DHL PTX\??`d $hl(,pt04 @@$@1$@Q$@q$@$@$&1111223QQQQ RRSqqqq rr0s    @@@@@U46@@@@@ @ @   U*,@@@@@ $&P"@U$&@"   $" T AU  @  @ @ @ @   @ @ @ @ @AUU[U]?@K_*aGMO Q SU1WIKeBXGXIXWXY\\ p@@DHxLx PT @Q&q&&QQQ Q QQQRRR R SSSSqqqqqqqrrrrsss @U46@@@@@ @ U*,@@@@@ $&"P$&h"    P @ @ @ @    T]U[?*a _QSU1WGIKMeBXGXIXWXY\\ 0@@@D@HL  @$ " "@@@ @@@ <""$ @   C  @ @ @ $  #$ +##]E[ 0a_@   !@ @-++!UWG2IK M1eBXX XPXP \'\) @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBXb'Xb)X`X` \a\a @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBXXXQXQ\R'\R) @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBX X X0X0 \'\) @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBX!X!X1X1\"'\") @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBX@X@ XAXA\B'\B) @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBX7X9XX \\ @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eBX2'X2) @@D @$ "@46,$&P&   C @ @ 7G 55 ] [0(a6 @@@75G565 5666UWGIK M1eB\ @@DHL PTX\`d $hl(,pt04x|8< @6,&@&   @ I]  a0UW1eBXGXIXWXY\\ @ @   ( .(:@ @ @ "$  P"@  @ @ @ P[ _I KM1eBXGXIXWXY\\ @ @   ( .(:@ @ @ "$  P"@  @ @ @ P[ _I KM1eBXGXIXWXY\\ @ @     ( .(:@ @ @ "$  P"@  @ @ @ P[ _I KM1eBXGXIXWXY\\ @ @ @(. ( :@@@"@"$` " @ @@ @ P[ _IK M1eBXGXIXWXY\\ @ @'0,8px$%&-. / .,$%&',-./:@46@@@ @ ,@@@@@ $&"P&T"$   @$&PU" @ U P T @ @ @ @ @ @ @ @ @ @AUU[U]?@K_*a GMOQS U1WIKeBXGXIXWXY\\ @ @ ('(, $%&',-./.,$%&-. / :@@@@@46@   U*?$@@U$&  @U$ T U @ U @  @ @ @ @ @ @ @ @ @AUU[U]?@K_*aG MOQSU1 WIKeBXGXIXWXY\\ @@8D8 @PPPs * ,@@@U46@@@  T*,@@ '$&" '@@A$&" f   '$ @ @D E V O  @ @ (!5(5!@A_[P]`>@K _*a @5 5 56@6G1MOQSU1 W8I11KeBXGXIXWXY\\ @@DH0L0 PTX\ @&&1&Q&q&&   $ww11123wQQQRSwqqqrsw  w  @@@@@4@@@@@ @ @   *@@@@@ $"# " @V$@"# "    "# "   T   @  @ @  @ @ @AUU[U]@K_aGMOQS1I KeBXGXIXWXY\\ @ @>|@ <    >(, @@@@U46@@@@@ @   U*,@@@@@ $&"UQ$&T"   1    3   "  A   %  @ @ @ @ @ @ @ @ @ @ @ @ @ UU[U]?_*aMO QSU1WGIKeBXGXIXWXY\\\ @ @7G 55 [6 @@@75G565 5666GIKM1eBXGXIXWXY\\\ 0@@DH`L`  @ @@@@PpQq@@@@@   @$G6 55 @AP[,]@K_a7@@75G5655@666GMOQ1UWIKeBXGXIXWXY\\ @ @08       @    $%&',-./.,@AP[U] KP_UaGMOQSU1eBXGXIXWXY\\ @ @ @   ( .[_  KM1eBXGXIXWXY\\ @ @     @ (.P[P_ IK1eBXGXIXWXY\\ @ @    @ (.P[P_ IK1eBXGXIXWXY\\ @ @    @ (.P[P_ IK1eBXGXIXWXY\\ @@DH`L` PTX\?? @> >>2 2>443 @@ 2322 @2@2<34444 5"@ @     @ @   @  @ U  @AP[U] KP_UaGMOQSU1eBXGXIXWXY\\ 0@?@DHL PTX\`d $hxl(x, @@$&@1$1&    #111111111 1122222223333p "@ @    @     @ @ @ @ #    @      @  @   @ P@@ 1 @AUU[] KUU_a   GMOQS1UWIKeBXGXIXWXY\\ 0@@@D@HL  @$ " "@ @ @   @  C  @$  #$#]D[ aD _  @    @U WIKM1eBXX XPXP \'\) @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBXb'Xb)X`X` \a\a @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBXXXQXQ\R'\R) @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBX X X0X0 \'\) @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBX!X!X1X1\"'\") @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBX@X@ XAXA\B'\B) @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBX7X9XX \\ @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eBX2'X2) @@D @$ "@ @   C 7G 55 ] [a6 @@@75G565 5666UWGIKM1eB\ @@DHL PTX\`d $hl(,pt04x|8< @@   I]aUW1eBThreadsAndRast1ThreadsAndRast3XveActivity1RenderPipeProfile1RenderPipeProfile2Sampler_Slice23Metric set HDCAndSF1Metric set HDCAndSF2RasterizerAndPixelBackend1RasterizerAndPixelBackend2TDL1TDL2TDL3TDL4ComputeOverviewL1ProfileReadsL1ProfileReads_XeCore0L1ProfileReads_XeCore3L1ProfileSlmBankConflictsL1ProfileWritesL1ProfileWrites_XeCore0L1ProfileWrites_XeCore3DataportReadsDataportWritesExt1Ext2Ext3Ext4Ext5Ext6Ext7Ext8Ext9Ext10Ext11Ext12896dda0d-84b8-4d1d-b54b-c2e5ded94581f5e936f0-aacb-4aea-80a5-d434f21d427dc9b51681-9e54-49b0-918d-4e588078d5cdc4a47a95-b80a-46d3-abf0-98a95a8404072d7c9960-0ec0-4aa2-9bd0-e6d76f214bf785afcb2a-90a8-4b1a-adc3-61e322884520780e4dd7-8360-4294-9ff6-3bef25e0fe090348b595-94ef-445f-b4e5-11d0076b630767577936-ac11-46a1-b07d-44ea1318df5bb1c1cb56-f82f-444e-b408-aebbe4777f40b45c7714-75be-4639-83b8-258392695044e63fc92b-0c14-48b8-b832-52631f75b1c6a5bd7cc2-3b17-4287-bdb2-a6814998daa1036c9033-142d-438f-a5ec-ea0ec62a6f43fbba3669-b6db-4aa8-a993-b2e51998a8ddc3ea2a23-f1c7-4a19-9da2-b569226fb6dea5e2f79b-cecb-4eff-8f29-cda8e2a5874989173c19-fcfe-48da-ac26-fb64425f141bRender Metrics Basic - aggregation approximationf5b8f05e-c84c-4f1c-bb05-68fbea73879b53ee6271-905c-4b2a-b449-9117ffd10a48952f5f55-449d-43db-87d7-6113e9c3b89aabb4b8fd-b9cd-4b11-a610-1c0707af14cf91273130-42fe-4c5e-ba34-6f9140b612c6fd9d1ad4-13b3-4583-9f2c-998f627e370d4b785529-8efb-471e-93c5-481dae7b3b8b8a0c5d31-e0cb-4d2c-8056-f3824c57ad9a0f40fba0-129a-4a19-87de-5fdbe111b91524695fb7-a404-4cd6-9aad-d23738b6d4994486113b-a8a7-4f75-a1c2-7d307fa0e00e75fc20f8-8694-47f2-b67b-cbb35f697a8ed5e02a31-fc87-4cdc-8136-4b19e00b7e94Metric set RasterizerAndPixelBackend108858210-0dc3-452b-afee-e5c7811c01cbMetric set RasterizerAndPixelBackend230b71e0c-55eb-49ed-8863-ee7db68ff1b13620f0df-42c6-4904-b395-5497f5a2ea4b28357a3a-a53b-4da4-a5b7-395dbfa501f1262cf8cb-824e-4f48-bac4-6be3d8dda6a51e629e21-abd2-418e-a184-753977bb529b57f210de-b537-464a-af7b-7dfe2f3780c137b5b93b-6acf-4726-9b57-1a65fab22bb2a2fe4388-0540-4550-b57e-6948cd7ab47a16bc63c3-d365-4bee-baf7-bafbc1aa7c2dL1ProfileSlmBankConflicts_XeCore028da4c17-4629-4111-a575-787a85100db9L1ProfileSlmBankConflicts_XeCore3825f82b5-486a-4ca2-96fa-f358871984b05d58094c-105e-4562-b53d-68185319c7943ce21cd6-fe3e-468f-ae53-07dbf73c45f954d0193f-f8e0-4b81-99ba-e73a23fd941817982512-46b0-4b58-9e8d-d59b5bf8b3f5480895b0-8013-4be1-8bbf-fc3f1ad2e97fb899d843-d8ce-4803-8174-f2bf1107de0059e0ed29-cd2d-43ee-bf49-e4637e8ef9ee475c650e-1045-45dc-a280-3365f7af8f8cb7d7a874-19d8-48e6-bf54-f859a994b0a4f1a94d28-672b-41a6-9ab9-e2040200d28a31d119ed-a150-4b52-9206-3f9832e275ea4eb14f16-d2ac-46d3-b974-e413430fddecb875dedd-f121-4f89-b02f-ff2c873e2543691b6a0d-d3d7-4b5e-a70e-d8232722cddf3c626d93-4368-4115-a21d-8fd8cd10e8fa4678846c-99cd-4a3f-acb4-8f055f48da56 @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+   + +K Kk k , @,L Ll lb   b++bKK KKbkk k kb  @  b,,bLL@LLbll@l l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+  +Kk ,Ll   ++ +KKKKkkk k   ,, ,LLLLlll l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+   @4@  4 @4 4  0 UZ O     Z   UUPRCDp 0"(Fp$p( UUUUUUd @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+   + K k @ , L l   ++KKKkk k @  ,,L@LLl@l l0HU Hg UUPR(D "F$(d @@,+  + K k , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+   ` + `+ K `K k `k  @a @, `, L `L l `l 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg UUUUB*HJ LpNPR(D "F$(d @@,+  P P NP D"!F$( B b0AB Babbd @@,+ @AQBBaQbAA ABBBaabbb HJLNPR$ F(d @@,+  ^ P H JLNP RBD "BF$(8A@A8a@aAA AAA A AAaa a a a@aaadXPX@@ ,+    B*Hd   @@@@@ @ , , kU kU k- k- ! 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@@,+@DHbLPTX\?` dh"lptx|? @G:h"$@G(, TUUT2  UU PU III2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?   @G:h#%@G), TUUT2  UU PU  UUPU   $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?   @G:h#%@G), TUUT2  UU PU     UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?   @G:h#%@G), TUUT2  UU PU  UU PU UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?   @G:h#%@G), TUUT2  UU PU  UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?  @G:h"$@G(, TUUT2  UUPU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?  @G:h"$@G(, TUUT2   UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?  @G:h"$@G(, TUUT2  UU PU UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+@DHbLPTX\?` dh"lptx|?  @G:h"$@G(, TUUT2  UU PU $$2 6&,8:<4 UUPUUUPUUUPUR @@,+  ||01_U 0 10 ||1 _U  1  $>@0!20!$400 6 UUU UUUR @@,+@DH`LPTX\?  xx @0pU P  @ 2 < @PP  xx2 0 U    2  <PP  I@"0 20 )6&,a8:<400 UPUPUP 0UUU R @@,+@D  UUUUP$P    2 6&,8:<>48AAAAHAA LA AAR @@,+ NA@A@a@a@@@@AAAaaaaPPPPR" >@246R @@,+  B b  AB BBDab bb"  PPPPR" >@246R @@,+ QBQbQQABBB00abb b  UUUUUUI"$ 2 6&,8:<>@4R @@,+  PPPI"z  2468A8a88AAAaaaR @@,+ 8A@A8a@a8@8@AA AAaa aa  UUU$ >@246R @@,+ 8A8a88AAAAaa@aa@PPPPR" >@246R @@,+   + K k  , L l    +++KKKkk k   ,,,LLLll l0HU Hg  + K k  , L l   ++KKKkkk  ,,LLLlll0HU Hg II$$D2 6&,8:<P>@@ 4R @@,+  +Kk ,Ll   ++KKKkk k   ,,LLLll l0HU Hg +Kk ,Ll  ++ +KKKkkk  ,, ,LLLlll0HU Hg II$$D2 6&,8:<P>@@ 4R @@,+  +Kk @,Ll   ++KKKkk k @  ,,L@LLl@l l0HU Hg +Kk ,Ll  ++ +KKKkkk @ ,@, ,L@LLl@ll0HU Hg II$$D2 6&,8:<P>@@ 4R @@,+  +Kk ,Ll   ++KKKkk k   ,,LLLll l0HU Hg +Kk ,Ll  ++ +KKKkkk  ,, ,LLLlll0HU Hg II$$D2 6&,8:<P>@@ 4R @@,+@DH`LPTX\?`dh`lptx|?   +Kk ,Ll   ++ +KKKkkk   ,, ,LL Lll ZUU 33 III!2 $6&,8: <>@4R @@,+@DH`LPTX\?`dh`lptx|?   +Kk ,Ll   ++ +KKKkkk   ,, ,LL Lll ZUU 33 $$$!2 $6&,8: <>@4R @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+@8DHLPT?Xp\  K K k k L L l Bl 2KKKK2kk kkk2LBLLLL2ll ll0HjUUUUIII2 6&,8:<>@4R @@,+@8DHLPT?Xp\   + +  , B, 2    2++ +++2 B    2,, ,,  HǡZgǡ III %2 6&, 8`:<> @ 4R @@,+@8DHLPT?Xp\  K K k k L L l Bl 2KKKK2kk kkk2LBLLLL2ll ll0HjUUUU$$$2 6&,8:<>@4R @@,+@8DHLPT?Xp\   + +  , B, 2    2++ +++2 B    2,, ,,  HǡZgǡ $$$ %2 6&, 8`:<> @ 4R @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+  + +K Kk k , ,L Ll l&    &++&KKKK&kkk k&    &,,&LLLL&lll l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+  + K k , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+  + K k , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+   + K k @ , L l    ++ +KKKKkkk k  @  ,, ,LL@LLll@l l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+   + K k @ , L l    ++ +KKKKkkk k  @  ,, ,LL@LLll@l l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+   ` + `+ K `K k `k  @a @, `, L `L l `l 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+   ` + `+ K `K k `k  @a @, `, L `L l `l 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg III$2 6&,8:<@>@*4R @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg $$$$2 6&,8:<@>@*4R @@,+ U   0U    U   0U   UU UU  U  UU U U III2 F 6&,8:<0>@B4 UUUUUUUUUUUUR @@,+ U   0U    U  0U  U UU U U III2 F 6&,8:<0>@B4 UUUUUUUUUUUUR @@,+  U   0U    U   0U   UU UU  U  UU U U $$$2 F 6&,8:<0>@B4 UUUUUUUUUUUUR @@,+  U   0U    U  0U  U UU U U $$$2 F 6&,8:<0>@B4 UUUUUUUUUUUURp @@,+@DH2LPRTX\`dhlpt}  `(UUTU    3 UUTU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `(UUTU    3  UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `(UUTU    3 UU TU UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `(UUTU    3 UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}   "$UUTU   # UUTU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}   "$UUTU   #  UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}   "$UUTU   # UU TU UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}   "$UUTU   # UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  UUTU 2  UUTU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  UUTU 2   UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  UUTU 2  UU TU UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  UUTU 2  UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `UUTUT  UUTU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `UUTUT   UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `UUTUT  UU TU UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  `UUTUT  UU TU $ $` 2 6&,8:<>@c 4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  S`(UUTU@  Rx | UUTU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  S`(UUTU@  Rx |  UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  S`(UUTU@  Rx | UU TU UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  S`(UUTU@  Rx | UU TU $ $2 6&,8:<>@4 UUTUUUTUUUTURp @@,+@DH2LPRTX\`dhlpt}  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V ~* U  *~ * ~T x,  UU U *I"$$020 60&0,g8:h<>@4 UUUUUU* UUURp @@,+@ADHLPT  (,.0- t 9UU   6 *~TT~?U U U * ?T ~T x,  UUU U *I"$$020 60&0,g8:h<>@4 UUUUUU* UUURp @@,+@ADHLPT  (,.0- t 9UU   6 *~TT~?U U ~* *T x,  UUU *I"$$020 60&0,g8:h<>@4 UUUUUU* UUURp @@,+@DHLPT  (,.0- 3  TTp    PUPUT ZU  PU  (-/ t 9 UUU  U  I$$ 2 6&,8:i<> @!4 TUUTUUTUU UUURp @@,+@DHLPT  (,.0- 3  TTp    PUPU  ZU  T    PU (-/ t 9 UUU    U I$$ 2 6&,8:i<> @!4 TUUTUUTUU UUURp @@,+@DHLPT  (,.0- 3  TTp    PUPUT UU T PU PU (-/ t 9 UUU  U U I$$ 2 6&,8:i<> @!4 TUUTUUTUU UUURp @@,+@DHLPT  (,.0- 3  TTp    PUPUT UU  PU (-/ t 9 UUU  U I$$ 2 6&,8:i<> @!4 TUUTUUTUU UUURp @@,+@DHLPT  0,p   PUPUPU (,.(-/ t 9 UU 3   TTU V   T   II$0(%20 !60&0,h8:<>@000)%4000 PUPUPU UUUUUU Rp @@,+@DHLPT  0,p   PUPU PU (,.(-/ t 9 UU 3   TT V   U     T  II$0(%20 !60&0,h8:<>@000)%4000 PUPUPU UUUUUU Rp @@,+@DHLPT  0,p   PUPUPU PU (,.(-/ t 9 UU 3   TTUU  U T  T  II$0(%20 !60&0,h8:<>@000)%4000 PUPUPU UUUUUU RVectorEngine35VectorEngine36VectorEngine37VectorEngine38VectorEngine39VectorEngine40VectorEngine41ColorPipe13ColorPipe16DepthPipe9DepthPipe15DepthPipe17DepthPipe18DepthPipe19DepthPipe20DepthPipe21DepthPipe22DepthPipe23DepthPipe27DepthPipe28DepthPipe29DepthPipe30DepthPipe33DepthPipe36DepthPipe37DepthPipe38DepthPipe39DepthPipe45DepthPipe47Memory8Memory9Memory10Memory11Memory12Memory13Memory14Render Metrics BasicHDCAndSF_Slice01HDCAndSF_Slice23HDCAndSF_Slice45HDCAndSF_Slice67L3_Slice01L3_Slice23L3_Slice45L3_Slice67RasterizerAndPixelBackend4RasterizerAndPixelBackend5RenderPipeProfile_Slice0RenderPipeProfile_Slice1RenderPipeProfile_Slice2RenderPipeProfile_Slice3RenderPipeProfile_Slice4RenderPipeProfile_Slice5RenderPipeProfile_Slice6RenderPipeProfile_Slice7Sampler_Slice01Sampler_Slice45Sampler_Slice67bf1e00b6-18c0-409e-8d2c-8105be297da4bbb25709-1345-473f-8233-6df9075eacdafc1c6f5b-60ad-48c8-b0b7-ed9328548c7a39a71cf8-2d00-49f4-b8fb-38da2b23da30d538856d-b249-46ab-b850-9058093d45d67392b735-c76c-4e4d-b936-8ec5fc8877e602d21db0-db5d-4eae-9ffa-8fa1603ec8f276fcf17c-a3ad-474c-a2fb-58a1517c28f4f1e33629-b9d8-4033-a791-2afb70f5bf8d60b56817-8e14-488e-917d-29bffd9fefbbd706dc1e-e6c8-4fe0-b6ed-ea99cdc41673c3d18c22-f267-4f8a-8b4e-b26abd1d16600fa14813-96d3-424b-8935-b70b4e24ea854e741dfb-12e7-4a31-8bed-1d587c0cafc566117e26-8834-4f72-b8f3-162bafb242324b9e649c-1392-4856-abe6-9e67bb06ac5eced7882f-f88d-431c-9dad-8f3016a6477717ba725c-bcfb-444c-8725-fe9bc1a99c5b8c0a8f9b-3e97-4b6d-adb1-fbecb395ec00b7471c18-89e6-4e6d-826c-5f0ca079115436d7c5ca-28e3-41c8-8e2b-f67beba4b23f1bfbb150-1614-49a3-973b-7972bf7c9a91101b4d80-895b-4957-9f24-18456078793af19a51db-ff00-40c0-a13f-1c404e80652e6f269feb-2743-4953-a8b4-7e4b000901bc7b9d22cb-7c4e-4885-be22-833c310e7fd4482c20b4-68c5-4656-8de2-039b2ca8a0f971825303-a777-4079-85e0-69ee3f3caad3b0b33553-4e1c-445d-8e40-c03873ef1d5e08667e1d-ae1b-4370-bc59-2347bb0d7f8db2462b2f-f73f-42d6-9b5e-46cae062d1c115694e7b-c38d-4a65-a355-df93411ed0df84667f81-6441-46d7-844d-e13078a168113ec5f9fe-1567-456a-bb0c-f3b026813bd73ab47029-8b0b-4049-ac68-1ff07d0e7a6e8748eaa5-422c-4597-b4a1-519ccb6f4e9547b237c5-ed48-465b-b869-0d7ef59a69821643fb69-a674-4438-8b44-840e988877bda4b6cfe0-e514-49d2-857c-38f3487ea62a026653d5-37d2-4970-bffd-b1c64dc03deca20872dc-9d91-4ec5-966b-3ae75cb581b77389b9c9-de73-468d-83a8-b27776215e6bMetric set HDCAndSF for Slice01ba8ef361-332f-42f2-9c66-f8531db5e511Metric set HDCAndSF for Slice23a950a603-f683-4f26-a83d-a7ebbe218afbMetric set HDCAndSF for Slice4560f4dc32-a7b6-4301-8d34-be04b1c94e38Metric set HDCAndSF for Slice677666a6f3-801d-4082-ab47-f534b4dad4945357c0dc-c0cb-4ee0-bb6e-2d0882d357a6b0c45d01-03a9-46c2-a04f-2c6a7a5d73d70c42d17c-81b7-4058-9864-65db72b70e2759ce881a-3c51-45e0-96b4-3b565220f3a736b86585-1933-4c0f-9fd0-6dfe61480d8d99a4388a-a104-4bbb-b8b2-7b827644a16bc5db2948-d89c-468c-b52e-f2323a099c92Metric set RasterizerAndPixelBackend3d8d668a7-3468-4ff2-84ab-f285b2468295Metric set RasterizerAndPixelBackend40c4bf00d-3ee4-4804-9f61-5b78f9810d6b0eef4659-956d-4a4e-840c-dca20176165aac9c3eb4-c49e-4297-8126-3d0a78a056f853434b4e-ae6b-457a-b337-c9ebefa86aeb3921cb4b-32f1-4595-b51b-531651d6d89d47924a4a-4cbb-4c9a-a186-efd3af8acf6aee1b4183-c89c-4bad-a11d-b91b60769895a1534029-affd-453e-b8d9-2931505c528826a82035-dadd-4227-a1b4-f7808081f10c71b5ebc0-874f-4ecd-b409-c387a5bb05431fa63cc6-c791-42ae-9db4-4170daefe666c22bbd17-c8bd-4f7e-bb2f-4b045e41f1cb3946ded6-dff6-461a-a9cd-5291d9dcce516ab037fb-065e-4f01-b24e-5f425077189c @@,+ L,L,L,L,L,L,L,L,@$ @@@@  @@@$ @ @$@@@@ @$@   00 UZ UZ OO        Z Z     IIIc>&B,2D8F?H Jp@0pp UUUUUUUUUUUU\ @@,+ L,L,L,L,L,L,L,L,@$ @@@@  @@@$ @ @$@@@@ @$@   00 UZ UZ OO        Z Z     UUUUIIIc>&B,2D8F?H Jp@0pp UUUUUUUUUUUU\ @@,+  L,L,L,L,L,L,L,L,@$ @@@@  @@@$ @ @$@@@@ @$@   00 UZ UZ OO        Z Z     $$$c>&B,2D8F?H Jp@0pp UUUUUUUUUUUU\ @@,+  L,L,L,L,L,L,L,L,@$ @@@@  @@@$ @ @$@@@@ @$@   00 UZ UZ OO        Z Z     $$$c>&B,2D8F?H Jp@0pp UUUUUUUUUUUU\ @@,+  @!    | QU UU     "@! 203@   #  (  @   DP  "    AII>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+  @!   |    "@! 203@   #  (  @   DP   "   AII>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+  @!    | QU UU     "@! 203@   #  (  @   DP  "    QUUUAII>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+  @!   |    "@! 203@   #  (  @   DP   "   QUUUAII>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+   @!    | QU UU     "@! 203@   #  (  @   DP  "    $$$>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+   @!   |    "@! 203@   #  (  @   DP   "   $$$>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+   @!    | QU UU     "@! 203@   #  (  @   DP  "    $$$>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+   @!   |    "@! 203@   #  (  @   DP   "   $$$>, B2D8FaH" J@ QUUUQUUUQUUU\ @@,+ &&@ 8 1 &&@ 8 @1   &&@ 81 &&@  8 @1  >@)I$J (>& B,2AD8FH!J@@ \0 @@,+@8DHLPTX\``dhl p`p ` p `  ?@U @ * 5><  `     p`p ` p ` ?7@@ U ?     @0 @ U     0   UjIIIf >&B,2D8F`H J @pp U@U@U@* @U@U@U*\0 @@,+@8DHLPTX\``dhl `p ` p ` p5>(` U) @    `    @@ `p ` p ` p@   @00 @ U L    0    7@ UjIII0>0&!B0,02 D08bFHhJ000B@0 U@U@U@* @U@U@U*\0 @@,+@8DHLPTX\``dhl  p`p ` p `  ?@U @ * 5><  `      p`p ` p ` ?7@@ U ?     @0 @ U     0   $$$f >&B,2D8F`H J @pp U@U@U@* @U@U@U*\0 @@,+@8DHLPTX\``dhl  `p ` p ` p5>(` U) @    `    @@  `p ` p ` p@   @00 @ U L    0    7@ $$$0>0&!B0,02 D08bFHhJ000B@0 U@U@U@* @U@U@U*\ @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg III$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg UUUUIII$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg $$$$>&B,2@D8FHJ*@ \ @@,+  + K k  , L l     +++KKKKkkk k    ,,,LLLLlll l00HHU U HHgg $$$$>&B,2@D8FHJ*@ \ @@,+@DHLPTX\`dhlptx|  dd     ddP  @@ dd      dd@P   @@ p p! pA pa p p p p !!!AAAaaaIH$I8   $  '  0>&$$B0,2D08`FH J@   PPP 0  PPP\ @@,+@DHLPTX\`dhlptx| @  @ @@ @    @@ @@` U   `    @ IIp >p& B0,p2GD8FH UUUUUU\ @@,+@DHLPTX\`dhlptx| @  @ @@ @    @@ @@` U   `    @ UUIIp >p& B0,p2GD8FH UUUUUU\ @@,+@DHLPTX\`dhlptx|  @  @ @@ @    @@ @@` U   `    @ $p >p& B0,p2GD8FH UUUUUU\ @@,+@DHLPTX\`dhlptx|  @  @ @@ @    @@ @@` U   `    @ $p >p& B0,p2GD8FHUUUUUU\ @@,+@DHLPTX\`dhlptx| .4$HJ\XPX0 @@,+@DHL $ B"    @@@$ $ B"    $@$$$$ $( 2<&   $UDUh$m+$0>0&B0,02D08FHb J00@000 \X X@X1X" \B  @@,+XXPXX\a \@\ @@,+XPXX 0X \`\ @@,+XPX0XX\Q  @@,+  (@ 7 PP FHPPP\ @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Qt2 6&,8:<>@4(U33UU  U "" ? 3   ; < =>UUUUU   UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  33II"Q(2 6&,8:<> @p@4p(? 3  ; < =>UUUUU   UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@ 4 X  33UU  U, 8          UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4X  U33UU  U "" 33UU  U, 8           UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@ 4 X  33UU  U, 8          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@4 X  ""U "" U, 8          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$|2 6&,8:<>@4 X  U33UU  U "" 33UU  U, 8           UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@@4 X  U33UU  U "" ""U  "" U, 8           UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@@4X  33UU  U, 8          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4X  ""U "" U, 8          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4X  U33UU  U "" 33UU  U, 8           UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  ""$$$|2 6&,8:<>@4 D  U33UU  U "" 33UU  U, <           UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@@4 D  U33UU  U "" ""U  "" U, <           UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@@4D  33UU  U, <          UUUUUUU""R @@,+@ DH"LPBTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4D  ""U "" U, <          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@ 4 D  33UU  U, <          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  ""$$$2 6&,8:<>@@4 D  U33UU  U "" ""U  "" U, <           UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@@4D  33UU  U, <          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4D  ""U "" U, <          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4D  U33UU  U "" 33UU  U, <           UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@@4`  33UU  U, 8          UUUUUUU""R @@,+@DH2LPRTX\`dhlpt}x|  .0  33II"Q2 6&,8:<>@4`  U33UU  U "" 33UU  U, 8           UUUUUUU""R @@,+@D 8aaaaHaa La aaUUUU$2 6&,8:<>R @@,+@D 8H L UUII  2 6&,8:<>R @@,+@D 8H L UUII  2 6&,8:<>R0 @@,+@DHL @%A8aa(AAA A A AAaaa aaaaUUUUUUUU$$$2 6&,8:<>@4R0 @@,+@DHL 8AA@%aAAA AAAA(aaa a a aaUUUUUUUU$$$2 6&,8:<>@4R0 @@,+@DHL @%8(    UUUUIII 2 6&,8:<>@4R0 @@,+@DHL 8@% (   UUUUIII 2 6&,8:<>@4RXEXA X X @@,+X Xb XB X \  @@,+X`XXX \ \ @@,+XP XePX%P XUP \P  @@,+X X X X\ @@,+XX0X` X\1\a  @@,+XPXXX\ @@,+TDL_Slice01_1TDL_Slice01_2TDL_Slice01_3TDL_Slice01_4TDL_Slice23_1TDL_Slice23_2TDL_Slice23_3TDL_Slice23_4TDL_Slice45_1TDL_Slice45_2TDL_Slice45_3TDL_Slice45_4TDL_Slice67_1TDL_Slice67_2TDL_Slice67_3TDL_Slice67_4f0294ed6-827a-44e0-9f79-1ddc2218289914477b8c-ad25-4351-8c67-e6411cb77bab6b48996e-1179-4955-bd28-d5aefeea11966403c3b2-e302-4c1a-a604-7817e846ab2c51d2c1bd-7432-411f-9095-ac97d55dc28532e32945-471f-4f17-bae1-9d96f9c54f8d34804b9e-0d2b-4e97-ba78-5c2069bc9df997ca0de0-9d3b-4bdd-94f7-662113dfc905f4ba49b6-37a1-4848-88d6-3c63cb8e1c12a6969313-fe82-4f0b-9499-b90c98e9ede78dd20826-657e-43b7-9bba-a48ef4db2d14e479a02f-fc83-438f-818d-3e11e769fbaedeb1e6dd-bddd-42a4-87f5-c4bd8438a8840a6abc27-343e-4118-b17e-5c5121611b0867abb260-55fb-4c66-8469-db2f8700884a7c064e0d-b3ee-4159-9361-8d1da3158d395ae9db29-303b-4e74-8dc8-b9f2eb31aaa116047ddf-5ee1-4948-81dc-edbe26576ac1224881aa-faa7-4d2d-8161-50dbb10026e8dc5ee653-2006-48de-8be2-e8b760a4369c41302bd4-41dd-4c52-b250-569324d62f1aa0369d50-1c37-4bf4-97a9-169c92b63483ff386ef9-604c-48a5-9fc9-e2281bbd7463c027d083-6448-4ec1-9415-8a1ff807562c57e2e261-2715-4b63-baec-527eba9e06cb9e92a393-69c4-46fd-b038-e6183364d8c5e8621f59-b8d2-4e00-86a9-472e3848973d12eee9d0-7d4a-495c-a3b5-7d8ab1b0fe0259c0b126-b2dc-4a97-818e-741e6355059c9da5cb85-6e23-4896-8d99-1b8a87dd89304cd5fd6b-e82a-44fc-a068-4debac13114f29eade65-5f7c-4b51-8006-66852e9f2181859c2807-55de-47e0-aa30-320c23c9373dc9c488d0-950c-4a0a-a079-b299cd33aa6b4599426b-4cfa-442a-8a59-9eda3dd742db42107330-c266-42b4-aef5-5c2ab410edc4a0add3fe-f028-4e6c-b104-c369fabe2b094aeacf49-91c2-41bf-8d9f-49233689e36a60e3a9fa-b807-4a8d-8a83-88705d05e2c90aab7745-1e24-42af-9c96-c640e4f45aa997670487-9837-4cd2-9475-dea1d28d34fc2908914a-a836-44ec-a053-36a7ed38346234f121ae-5907-4fe2-a237-a36940510708f3893d2b-10f8-48f6-8417-6ed748d3dccd6b5ae61c-ceab-4202-b550-8430b037566c66bbd7d1-f6a2-4189-99f7-8e360e28be45b8a9f40b-5906-46b2-ad95-8d36eb9cf998e5d242d2-5bf6-4380-8f7c-cb0ff2372733b6096e7e-a2c9-4622-9bd6-2169cdebc490c7b9f883-12c5-470c-ab75-790961e66be678161cec-30c8-4b7f-aab8-6f13139f454ee9ba5301-d2ca-4978-af6e-19096ad16dbbcae0eb96-c3e6-4a3a-83e2-e939146602b5002950f1-a311-45f9-b88e-2276f42d8f9298b27683-8d7c-4b3e-92d9-3c3683b2cc3857d03ea4-1959-4b4f-8a32-abaa96246b1d @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l   ++KKKkk k   ,,LLLll l0HU Hg  + K k  , L l  ++ +KKKkkk  ,, ,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l   ++KKKkk k   ,,LLLll l0HU Hg  + K k  , L l  ++ +KKKkkk  ,, ,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l    +++KKKkk k @  ,@,,L@LLl@l l0HU Hg  + K k  @, L l   ++KKKkkk @ ,,L@LLl@ll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k  , L l    +++KKKkk k @  ,@,,L@LLl@l l0HU Hg  + K k  @, L l   ++KKKkkk @ ,,L@LLl@ll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+  ` `+ `K `k ` `, `L `l    +++KKKkk k @  ,@,,L@LLl@l l0HU Hg ` `+ `K `k ` @a, `L `l   ++KKKkkk @ ,,L@LLl@ll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+ ` `+ `K `k ` `, `L `l    +++KKKkk k @  ,@,,L@LLl@l l0HU Hg ` `+ `K `k ` @a, `L `l   ++KKKkkk @ ,,L@LLl@ll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+@8DHLPT?Xp\`d   + K , L  B   +B+ + +KBKKK,,,LL LL?T*T 8j*8 *III>&B,2!D8FH J!@\ @@,+@8DHLPT?Xp\`d  K k L l KKKkk kkLBLLLlBl l ljUUU   B   pp UUU*III>&B,2!D8FHJ!@\ @@,+@8DHLPT?Xp\`d  k kBkkk?*  +  ,  B +B+++   ,, ,,@8@V?8 ?@UUII>&B,2D8 F`HJ)%@\ @@,+@8DHLPT?Xp\`d  + K , L l +++KK KK,B,,,LBL L LlBlllP*V*PU*կ* ?$$$!>& B,2JD8 FHJ@\ @@,+@8DHLPT?Xp\`d K k l KBKKKkBk k klll? UU    B       *TT* ?$$$!>& B,2D8F@HJ@\ @@,+@8DHLPT?Xp\`d  +  , L    ++ ++ B   ,B, , ,LBLLL* Z* *$$$A)>& B,2D8FHJ@\ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k , L l    +++KKKkk k   ,,,LLLll l0HU Hg + K k , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l    +++KKKkk k   ,,,LLLll l0HU Hg  + K k  , L l   ++KKKkkk  ,,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k  , L l    +++KKKkk k   ,,,LLLll l0HU Hg  + K k  , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l    +++KKKkk k   ,,,LLLll l0HU Hg  + K k  , L l   ++KKKkkk  ,,LLLlll0HU Hg UUIII$>&B,2@D8FHJ*@ \ @@,+  + K k  , L l    +++KKKkk k   ,,,LLLll l0HU Hg  + K k  , L l   ++KKKkkk  ,,LLLlll0HU Hg $$$$>&B,2@D8FHJ*@ \ @@,+   + K k  , L l @  +@++K@K Kk@k k   ,,,LL Lll l !U!٪  +@ K k  , L l @ +@++KKk@kk  ,,,LLlll !U!٪ UUIII!(>&B,2 D8F@HJ @ \ @@,+   +@ K k  , L l @ +@++KKk@kk  ,,,LLlll !U!٪  + K k  , L l @  +@++K@K Kk@k k   ,,,LL Lll l !U!٪ $$$!(>&B,2 D8F@HJ @ \ @@,+ N@@!@!@A@A@a@a@@@@@@@@!! !!AA AAaa aa $I$I$I 8  I"  $  @ S '  B>&@B,2D8FHJ@ \ @@,+   " B b    @@!""" ABB Babb b  $I$I$I 8  I"  $  @ S '  B>&@B,2D8FHJ@ \ @@,+ QQ"QBQbQQQQ0!" " AB Babb0 $I$I$I& J I I$ $  H   >&@B,2BD8FHJ@ \ @@,+ "Bb0!" " AB Babb0 $I$I$I& J I I$ $  H   >&@B,2BD8FHJ@ \ @@,+ 88!8A8a8888!! @!!AA AAaa @aa @@$I$I$I 8  I"  $  @ S '  B>&@B,2D8FHJ@ \ @@,+ 8@8!@!8A@A8a@a8@8@8@8@ !! !!AA AAaa aa    $I$I$I& J I I$ $  H   >&@B,2BD8FHJ@ \XPX@@ ,+  $  >&B\  @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U     @@@ ` U UU / @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U   (  @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U      @ @@  ` U UU /  @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U   )  @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U     @@@ ` U UU / @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U   (  @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U      @ @@  ` U UU /  @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U   ) @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U     @@@ ` U UU / @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  ( @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U      @ @@  ` U UU /  @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  ) @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U     @@@ ` U UU / @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  ( @@@@@ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U      @ @@  ` U UU /  @ P, U&k(`*V, .k-"PV$P, U&k(`*V, .k-"PV$ ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P ,P k-P` @j" $Pk-Pk-P @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U @ @ , , kU kU k- k- ! " #U $U %k &k 'V V U U  )  + K k 0 , L l  !! "$(    +++KKKkk k2     ,,,LLLll l0HU UUHUUg  &!(!*,.("$ &!(!*,.("$  !! "$(  !! "$(  !! "$(    ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '    &  + K k 0 , L l  !! "$(    +++KKKkk k2     ,,,LLLll l0HU UUHUUg  &!(!*,.("$ &!(!*,.("$ !! "$(  !! "$(  !! "$(    ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '     &  + K k 0 , L l  !! "$(    +++KKKkk k2     ,,,LLLll l0HU UUHUUg  &!(!*,.("$ &!(!*,.("$ !! "$(  !! "$(  !! "$(    ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '     &  + K k 0 , L l  !! "$(    +++KKKkk k2     ,,,LLLll l0HU UUHUUg  &!(!*,.("$ &!(!*,.("$ !! "$(  !! "$(  !! "$(    ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '        ' ' ! ! ! " # $ % & '     &XPX " ? $( ,048<?@@ ,+ @ @     @ B\  V    J J @) @) ! " #Q $Q % & '      2  02 PPPP2 02V  PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '        (  V    J J @) @) ! " #Q $Q % & '      2    02  PPPP2   02V   PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '        )  V    J J @) @) ! " #Q $Q % & '      2  02 PPPP2 02V  PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '        (  V    J J @) @) ! " #Q $Q % & '      2    02  PPPP2   02V   PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '        ) V    J J @) @) ! " #Q $Q % & '      2  02 PPPP2 02V  PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '       ( V    J J @) @) ! " #Q $Q % & '      2    02  PPPP2   02V   PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '       ) V    J J @) @) ! " #Q $Q % & '      2  02 PPPP2 02V  PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '       ( V    J J @) @) ! " #Q $Q % & '      2    02  PPPP2   02V   PPPPZZ U U  P P 0   &J( *@,.c"$ &J( *@,.c"$ @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)  @)@  @"$c@)    J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '          J J @) @) ! " #Q $Q % & '       )& & & &XPX @@,+2 R $(,04}  `    c c  ! " # $ %` &` '      UUTUT  UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  `    c c  ! " # $ %` &` '      UUTUT   UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        )  `    c c  ! " # $ %` &` '      UUTUT  UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  `    c c  ! " # $ %` &` '      UUTUT   UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        ) `    c c  ! " # $ %` &` '      UUTUT  UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( `    c c  ! " # $ %` &` '      UUTUT   UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ) `    c c  ! " # $ %` &` '      UUTUT  UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( `    c c  ! " # $ %` &` '      UUTUT   UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       )& & & &XPX @@,+2 R $(,04}  `    c c  ! " # $ %` &` '      UUTUT  UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  `    c c  ! " # $ %` &` '      UUTUT   UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        )  `    c c  ! " # $ %` &` '      UUTUT  UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  `    c c  ! " # $ %` &` '      UUTUT   UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        ) `    c c  ! " # $ %` &` '      UUTUT  UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( `    c c  ! " # $ %` &` '      UUTUT   UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ) `    c c  ! " # $ %` &` '      UUTUT  UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( `    c c  ! " # $ %` &` '      UUTUT   UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       )& & & &XPX @@,+  "$(       ! " # $ % & '    UUUUT21 ! UUUU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      (  #%)       ! " # $ % & '    UUUUT21  ! UUUU    &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      )  "$(       ! " # $ % & '    UUUUT21 ! UUUU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      (  #%)       ! " # $ % & '    UUUUT21  ! UUUU    &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      ) "$(       ! " # $ % & '    UUUUT21 ! UUUU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ( #%)       ! " # $ % & '    UUUUT21  ! UUUU    &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ) "$(       ! " # $ % & '    UUUUT21 ! UUUU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ( #%)       ! " # $ % & '    UUUUT21  ! UUUU    &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     )& & & &XPX @@,+  "$(       ! " # $ % & '    UUUUT21 ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      (  #%)       ! " # $ % & '    UUUUT21  ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      )  "$(       ! " # $ % & '    UUUUT21 ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      (  #%)       ! " # $ % & '    UUUUT21  ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '      ) "$(       ! " # $ % & '    UUUUT21 ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ( #%)       ! " # $ % & '    UUUUT21  ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ) "$(       ! " # $ % & '    UUUUT21 ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     ( #%)       ! " # $ % & '    UUUUT21  ! UU UU  &(*,."$ &(*,."$  "$   "$   "$   "$       ! " # $ % & '           ! " # $ % & '           ! " # $ % & '     )& & & &XPX @@,+2 R $(,04}  S`    c c  ! " # $ %` &` '      UUTU@BTH L UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  S`    c c  ! " # $ %` &` '      UUTU@BTH  L UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        )  S`    c c  ! " # $ %` &` '      UUTU@BTH L UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  S`    c c  ! " # $ %` &` '      UUTU@BTH  L UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        ) S`    c c  ! " # $ %` &` '      UUTU@BTH L UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( S`    c c  ! " # $ %` &` '      UUTU@BTH  L UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ) S`    c c  ! " # $ %` &` '      UUTU@BTH L UUTU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( S`    c c  ! " # $ %` &` '      UUTU@BTH  L UUTU    &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       )& & & &XPX @@,+2 R $(,04}  S`    c c  ! " # $ %` &` '      UUTU@BTH L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  S`    c c  ! " # $ %` &` '      UUTU@BTH  L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        )  S`    c c  ! " # $ %` &` '      UUTU@BTH L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        (  S`    c c  ! " # $ %` &` '      UUTU@BTH  L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '        ) S`    c c  ! " # $ %` &` '      UUTU@BTH L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( S`    c c  ! " # $ %` &` '      UUTU@BTH  L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ) S`    c c  ! " # $ %` &` '      UUTU@BTH L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       ( S`    c c  ! " # $ %` &` '      UUTU@BTH  L UU TU  &(*,.c " $ &(*,.c " $  "$c c    "$c c    "$c c    "$c c     c c  ! " # $ %` &` '          c c  ! " # $ %` &` '          c c  ! " # $ %` &` '       )& & & &XPXXX\ @@,+ ( ) ( ) ( ) ( ) `  `+ + `K K `k k ` @ @a, , `L L `l l  * "$( 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg  &(**,.("$ &(**,.("$  * "$(  * "$(  * "$(    ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '    &  `  `+ + `K K `k k ` @ @a, , `L L `l l  * "$( 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg  &(**,.("$ &(**,.("$ * "$(  * "$(  * "$(    ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '     &  `  `+ + `K K `k k ` @ @a, , `L L `l l  * "$( 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg  &(**,.("$ &(**,.("$ * "$(  * "$(  * "$(    ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '     &  `  `+ + `K K `k k ` @ @a, , `L L `l l  * "$( 2   2+ ++2KK KK2kk k k2 @  2,@,,2L@L@LL2l@l@l l00HHU U HHgg  &(**,.("$ &(**,.("$ * "$(  * "$(  * "$(    ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '        ' '  !( "( # $ % & '     & @@,+@DHxLPTXx\ ++++ r  UU r  UU r  UU 3 UUUU UU  U  UU U U IIIj >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHxLPTXx\ **** r UU r UU r UU 3 UUU UU U U IIIj >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHLPTX\?`dhlptx|? @(@(@(@(@)@)@)@)1  1  PP1  01 PP1   1   PP1   01  PPZ U UU  P 0 Z U  P 0 IIIpj >p&JBp,p2 D08FwH"J(@ UUUUUUUUUUUU\ @@,+@DHLPTX\`dhlptx| ****++++0 0   r @U@U0   0  @  r  @U@U`U U U   `U     @ IIIpJ)>p& B0,p2GD8FH Jp@ppp UUUUUUUUUUUU\ @@,+@DHxLPTXx\ ++++ r  UU r  UU r  UU 3 UUUU UU  U  UU U U UUUUIIIj >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHxLPTXx\ **** r UU r UU r UU 3 UUU UU U U UUUUIIIj >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHLPTX\?`dhlptx|? @(@(@(@(@)@)@)@)1  1  PP1  01 PP1   1   PP1   01  PPZ U UU  P 0 Z U  P 0 UUUUIIIpj >p&JBp,p2 D08FwH"J(@ UUUUUUUUUUUU\ @@,+@DHLPTX\`dhlptx| ****++++0 0   r @U@U0   0  @  r  @U@U`U U U   `U     @ UUUUIIIpJ)>p& B0,p2GD8FH Jp@ppp UUUUUUUUUUUU\ @@,+@DHxLPTXx\  ++++ r  UU r  UU r  UU 3 UUUU UU  U  UU U U $$$j >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHxLPTXx\  **** r UU r UU r UU 3 UUU UU U U $$$j >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHLPTX\?`dhlptx|?  @(@(@(@(@)@)@)@)1  1  PP1  01 PP1   1   PP1   01  PPZ U UU  P 0 Z U  P 0 $$$pj >p&JBp,p2 D08FwH"J(@ UUUUUUUUUUUU\ @@,+@DHLPTX\`dhlptx|  ****++++0 0   r @U@U0   0  @  r  @U@U`U U U   `U     @ $$$pJ)>p& B0,p2GD8FH Jp@ppp UUUUUUUUUUUU\ @@,+@DHxLPTXx\  ++++ r  UU r  UU r  UU 3 UUUU UU  U  UU U U $$$j >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHxLPTXx\  **** r UU r UU r UU 3 UUU UU U U $$$j >&B)B,2 D8FHJB@ UUUUUUUUUUUU\ @@,+@DHLPTX\?`dhlptx|?  @(@(@(@(@)@)@)@)1  1  PP1  01 PP1   1   PP1   01  PPZ U UU  P 0 Z U  P 0 $$$pj >p&JBp,p2 D08FwH"J(@ UUUUUUUUUUUU\ @@,+@DHLPTX\`dhlptx|  ****++++0 0   r @U@U0   0  @  r  @U@U`U U U   `U     @ $$$pJ)>p& B0,p2GD8FH Jp@ppp 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Data has been dropped. Increase setting with INTEL_MEASURE=buffer_size={count} INTEL_MEASURE failed to open output file %s: %s INTEL_MEASURE start frame may not be negative: %d INTEL_MEASURE count frame must be positive: %d INTEL_MEASURE failed to create control fifo %s: %s INTEL_MEASURE failed to open control fifo %s: %s INTEL_MEASURE event_interval must be positive: %d INTEL_MEASURE minimum batch_size is 1k: %d INTEL_MEASURE batch_size limited to 4M: %d INTEL_MEASURE minimum buffer_size is 1k: %d INTEL_MEASURE buffer_size limited to 1M: %d draw_start,draw_end,frame,batch,batch_size,renderpass,event_index,event_count,type,count,vs,tcs,tes,gs,fs,cs,ms,ts,idle_us,time_us draw_start,frame,batch,batch_size,event_index,event_count,type,count %lu,%lu,%u,%u,%lu,%u,%u,%u,%s,%u,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,%.3lf,%.3lf 78925a28-3e52-4d74-b03b-cb27c6a4401a1e91d8d9-ced4-4240-bf9e-fdd7d015c058da34c79f-d1c6-4d15-b848-2085528bb86b33ceab81-26bc-49f3-a124-5dbb2d592a87d8b7d2f7-7c3a-4a68-b6c1-48d197b2294501d6bd34-b8d1-4412-b53b-0d16b327abec7485f9ec-ac5f-4c6d-8c5f-6a023e7d29d5944dc12b-b2fd-4bf5-a59d-540e2b280cdd5c97330a-b407-4ef8-908f-7fdeec216f8165e4ac2a-db8f-4918-bdd6-ac4d85de160e0eb11775-ad71-44d4-ad2c-c2fa6431b144d7736d53-f1cb-4899-8f3d-d8aaad1f1c67496219cc-316b-4945-9fc4-180e60331262c7e6721e-51f9-40af-ba8b-0520a10828550e9b064c-9fa7-4e85-8aaa-cc871010117d44d73f02-f843-4717-a3d5-3d1dfbd3f106b84f370e-1b64-41d1-a4d8-f095fb79e5f8772a2c24-0a03-480e-baca-72f2f55a5422953d3bf8-af3d-4287-ac22-dcd122c5eb51dbb009c2-98ad-4af0-905a-e7808ac5424c16fd8981-676d-4cbc-b010-8d731ba66a067bcdd766-98a5-461a-ac8e-d8c6489583641625df84-2f24-4aed-9ced-e652184c9949d86c1224-3af7-4df1-a44d-e4522f22b2ae03090380-689d-481a-ace2-9725ea0c10d2db4a27f8-40a0-4cb5-aa3a-5368add92cd56b5736f5-a627-4cb6-9078-1c05137bc4605e6f4959-c37c-4be0-bb4e-2f1c1aef2bb3fe2d673e-8b2e-47d0-b9db-2c50e10ee53e5ba2bf20-ca4e-4872-86fd-9026c9de8c93fe8810c2-457b-47e0-a3b9-50cab24718b4bf950c5b-7250-47f4-aa59-d97b22db02ff9027ff05-4348-4061-a434-0befaba7c3793b94a07f-e4d8-4cf2-969e-ea19bb253a8cf4399df4-e808-4a0a-85ff-0c66f9c9e8a403eb9c9b-72ee-4c7b-930b-6211dbb60503c3586bbc-f20b-4ffc-bd62-21ea68c161f4pack_uint_32_to_r10g10b10a2_v3dunpack_half_2x16_flush_to_zerounpack_half_2x16_split_x_flush_to_zerounpack_half_2x16_split_y_flush_to_zeroHXh88hhH`#(08LDLD | l \ L < ,   |l\L<, |l\L<,    |l\L<,  |l\L<,  4#D#D#D#$###D#D#D#D#D#D#D#D#D#D#D#D#D#D#D#D#D#D#D#"D#""D#D#D#D#D#D#D#D#D#"D#D#D#D#D#D#D#D#$$D#D#D#D#"D#D#D#"D#D#"D#"t"D#D#d"D#T"D#D#D#D#D#D#D#D#D#D#D#D"D#4"D#$"D#D#D#D#"D#D#D#D#D#D#D#D#D#4$D#D#"!D#!D#D#D#D#!D#!!D#D#D#D#D#!D#D#!D#D#!D#D#D#D#t!D#D#D#D#D#D#d!D#D#D#D#D#D#T!D#D#D#D#D#D#D#D#D#D#D#D!4!$!D#D#D#!! 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(%+li%+d%s#%u0x%08lxsystempush_constimageshader_tempfunction_tempgenericshader_call_dataray_hit_attribnode_payloadnode_payload_in~0%s%scoherentvolatilerestrictreadonlywriteonlyreorderablespeculatablenon-temporalinclude-helpersVERT_ATTRIB_POSVERT_ATTRIB_NORMALVERT_ATTRIB_COLOR0VERT_ATTRIB_COLOR1VERT_ATTRIB_FOGVERT_ATTRIB_COLOR_INDEXVERT_ATTRIB_TEX0VERT_ATTRIB_TEX1VERT_ATTRIB_TEX2VERT_ATTRIB_TEX3VERT_ATTRIB_TEX4VERT_ATTRIB_TEX5VERT_ATTRIB_TEX6VERT_ATTRIB_TEX7VERT_ATTRIB_POINT_SIZEVERT_ATTRIB_GENERIC0VERT_ATTRIB_GENERIC1VERT_ATTRIB_GENERIC2VERT_ATTRIB_GENERIC3VERT_ATTRIB_GENERIC4VERT_ATTRIB_GENERIC5VERT_ATTRIB_GENERIC6VERT_ATTRIB_GENERIC7VERT_ATTRIB_GENERIC8VERT_ATTRIB_GENERIC9VERT_ATTRIB_GENERIC10VERT_ATTRIB_GENERIC11VERT_ATTRIB_GENERIC12VERT_ATTRIB_GENERIC13VERT_ATTRIB_GENERIC14VERT_ATTRIB_GENERIC15VERT_ATTRIB_EDGEFLAGVARYING_SLOT_POSVARYING_SLOT_COL0VARYING_SLOT_COL1VARYING_SLOT_FOGCVARYING_SLOT_TEX0VARYING_SLOT_TEX1VARYING_SLOT_TEX2VARYING_SLOT_TEX3VARYING_SLOT_TEX4VARYING_SLOT_TEX5VARYING_SLOT_TEX6VARYING_SLOT_TEX7VARYING_SLOT_PSIZVARYING_SLOT_BFC0VARYING_SLOT_BFC1VARYING_SLOT_EDGEVARYING_SLOT_CLIP_VERTEXVARYING_SLOT_CLIP_DIST0VARYING_SLOT_CLIP_DIST1VARYING_SLOT_CULL_DIST0VARYING_SLOT_CULL_DIST1VARYING_SLOT_PRIMITIVE_IDVARYING_SLOT_LAYERVARYING_SLOT_VIEWPORTVARYING_SLOT_FACEVARYING_SLOT_TESS_LEVEL_OUTERVARYING_SLOT_TESS_LEVEL_INNERVARYING_SLOT_BOUNDING_BOX0VARYING_SLOT_BOUNDING_BOX1VARYING_SLOT_VIEW_INDEXVARYING_SLOT_VIEWPORT_MASKVARYING_SLOT_VAR0VARYING_SLOT_VAR1VARYING_SLOT_VAR2VARYING_SLOT_VAR3VARYING_SLOT_VAR4VARYING_SLOT_VAR5VARYING_SLOT_VAR6VARYING_SLOT_VAR7VARYING_SLOT_VAR8VARYING_SLOT_VAR9VARYING_SLOT_VAR10VARYING_SLOT_VAR11VARYING_SLOT_VAR12VARYING_SLOT_VAR13VARYING_SLOT_VAR14VARYING_SLOT_VAR15VARYING_SLOT_VAR16VARYING_SLOT_VAR17VARYING_SLOT_VAR18VARYING_SLOT_VAR19VARYING_SLOT_VAR20VARYING_SLOT_VAR21VARYING_SLOT_VAR22VARYING_SLOT_VAR23VARYING_SLOT_VAR24VARYING_SLOT_VAR25VARYING_SLOT_VAR26VARYING_SLOT_VAR27VARYING_SLOT_VAR28VARYING_SLOT_VAR29VARYING_SLOT_VAR30VARYING_SLOT_VAR31VARYING_SLOT_PATCH0VARYING_SLOT_PATCH1VARYING_SLOT_PATCH2VARYING_SLOT_PATCH3VARYING_SLOT_PATCH4VARYING_SLOT_PATCH5VARYING_SLOT_PATCH6VARYING_SLOT_PATCH7VARYING_SLOT_PATCH8VARYING_SLOT_PATCH9VARYING_SLOT_PATCH10VARYING_SLOT_PATCH11VARYING_SLOT_PATCH12VARYING_SLOT_PATCH13VARYING_SLOT_PATCH14VARYING_SLOT_PATCH15VARYING_SLOT_PATCH16VARYING_SLOT_PATCH17VARYING_SLOT_PATCH18VARYING_SLOT_PATCH19VARYING_SLOT_PATCH20VARYING_SLOT_PATCH21VARYING_SLOT_PATCH22VARYING_SLOT_PATCH23VARYING_SLOT_PATCH24VARYING_SLOT_PATCH25VARYING_SLOT_PATCH26VARYING_SLOT_PATCH27VARYING_SLOT_PATCH28VARYING_SLOT_PATCH29VARYING_SLOT_PATCH30VARYING_SLOT_PATCH31VARYING_SLOT_VAR0_16BITVARYING_SLOT_VAR1_16BITVARYING_SLOT_VAR2_16BITVARYING_SLOT_VAR3_16BITVARYING_SLOT_VAR4_16BITVARYING_SLOT_VAR5_16BITVARYING_SLOT_VAR6_16BITVARYING_SLOT_VAR7_16BITVARYING_SLOT_VAR8_16BITVARYING_SLOT_VAR9_16BITVARYING_SLOT_VAR10_16BITVARYING_SLOT_VAR11_16BITVARYING_SLOT_VAR12_16BITVARYING_SLOT_VAR13_16BITVARYING_SLOT_VAR14_16BITVARYING_SLOT_VAR15_16BITFRAG_RESULT_DEPTHFRAG_RESULT_STENCILFRAG_RESULT_COLORFRAG_RESULT_SAMPLE_MASKFRAG_RESULT_DATA0FRAG_RESULT_DATA1FRAG_RESULT_DATA2FRAG_RESULT_DATA3FRAG_RESULT_DATA4FRAG_RESULT_DATA5FRAG_RESULT_DATA6FRAG_RESULT_DATA7SYSTEM_VALUE_SUBGROUP_SIZESYSTEM_VALUE_SUBGROUP_EQ_MASKSYSTEM_VALUE_SUBGROUP_GE_MASKSYSTEM_VALUE_SUBGROUP_GT_MASKSYSTEM_VALUE_SUBGROUP_LE_MASKSYSTEM_VALUE_SUBGROUP_LT_MASKSYSTEM_VALUE_NUM_SUBGROUPSSYSTEM_VALUE_SUBGROUP_IDSYSTEM_VALUE_VERTEX_IDSYSTEM_VALUE_INSTANCE_IDSYSTEM_VALUE_INSTANCE_INDEXSYSTEM_VALUE_BASE_VERTEXSYSTEM_VALUE_FIRST_VERTEXSYSTEM_VALUE_IS_INDEXED_DRAWSYSTEM_VALUE_BASE_INSTANCESYSTEM_VALUE_DRAW_IDSYSTEM_VALUE_INVOCATION_IDSYSTEM_VALUE_FRAG_COORDSYSTEM_VALUE_POINT_COORDSYSTEM_VALUE_LINE_COORDSYSTEM_VALUE_FRONT_FACESYSTEM_VALUE_SAMPLE_IDSYSTEM_VALUE_SAMPLE_POSSYSTEM_VALUE_SAMPLE_MASK_INSYSTEM_VALUE_LAYER_IDSYSTEM_VALUE_COLOR0SYSTEM_VALUE_COLOR1SYSTEM_VALUE_TESS_COORDSYSTEM_VALUE_VERTICES_INSYSTEM_VALUE_PRIMITIVE_IDSYSTEM_VALUE_TESS_LEVEL_OUTERSYSTEM_VALUE_TESS_LEVEL_INNERSYSTEM_VALUE_WORKGROUP_IDSYSTEM_VALUE_NUM_WORKGROUPSSYSTEM_VALUE_WORKGROUP_SIZESYSTEM_VALUE_WORK_DIMSYSTEM_VALUE_USER_DATA_AMDSYSTEM_VALUE_DEVICE_INDEXSYSTEM_VALUE_VIEW_INDEXSYSTEM_VALUE_VERTEX_CNTSYSTEM_VALUE_RAY_LAUNCH_IDSYSTEM_VALUE_RAY_LAUNCH_SIZESYSTEM_VALUE_RAY_WORLD_ORIGINSYSTEM_VALUE_RAY_T_MINSYSTEM_VALUE_RAY_T_MAXSYSTEM_VALUE_RAY_HIT_KINDSYSTEM_VALUE_RAY_FLAGSSYSTEM_VALUE_CULL_MASKSYSTEM_VALUE_MESH_VIEW_COUNTSYSTEM_VALUE_GS_HEADER_IR3SYSTEM_VALUE_TCS_HEADER_IR3SYSTEM_VALUE_REL_PATCH_ID_IR3SYSTEM_VALUE_FULLY_COVEREDSYSTEM_VALUE_FRAG_SIZESYSTEM_VALUE_SHADER_INDEXSYSTEM_VALUE_WARPS_PER_SM_NVSYSTEM_VALUE_SM_COUNT_NVSYSTEM_VALUE_WARP_ID_NVSYSTEM_VALUE_SM_ID_NVVARYING_SLOT_PRIMITIVE_SHADING_RATESYSTEM_VALUE_SUBGROUP_INVOCATIONSYSTEM_VALUE_VERTEX_ID_ZERO_BASESYSTEM_VALUE_HELPER_INVOCATIONSYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULTSYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULTSYSTEM_VALUE_LOCAL_INVOCATION_IDSYSTEM_VALUE_LOCAL_INVOCATION_INDEXSYSTEM_VALUE_GLOBAL_INVOCATION_IDSYSTEM_VALUE_BASE_GLOBAL_INVOCATION_IDSYSTEM_VALUE_GLOBAL_INVOCATION_INDEXSYSTEM_VALUE_GLOBAL_GROUP_SIZESYSTEM_VALUE_BARYCENTRIC_PERSP_PIXELSYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLESYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROIDSYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHWSYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXELSYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROIDSYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLESYSTEM_VALUE_BARYCENTRIC_PULL_MODELSYSTEM_VALUE_RAY_WORLD_DIRECTIONSYSTEM_VALUE_RAY_OBJECT_ORIGINSYSTEM_VALUE_RAY_OBJECT_DIRECTIONSYSTEM_VALUE_RAY_OBJECT_TO_WORLDSYSTEM_VALUE_RAY_WORLD_TO_OBJECTSYSTEM_VALUE_RAY_GEOMETRY_INDEXSYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONSSYSTEM_VALUE_MESH_VIEW_INDICESSYSTEM_VALUE_FRAG_SHADING_RATESYSTEM_VALUE_FRAG_INVOCATION_COUNTSYSTEM_VALUE_COALESCED_INPUT_COUNTPP=P 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*)[%ld][[*]bindless centroid sample patch invariant per_view per_primitive ray_query abcdefghijklmnopxyzw compactnearestclamp_to_edgeclamprepeatrepeat_mirroreddecl_var %s%s%s%s%s%s%s%s%s %s highplowp%s %s (%s%s) (%s%s, %u, %u)%s = null = { = { %s, %s, %s } = &%sinline-UBOtexturetexture-bufferimage-bufferSSBOaccel-structinput-atttexture+sampler = %s.nsw.nuw = deref_var = deref_array = deref_struct = deref_cast = deref_ptr_as_array | %s) // &%*scall %s @%swrmask=reduction_op=%satomic_op=fcmpxchginc_wrapdec_wrapimage_dim=%simage_array=%sformat=%sdesc_type=%ssrc_type=dest_type=swizzle_mask=((id & %d) | %d) ^ %dmem_semantics=ACQACQ|REL|AVAILABLE|VISIBLEmem_modes=%s=%sio location=%s slots=%u per_primitive explicit_strict dualsrc fbfetch perview mediump high_16bits invariant high_dvec2 no_varying no_sysval_output gs_streams(%s%c=%uxfb%s(components=%u..%ucomponent=%u buffer=%u offset=%urounding_mode=ruray_query_value=intersection_typeintersection_tintersection_instance_idintersection_geometry_indexintersection_primitive_indexintersection_barycentricsintersection_front_faceintersection_object_to_worldintersection_world_to_objecttminworld_ray_directionworld_ray_originresource_intel=bindlesspushablesampler-embeddedaccess=matrix_layout=row_majorcol_majorcmat_signed=Resultalu_op=%s%s=%d // %stex txb txl txd txf txf_ms txf_ms_fb txf_ms_mcs_intel txs lod tg4 query_levels texture_samples samples_identical tex (pre-dispatchable) fragment_fetch_amd fragment_mask_fetch_amd sampler_descriptor_amd lod_bias_agx hdr_dim_nv tex_type_nv (backend1)(backend2)(coord)(projector)(comparator)(offset)(bias)(lod)(min_lod)(ms_index)(ms_mcs_intel)(ddx)(ddy)(texture_deref)(sampler_deref)(texture_offset)(sampler_offset)(texture_handle)(sampler_handle)(plane), implicit lod, %u (gather_component), { (%i, %i), (%i, %i) } (offsets), %u (texture), %u (sampler), texture non-uniform, sampler non-uniform, sparse = load_const goto b%ugoto b%u if else b%u = undefined = phi b%u: ; con%s block b%u: // preds: , succs: b%u %*s// preds: %*s// succs: // flatten // don't flatten // divergent always taken} else { loop { } continue { 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QP_YSUMTGSA}ȍwǍqƍkvkAcquireFullScreenExclusiveModeEXTvkAcquireImageANDROIDvkAcquireNextImage2KHRvkAcquireNextImageKHRvkAcquirePerformanceConfigurationINTELvkAcquireProfilingLockKHRvkAllocateCommandBuffersvkAllocateDescriptorSetsvkAllocateMemoryvkBeginCommandBuffervkBindAccelerationStructureMemoryNVvkBindBufferMemoryvkBindBufferMemory2vkBindBufferMemory2KHRvkBindImageMemoryvkBindImageMemory2vkBindImageMemory2KHRvkBindOpticalFlowSessionImageNVvkBindVideoSessionMemoryKHRvkBuildAccelerationStructuresKHRvkBuildMicromapsEXTvkCmdBeginConditionalRenderingEXTvkCmdBeginDebugUtilsLabelEXTvkCmdBeginQueryvkCmdBeginQueryIndexedEXTvkCmdBeginRenderPassvkCmdBeginRenderPass2vkCmdBeginRenderPass2KHRvkCmdBeginRenderingvkCmdBeginRenderingKHRvkCmdBeginTransformFeedbackEXTvkCmdBeginVideoCodingKHRvkCmdBindDescriptorBufferEmbeddedSamplers2EXTvkCmdBindDescriptorBufferEmbeddedSamplersEXTvkCmdBindDescriptorBuffersEXTvkCmdBindDescriptorSetsvkCmdBindDescriptorSets2KHRvkCmdBindIndexBuffervkCmdBindIndexBuffer2KHRvkCmdBindInvocationMaskHUAWEIvkCmdBindPipelinevkCmdBindPipelineShaderGroupNVvkCmdBindShadersEXTvkCmdBindShadingRateImageNVvkCmdBindTransformFeedbackBuffersEXTvkCmdBindVertexBuffersvkCmdBindVertexBuffers2vkCmdBindVertexBuffers2EXTvkCmdBlitImagevkCmdBlitImage2vkCmdBlitImage2KHRvkCmdBuildAccelerationStructureNVvkCmdBuildAccelerationStructuresIndirectKHRvkCmdBuildAccelerationStructuresKHRvkCmdBuildMicromapsEXTvkCmdClearAttachmentsvkCmdClearColorImagevkCmdClearDepthStencilImagevkCmdControlVideoCodingKHRvkCmdCopyAccelerationStructureKHRvkCmdCopyAccelerationStructureNVvkCmdCopyAccelerationStructureToMemoryKHRvkCmdCopyBuffervkCmdCopyBuffer2vkCmdCopyBuffer2KHRvkCmdCopyBufferToImagevkCmdCopyBufferToImage2vkCmdCopyBufferToImage2KHRvkCmdCopyImagevkCmdCopyImage2vkCmdCopyImage2KHRvkCmdCopyImageToBuffervkCmdCopyImageToBuffer2vkCmdCopyImageToBuffer2KHRvkCmdCopyMemoryIndirectNVvkCmdCopyMemoryToAccelerationStructureKHRvkCmdCopyMemoryToImageIndirectNVvkCmdCopyMemoryToMicromapEXTvkCmdCopyMicromapEXTvkCmdCopyMicromapToMemoryEXTvkCmdCopyQueryPoolResultsvkCmdCuLaunchKernelNVXvkCmdDebugMarkerBeginEXTvkCmdDebugMarkerEndEXTvkCmdDebugMarkerInsertEXTvkCmdDecodeVideoKHRvkCmdDecompressMemoryIndirectCountNVvkCmdDecompressMemoryNVvkCmdDispatchvkCmdDispatchBasevkCmdDispatchBaseKHRvkCmdDispatchIndirectvkCmdDrawvkCmdDrawClusterHUAWEIvkCmdDrawClusterIndirectHUAWEIvkCmdDrawIndexedvkCmdDrawIndexedIndirectvkCmdDrawIndexedIndirectCountvkCmdDrawIndexedIndirectCountAMDvkCmdDrawIndexedIndirectCountKHRvkCmdDrawIndirectvkCmdDrawIndirectByteCountEXTvkCmdDrawIndirectCountvkCmdDrawIndirectCountAMDvkCmdDrawIndirectCountKHRvkCmdDrawMeshTasksEXTvkCmdDrawMeshTasksIndirectCountEXTvkCmdDrawMeshTasksIndirectCountNVvkCmdDrawMeshTasksIndirectEXTvkCmdDrawMeshTasksIndirectNVvkCmdDrawMeshTasksNVvkCmdDrawMultiEXTvkCmdDrawMultiIndexedEXTvkCmdEncodeVideoKHRvkCmdEndConditionalRenderingEXTvkCmdEndDebugUtilsLabelEXTvkCmdEndQueryvkCmdEndQueryIndexedEXTvkCmdEndRenderPassvkCmdEndRenderPass2vkCmdEndRenderPass2KHRvkCmdEndRenderingvkCmdEndRenderingKHRvkCmdEndTransformFeedbackEXTvkCmdEndVideoCodingKHRvkCmdExecuteCommandsvkCmdExecuteGeneratedCommandsNVvkCmdFillBuffervkCmdInsertDebugUtilsLabelEXTvkCmdNextSubpassvkCmdNextSubpass2vkCmdNextSubpass2KHRvkCmdOpticalFlowExecuteNVvkCmdPipelineBarriervkCmdPipelineBarrier2vkCmdPipelineBarrier2KHRvkCmdPreprocessGeneratedCommandsNVvkCmdPushConstantsvkCmdPushConstants2KHRvkCmdPushDescriptorSet2KHRvkCmdPushDescriptorSetKHRvkCmdPushDescriptorSetWithTemplate2KHRvkCmdPushDescriptorSetWithTemplateKHRvkCmdResetEventvkCmdResetEvent2vkCmdResetEvent2KHRvkCmdResetQueryPoolvkCmdResolveImagevkCmdResolveImage2vkCmdResolveImage2KHRvkCmdSetAlphaToCoverageEnableEXTvkCmdSetAlphaToOneEnableEXTvkCmdSetAttachmentFeedbackLoopEnableEXTvkCmdSetBlendConstantsvkCmdSetCheckpointNVvkCmdSetCoarseSampleOrderNVvkCmdSetColorBlendAdvancedEXTvkCmdSetColorBlendEnableEXTvkCmdSetColorBlendEquationEXTvkCmdSetColorWriteEnableEXTvkCmdSetColorWriteMaskEXTvkCmdSetConservativeRasterizationModeEXTvkCmdSetCoverageModulationModeNVvkCmdSetCoverageModulationTableEnableNVvkCmdSetCoverageModulationTableNVvkCmdSetCoverageReductionModeNVvkCmdSetCoverageToColorEnableNVvkCmdSetCoverageToColorLocationNVvkCmdSetCullModevkCmdSetCullModeEXTvkCmdSetDepthBiasvkCmdSetDepthBias2EXTvkCmdSetDepthBiasEnablevkCmdSetDepthBiasEnableEXTvkCmdSetDepthBoundsvkCmdSetDepthBoundsTestEnablevkCmdSetDepthBoundsTestEnableEXTvkCmdSetDepthClampEnableEXTvkCmdSetDepthClipEnableEXTvkCmdSetDepthClipNegativeOneToOneEXTvkCmdSetDepthCompareOpvkCmdSetDepthCompareOpEXTvkCmdSetDepthTestEnablevkCmdSetDepthTestEnableEXTvkCmdSetDepthWriteEnablevkCmdSetDepthWriteEnableEXTvkCmdSetDescriptorBufferOffsets2EXTvkCmdSetDescriptorBufferOffsetsEXTvkCmdSetDeviceMaskvkCmdSetDeviceMaskKHRvkCmdSetDiscardRectangleEXTvkCmdSetDiscardRectangleEnableEXTvkCmdSetDiscardRectangleModeEXTvkCmdSetEventvkCmdSetEvent2vkCmdSetEvent2KHRvkCmdSetExclusiveScissorEnableNVvkCmdSetExclusiveScissorNVvkCmdSetExtraPrimitiveOverestimationSizeEXTvkCmdSetFragmentShadingRateEnumNVvkCmdSetFragmentShadingRateKHRvkCmdSetFrontFacevkCmdSetFrontFaceEXTvkCmdSetLineRasterizationModeEXTvkCmdSetLineStippleEXTvkCmdSetLineStippleEnableEXTvkCmdSetLineStippleKHRvkCmdSetLineWidthvkCmdSetLogicOpEXTvkCmdSetLogicOpEnableEXTvkCmdSetPatchControlPointsEXTvkCmdSetPerformanceMarkerINTELvkCmdSetPerformanceOverrideINTELvkCmdSetPerformanceStreamMarkerINTELvkCmdSetPolygonModeEXTvkCmdSetPrimitiveRestartEnablevkCmdSetPrimitiveRestartEnableEXTvkCmdSetPrimitiveTopologyvkCmdSetPrimitiveTopologyEXTvkCmdSetProvokingVertexModeEXTvkCmdSetRasterizationSamplesEXTvkCmdSetRasterizationStreamEXTvkCmdSetRasterizerDiscardEnablevkCmdSetRasterizerDiscardEnableEXTvkCmdSetRayTracingPipelineStackSizeKHRvkCmdSetRenderingAttachmentLocationsKHRvkCmdSetRenderingInputAttachmentIndicesKHRvkCmdSetRepresentativeFragmentTestEnableNVvkCmdSetSampleLocationsEXTvkCmdSetSampleLocationsEnableEXTvkCmdSetSampleMaskEXTvkCmdSetScissorvkCmdSetScissorWithCountvkCmdSetScissorWithCountEXTvkCmdSetShadingRateImageEnableNVvkCmdSetStencilCompareMaskvkCmdSetStencilOpvkCmdSetStencilOpEXTvkCmdSetStencilReferencevkCmdSetStencilTestEnablevkCmdSetStencilTestEnableEXTvkCmdSetStencilWriteMaskvkCmdSetTessellationDomainOriginEXTvkCmdSetVertexInputEXTvkCmdSetViewportvkCmdSetViewportShadingRatePaletteNVvkCmdSetViewportSwizzleNVvkCmdSetViewportWScalingEnableNVvkCmdSetViewportWScalingNVvkCmdSetViewportWithCountvkCmdSetViewportWithCountEXTvkCmdSubpassShadingHUAWEIvkCmdTraceRaysIndirect2KHRvkCmdTraceRaysIndirectKHRvkCmdTraceRaysKHRvkCmdTraceRaysNVvkCmdUpdateBuffervkCmdUpdatePipelineIndirectBufferNVvkCmdWaitEventsvkCmdWaitEvents2vkCmdWaitEvents2KHRvkCmdWriteAccelerationStructuresPropertiesKHRvkCmdWriteAccelerationStructuresPropertiesNVvkCmdWriteBufferMarker2AMDvkCmdWriteBufferMarkerAMDvkCmdWriteMicromapsPropertiesEXTvkCmdWriteTimestampvkCmdWriteTimestamp2vkCmdWriteTimestamp2KHRvkCompileDeferredNVvkCopyAccelerationStructureKHRvkCopyAccelerationStructureToMemoryKHRvkCopyImageToImageEXTvkCopyImageToMemoryEXTvkCopyMemoryToAccelerationStructureKHRvkCopyMemoryToImageEXTvkCopyMemoryToMicromapEXTvkCopyMicromapEXTvkCopyMicromapToMemoryEXTvkCreateAccelerationStructureKHRvkCreateAccelerationStructureNVvkCreateBuffervkCreateBufferCollectionFUCHSIAvkCreateBufferViewvkCreateCommandPoolvkCreateComputePipelinesvkCreateCuFunctionNVXvkCreateCuModuleNVXvkCreateDeferredOperationKHRvkCreateDescriptorPoolvkCreateDescriptorSetLayoutvkCreateDescriptorUpdateTemplatevkCreateDescriptorUpdateTemplateKHRvkCreateEventvkCreateFencevkCreateFramebuffervkCreateGraphicsPipelinesvkCreateImagevkCreateImageViewvkCreateIndirectCommandsLayoutNVvkCreateMicromapEXTvkCreateOpticalFlowSessionNVvkCreatePipelineCachevkCreatePipelineLayoutvkCreatePrivateDataSlotvkCreatePrivateDataSlotEXTvkCreateQueryPoolvkCreateRayTracingPipelinesKHRvkCreateRayTracingPipelinesNVvkCreateRenderPassvkCreateRenderPass2vkCreateRenderPass2KHRvkCreateSamplervkCreateSamplerYcbcrConversionvkCreateSamplerYcbcrConversionKHRvkCreateSemaphorevkCreateShaderModulevkCreateShadersEXTvkCreateSharedSwapchainsKHRvkCreateSwapchainKHRvkCreateValidationCacheEXTvkCreateVideoSessionKHRvkCreateVideoSessionParametersKHRvkDebugMarkerSetObjectNameEXTvkDebugMarkerSetObjectTagEXTvkDeferredOperationJoinKHRvkDestroyAccelerationStructureKHRvkDestroyAccelerationStructureNVvkDestroyBuffervkDestroyBufferCollectionFUCHSIAvkDestroyBufferViewvkDestroyCommandPoolvkDestroyCuFunctionNVXvkDestroyCuModuleNVXvkDestroyDeferredOperationKHRvkDestroyDescriptorPoolvkDestroyDescriptorSetLayoutvkDestroyDescriptorUpdateTemplatevkDestroyDescriptorUpdateTemplateKHRvkDestroyDevicevkDestroyEventvkDestroyFencevkDestroyFramebuffervkDestroyImagevkDestroyImageViewvkDestroyIndirectCommandsLayoutNVvkDestroyMicromapEXTvkDestroyOpticalFlowSessionNVvkDestroyPipelinevkDestroyPipelineCachevkDestroyPipelineLayoutvkDestroyPrivateDataSlotvkDestroyPrivateDataSlotEXTvkDestroyQueryPoolvkDestroyRenderPassvkDestroySamplervkDestroySamplerYcbcrConversionvkDestroySamplerYcbcrConversionKHRvkDestroySemaphorevkDestroyShaderEXTvkDestroyShaderModulevkDestroySwapchainKHRvkDestroyValidationCacheEXTvkDestroyVideoSessionKHRvkDestroyVideoSessionParametersKHRvkDeviceWaitIdlevkDisplayPowerControlEXTvkEndCommandBuffervkExportMetalObjectsEXTvkFlushMappedMemoryRangesvkFreeCommandBuffersvkFreeDescriptorSetsvkFreeMemoryvkGetAccelerationStructureBuildSizesKHRvkGetAccelerationStructureDeviceAddressKHRvkGetAccelerationStructureHandleNVvkGetAccelerationStructureMemoryRequirementsNVvkGetAccelerationStructureOpaqueCaptureDescriptorDataEXTvkGetAndroidHardwareBufferPropertiesANDROIDvkGetBufferCollectionPropertiesFUCHSIAvkGetBufferDeviceAddressvkGetBufferDeviceAddressEXTvkGetBufferDeviceAddressKHRvkGetBufferMemoryRequirementsvkGetBufferMemoryRequirements2vkGetBufferMemoryRequirements2KHRvkGetBufferOpaqueCaptureAddressvkGetBufferOpaqueCaptureAddressKHRvkGetBufferOpaqueCaptureDescriptorDataEXTvkGetCalibratedTimestampsEXTvkGetCalibratedTimestampsKHRvkGetDeferredOperationMaxConcurrencyKHRvkGetDeferredOperationResultKHRvkGetDescriptorEXTvkGetDescriptorSetHostMappingVALVEvkGetDescriptorSetLayoutBindingOffsetEXTvkGetDescriptorSetLayoutHostMappingInfoVALVEvkGetDescriptorSetLayoutSizeEXTvkGetDescriptorSetLayoutSupportvkGetDescriptorSetLayoutSupportKHRvkGetDeviceAccelerationStructureCompatibilityKHRvkGetDeviceBufferMemoryRequirementsvkGetDeviceBufferMemoryRequirementsKHRvkGetDeviceFaultInfoEXTvkGetDeviceGroupPeerMemoryFeaturesvkGetDeviceGroupPeerMemoryFeaturesKHRvkGetDeviceGroupPresentCapabilitiesKHRvkGetDeviceGroupSurfacePresentModes2EXTvkGetDeviceGroupSurfacePresentModesKHRvkGetDeviceImageMemoryRequirementsvkGetDeviceImageMemoryRequirementsKHRvkGetDeviceImageSparseMemoryRequirementsvkGetDeviceImageSparseMemoryRequirementsKHRvkGetDeviceImageSubresourceLayoutKHRvkGetDeviceMemoryCommitmentvkGetDeviceMemoryOpaqueCaptureAddressvkGetDeviceMemoryOpaqueCaptureAddressKHRvkGetDeviceMicromapCompatibilityEXTvkGetDeviceProcAddrvkGetDeviceQueuevkGetDeviceQueue2vkGetDeviceSubpassShadingMaxWorkgroupSizeHUAWEIvkGetDynamicRenderingTilePropertiesQCOMvkGetEncodedVideoSessionParametersKHRvkGetEventStatusvkGetFenceFdKHRvkGetFenceStatusvkGetFenceWin32HandleKHRvkGetFramebufferTilePropertiesQCOMvkGetGeneratedCommandsMemoryRequirementsNVvkGetImageDrmFormatModifierPropertiesEXTvkGetImageMemoryRequirementsvkGetImageMemoryRequirements2vkGetImageMemoryRequirements2KHRvkGetImageOpaqueCaptureDescriptorDataEXTvkGetImageSparseMemoryRequirementsvkGetImageSparseMemoryRequirements2vkGetImageSparseMemoryRequirements2KHRvkGetImageSubresourceLayoutvkGetImageSubresourceLayout2EXTvkGetImageSubresourceLayout2KHRvkGetImageViewAddressNVXvkGetImageViewHandleNVXvkGetImageViewOpaqueCaptureDescriptorDataEXTvkGetLatencyTimingsNVvkGetMemoryAndroidHardwareBufferANDROIDvkGetMemoryFdKHRvkGetMemoryFdPropertiesKHRvkGetMemoryHostPointerPropertiesEXTvkGetMemoryRemoteAddressNVvkGetMemoryWin32HandleKHRvkGetMemoryWin32HandleNVvkGetMemoryWin32HandlePropertiesKHRvkGetMemoryZirconHandleFUCHSIAvkGetMemoryZirconHandlePropertiesFUCHSIAvkGetMicromapBuildSizesEXTvkGetPastPresentationTimingGOOGLEvkGetPerformanceParameterINTELvkGetPipelineCacheDatavkGetPipelineExecutableInternalRepresentationsKHRvkGetPipelineExecutablePropertiesKHRvkGetPipelineExecutableStatisticsKHRvkGetPipelineIndirectDeviceAddressNVvkGetPipelineIndirectMemoryRequirementsNVvkGetPipelinePropertiesEXTvkGetPrivateDatavkGetPrivateDataEXTvkGetQueryPoolResultsvkGetQueueCheckpointData2NVvkGetQueueCheckpointDataNVvkGetRayTracingCaptureReplayShaderGroupHandlesKHRvkGetRayTracingShaderGroupHandlesKHRvkGetRayTracingShaderGroupHandlesNVvkGetRayTracingShaderGroupStackSizeKHRvkGetRefreshCycleDurationGOOGLEvkGetRenderAreaGranularityvkGetRenderingAreaGranularityKHRvkGetSamplerOpaqueCaptureDescriptorDataEXTvkGetScreenBufferPropertiesQNXvkGetSemaphoreCounterValuevkGetSemaphoreCounterValueKHRvkGetSemaphoreFdKHRvkGetSemaphoreWin32HandleKHRvkGetSemaphoreZirconHandleFUCHSIAvkGetShaderBinaryDataEXTvkGetShaderInfoAMDvkGetShaderModuleCreateInfoIdentifierEXTvkGetShaderModuleIdentifierEXTvkGetSwapchainCounterEXTvkGetSwapchainGrallocUsage2ANDROIDvkGetSwapchainGrallocUsageANDROIDvkGetSwapchainImagesKHRvkGetSwapchainStatusKHRvkGetValidationCacheDataEXTvkGetVideoSessionMemoryRequirementsKHRvkImportFenceFdKHRvkImportFenceWin32HandleKHRvkImportSemaphoreFdKHRvkImportSemaphoreWin32HandleKHRvkImportSemaphoreZirconHandleFUCHSIAvkInitializePerformanceApiINTELvkInvalidateMappedMemoryRangesvkLatencySleepNVvkMapMemoryvkMapMemory2KHRvkMergePipelineCachesvkMergeValidationCachesEXTvkQueueBeginDebugUtilsLabelEXTvkQueueBindSparsevkQueueEndDebugUtilsLabelEXTvkQueueInsertDebugUtilsLabelEXTvkQueueNotifyOutOfBandNVvkQueuePresentKHRvkQueueSetPerformanceConfigurationINTELvkQueueSignalReleaseImageANDROIDvkQueueSubmitvkQueueSubmit2vkQueueSubmit2KHRvkQueueWaitIdlevkRegisterDeviceEventEXTvkRegisterDisplayEventEXTvkReleaseFullScreenExclusiveModeEXTvkReleasePerformanceConfigurationINTELvkReleaseProfilingLockKHRvkReleaseSwapchainImagesEXTvkResetCommandBuffervkResetCommandPoolvkResetDescriptorPoolvkResetEventvkResetFencesvkResetQueryPoolvkResetQueryPoolEXTvkSetBufferCollectionBufferConstraintsFUCHSIAvkSetBufferCollectionImageConstraintsFUCHSIAvkSetDebugUtilsObjectNameEXTvkSetDebugUtilsObjectTagEXTvkSetDeviceMemoryPriorityEXTvkSetEventvkSetHdrMetadataEXTvkSetLatencyMarkerNVvkSetLatencySleepModeNVvkSetLocalDimmingAMDvkSetPrivateDatavkSetPrivateDataEXTvkSignalSemaphorevkSignalSemaphoreKHRvkTransitionImageLayoutEXTvkTrimCommandPoolvkTrimCommandPoolKHRvkUninitializePerformanceApiINTELvkUnmapMemoryvkUnmapMemory2KHRvkUpdateDescriptorSetWithTemplatevkUpdateDescriptorSetWithTemplateKHRvkUpdateDescriptorSetsvkUpdateVideoSessionParametersKHRvkWaitForFencesvkWaitForPresentKHRvkWaitSemaphoresvkWaitSemaphoresKHRvkWriteAccelerationStructuresPropertiesKHRvkWriteMicromapsPropertiesEXT̡CC$݀k:rQ.Ìgg'=RdE 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41**vkAcquireDrmDisplayEXTvkAcquireWinrtDisplayNVvkAcquireXlibDisplayEXTvkCreateDevicevkCreateDisplayModeKHRvkEnumerateDeviceExtensionPropertiesvkEnumerateDeviceLayerPropertiesvkEnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHRvkGetDisplayModeProperties2KHRvkGetDisplayModePropertiesKHRvkGetDisplayPlaneCapabilities2KHRvkGetDisplayPlaneCapabilitiesKHRvkGetDisplayPlaneSupportedDisplaysKHRvkGetDrmDisplayEXTvkGetPhysicalDeviceCalibrateableTimeDomainsEXTvkGetPhysicalDeviceCalibrateableTimeDomainsKHRvkGetPhysicalDeviceCooperativeMatrixPropertiesKHRvkGetPhysicalDeviceCooperativeMatrixPropertiesNVvkGetPhysicalDeviceDirectFBPresentationSupportEXTvkGetPhysicalDeviceDisplayPlaneProperties2KHRvkGetPhysicalDeviceDisplayPlanePropertiesKHRvkGetPhysicalDeviceDisplayProperties2KHRvkGetPhysicalDeviceDisplayPropertiesKHRvkGetPhysicalDeviceExternalBufferPropertiesvkGetPhysicalDeviceExternalBufferPropertiesKHRvkGetPhysicalDeviceExternalFencePropertiesvkGetPhysicalDeviceExternalFencePropertiesKHRvkGetPhysicalDeviceExternalImageFormatPropertiesNVvkGetPhysicalDeviceExternalSemaphorePropertiesvkGetPhysicalDeviceExternalSemaphorePropertiesKHRvkGetPhysicalDeviceFeaturesvkGetPhysicalDeviceFeatures2vkGetPhysicalDeviceFeatures2KHRvkGetPhysicalDeviceFormatPropertiesvkGetPhysicalDeviceFormatProperties2vkGetPhysicalDeviceFormatProperties2KHRvkGetPhysicalDeviceFragmentShadingRatesKHRvkGetPhysicalDeviceImageFormatPropertiesvkGetPhysicalDeviceImageFormatProperties2vkGetPhysicalDeviceImageFormatProperties2KHRvkGetPhysicalDeviceMemoryPropertiesvkGetPhysicalDeviceMemoryProperties2vkGetPhysicalDeviceMemoryProperties2KHRvkGetPhysicalDeviceMultisamplePropertiesEXTvkGetPhysicalDeviceOpticalFlowImageFormatsNVvkGetPhysicalDevicePresentRectanglesKHRvkGetPhysicalDevicePropertiesvkGetPhysicalDeviceProperties2vkGetPhysicalDeviceProperties2KHRvkGetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHRvkGetPhysicalDeviceQueueFamilyPropertiesvkGetPhysicalDeviceQueueFamilyProperties2vkGetPhysicalDeviceQueueFamilyProperties2KHRvkGetPhysicalDeviceScreenPresentationSupportQNXvkGetPhysicalDeviceSparseImageFormatPropertiesvkGetPhysicalDeviceSparseImageFormatProperties2vkGetPhysicalDeviceSparseImageFormatProperties2KHRvkGetPhysicalDeviceSupportedFramebufferMixedSamplesCombinationsNVvkGetPhysicalDeviceSurfaceCapabilities2EXTvkGetPhysicalDeviceSurfaceCapabilities2KHRvkGetPhysicalDeviceSurfaceCapabilitiesKHRvkGetPhysicalDeviceSurfaceFormats2KHRvkGetPhysicalDeviceSurfaceFormatsKHRvkGetPhysicalDeviceSurfacePresentModes2EXTvkGetPhysicalDeviceSurfacePresentModesKHRvkGetPhysicalDeviceSurfaceSupportKHRvkGetPhysicalDeviceToolPropertiesvkGetPhysicalDeviceToolPropertiesEXTvkGetPhysicalDeviceVideoCapabilitiesKHRvkGetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHRvkGetPhysicalDeviceVideoFormatPropertiesKHRvkGetPhysicalDeviceWaylandPresentationSupportKHRvkGetPhysicalDeviceWin32PresentationSupportKHRvkGetPhysicalDeviceXcbPresentationSupportKHRvkGetPhysicalDeviceXlibPresentationSupportKHRvkGetRandROutputDisplayEXTvkGetWinrtDisplayNVvkReleaseDisplayEXT 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Q N M L k  g Q e 5 f D d * c  b  `  \  Z  [  Y  X  W w  8 * k\ g# e f d cb   `\Z[Y{XrWi   UPQOPNML ! # '?΍ ~ύ!# '֍ ׍!+#; 'x !_^]   k؍\ՍMԍӍҍэ  r Ѝ͍̍qˍfʍ[ɍPf \ H 3%c`_^] '΍   ύ ! #* 'g֍ ׍ ! # 'a  ؍ Ս ԍ Ӎ ҍ э y ZЍ K͍ <̍ ˍ ʍ ɍ f   c d _ ^` h #ō D 3^ T !b 4č 1k] J  ta $Í 0V%s[]%s[%u]%sx%ua%uB%sACCUMULATORcoopmat<%s, %s, %u, %u, %s>geometrykerneltessellation controltessellation evaluationraygenany hitclosest hitmissFSTCSTESRGENRAHITRCHITRMISSRINTRCALLVARYING_SLOT_PRIMITIVE_COUNTVARYING_SLOT_CULL_PRIMITIVEVARYING_SLOT_TASK_COUNTVARYING_SLOT_PRIMITIVE_INDICESAlevel=%hhu, "level": "%hhu"BLITCOPYCCS_AMBIGUATECCS_COLOR_CLEARCCS_PARTIAL_RESOLVECCS_RESOLVEHIZ_AMBIGUATEHIZ_CLEARHIZ_RESOLVEMCS_AMBIGUATEMCS_COLOR_CLEARMCS_PARTIAL_RESOLVESLOW_COLOR_CLEARSLOW_DEPTH_CLEAR"count": "%u"instance_count=%u, "instance_count": "%u""draw_count": "%u"max_draw_count=%u, "max_draw_count": "%u"group=%ux%ux%u +ccs_flush+eop+pss_stall+udp_flush+cs_stall+depth_stall+pb_stall+ic_inval+tex_inval+vf_inval+const_inval+state_inval+tile_flush+rt_flush+hdc_flush+dc_flush+depth_flushLIBGL_DEBUGquietlibGL: .confINTEL_GPU_TRACEPOINT executableexecutable_regexpsha1application_name_matchapplication_versions/proc/curproc/exe/proc/curproc/filescreenkernel_driverengine_name_matchengine_versionsCan't allocate parser buffer.queue_annotationcmd_buffer_annotationwrite_buffer_markergenerate_drawsgenerate_commandsquery_clear_blorpquery_clear_csquery_copy_csquery_copy_shaderdraw_indirect_byte_countdraw_indexed_indirectdraw_indexed_indirect_countdraw_meshdraw_mesh_indirectdraw_mesh_indirect_counttrace_copytrace_copy_cbas_buildapplicationdriconfengineoptionop=%s, width=%u, height=%u, samples=%u, blorp_pipe=%s, dst_fmt=%s, src_fmt=%s, predicated=%hhu, "op": "%s", "width": "%u", "height": "%u", "samples": "%u", "blorp_pipe": "%s", "dst_fmt": "%s", "src_fmt": "%s", "predicated": "%hhu""unstructured": "group=%ux%ux%u"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s : %s%s%s%s%s%s%s "unstructured": "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s : %s%s%s%s%s%s%s"Warning in %s line %d, column %d: unknown application attribute: %s.Warning in %s line %d, column %d: Invalid executable_regexp="%s".Warning in %s line %d, column %d: Incorrect sha1 application attributeWarning in %s line %d, column %d: Invalid application_name_match="%s".Warning in %s line %d, column %d: Failed to parse application_versions range="%s".Warning in %s line %d, column %d: nested elements.Warning in %s line %d, column %d: attributes specified on element.Warning in %s line %d, column %d: should be inside .Warning in %s line %d, column %d: nested elements.Warning in %s line %d, column %d: unknown device attribute: %s.Warning in %s line %d, column %d: illegal screen number: %s.Warning in %s line %d, column %d: should be inside .Warning in %s line %d, column %d: nested or elements.Warning in %s line %d, column %d: should be inside .Warning in %s line %d, column %d: Invalid engine_name_match="%s".Warning in %s line %d, column %d: Failed to parse engine_versions range="%s".Warning in %s line %d, column %d: